[go: up one dir, main page]

DE69613751D1 - Statische Halbleiterspeicheranordnung mit Impulsgenerator zur Verminderung des Schreibzyklus - Google Patents

Statische Halbleiterspeicheranordnung mit Impulsgenerator zur Verminderung des Schreibzyklus

Info

Publication number
DE69613751D1
DE69613751D1 DE69613751T DE69613751T DE69613751D1 DE 69613751 D1 DE69613751 D1 DE 69613751D1 DE 69613751 T DE69613751 T DE 69613751T DE 69613751 T DE69613751 T DE 69613751T DE 69613751 D1 DE69613751 D1 DE 69613751D1
Authority
DE
Germany
Prior art keywords
reduce
memory device
semiconductor memory
pulse generator
write cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69613751T
Other languages
English (en)
Other versions
DE69613751T2 (de
Inventor
Teruyuki Uchihira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69613751D1 publication Critical patent/DE69613751D1/de
Application granted granted Critical
Publication of DE69613751T2 publication Critical patent/DE69613751T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69613751T 1995-04-24 1996-04-23 Statische Halbleiterspeicheranordnung mit Impulsgenerator zur Verminderung des Schreibzyklus Expired - Fee Related DE69613751T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12312895A JP3180883B2 (ja) 1995-04-24 1995-04-24 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69613751D1 true DE69613751D1 (de) 2001-08-16
DE69613751T2 DE69613751T2 (de) 2002-05-08

Family

ID=14852878

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69613751T Expired - Fee Related DE69613751T2 (de) 1995-04-24 1996-04-23 Statische Halbleiterspeicheranordnung mit Impulsgenerator zur Verminderung des Schreibzyklus

Country Status (5)

Country Link
US (1) US5712824A (de)
EP (1) EP0740303B1 (de)
JP (1) JP3180883B2 (de)
KR (1) KR100227294B1 (de)
DE (1) DE69613751T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6483754B1 (en) * 2001-05-16 2002-11-19 Lsi Logic Corporation Self-time scheme to reduce cycle time for memories
KR100555534B1 (ko) * 2003-12-03 2006-03-03 삼성전자주식회사 인액티브 위크 프리차아징 및 이퀄라이징 스킴을 채용한프리차아지 회로, 이를 포함하는 메모리 장치 및 그프리차아지 방법
JP2006331568A (ja) * 2005-05-27 2006-12-07 Nec Electronics Corp 外部クロック同期半導体記憶装置及びその制御方法
US10127979B2 (en) 2016-03-11 2018-11-13 Western Digital Technologies, Inc. Memory cell located pulse generator
US10381408B2 (en) 2016-03-24 2019-08-13 Western Digital Technologies, Inc. Method to fabricate discrete vertical transistors

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143592A (en) * 1980-04-09 1981-11-09 Toshiba Corp Semiconductor memory device
US4608669A (en) * 1984-05-18 1986-08-26 International Business Machines Corporation Self contained array timing
JPH0766665B2 (ja) * 1988-03-31 1995-07-19 株式会社東芝 半導体記憶装置
US5228003A (en) * 1988-04-15 1993-07-13 Seiko Epson Corporation Semiconductor memory
US5404327A (en) * 1988-06-30 1995-04-04 Texas Instruments Incorporated Memory device with end of cycle precharge utilizing write signal and data transition detectors
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
US5386150A (en) * 1991-11-20 1995-01-31 Fujitsu Limited Tracking pulse generator and RAM with tracking precharge pulse generator

Also Published As

Publication number Publication date
EP0740303B1 (de) 2001-07-11
JPH08297978A (ja) 1996-11-12
KR960039000A (ko) 1996-11-21
KR100227294B1 (ko) 1999-11-01
EP0740303A3 (de) 1998-12-16
JP3180883B2 (ja) 2001-06-25
DE69613751T2 (de) 2002-05-08
EP0740303A2 (de) 1996-10-30
US5712824A (en) 1998-01-27

Similar Documents

Publication Publication Date Title
DE69428652D1 (de) Halbleiterspeicher mit mehreren Banken
DE69324508D1 (de) DRAM mit integrierten Registern
DE68926370D1 (de) Warmwasserversorgungsgerät
DE69424448D1 (de) Kraftstoffzufuhreinrichtung
KR950703763A (ko) 고장허용 한계를 갖는 메모리장치
DE69229104D1 (de) Stroboskopische Signale in Halbleiterspeicheranordnungen
DE69123666D1 (de) Halbleiterspeicheranordnung
DE4407210B4 (de) Halbleiterspeicherbauelementaufbau
DE69322311D1 (de) Halbleiterspeicheranordnung
DE69125671D1 (de) Halbleiter-Speicherbauteil
DE69600591D1 (de) Halbleiterspeicheranordnung
DE69427443D1 (de) Halbleiterspeicheranordnung
DE69432846D1 (de) Halbleiterspeichereinrichtung
DE69123379D1 (de) Halbleiterspeichervorrichtung
DE69322725D1 (de) Halbleiterspeicheranordnung
DE69127155D1 (de) Halbleiterspeicheranordnung
KR940011024U (ko) 반도체 메모리 장치
DE69329011D1 (de) Halbleiterspeichergerät mit Prüfmodus
DE69828021D1 (de) Halbleiterspeicheranordnung mit mehreren Banken
DE69128819D1 (de) Halbleiterspeicheranordnung
DE69324470D1 (de) Halbleiterspeicheranordnung
DE69125734D1 (de) Halbleiterspeicheranordnung
DE69427107D1 (de) Halbleiterspeicheranordnung
DE69613751D1 (de) Statische Halbleiterspeicheranordnung mit Impulsgenerator zur Verminderung des Schreibzyklus
DE69129524D1 (de) Gerät zur Speicheradressierung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee