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DE69507653D1 - Verfahren und Vorrichtung zur Erzeugung von Tests für elektronische Karten - Google Patents

Verfahren und Vorrichtung zur Erzeugung von Tests für elektronische Karten

Info

Publication number
DE69507653D1
DE69507653D1 DE69507653T DE69507653T DE69507653D1 DE 69507653 D1 DE69507653 D1 DE 69507653D1 DE 69507653 T DE69507653 T DE 69507653T DE 69507653 T DE69507653 T DE 69507653T DE 69507653 D1 DE69507653 D1 DE 69507653D1
Authority
DE
Germany
Prior art keywords
electronic cards
test
test set
card
generating tests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69507653T
Other languages
English (en)
Other versions
DE69507653T2 (de
Inventor
Denis Bougourd
Etienne Hourdin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Airbus Group SAS
Original Assignee
Airbus Group SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Airbus Group SAS filed Critical Airbus Group SAS
Application granted granted Critical
Publication of DE69507653D1 publication Critical patent/DE69507653D1/de
Publication of DE69507653T2 publication Critical patent/DE69507653T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31912—Tester/user interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/865—Monitoring of software

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69507653T 1994-03-25 1995-03-10 Verfahren und Vorrichtung zur Erzeugung von Tests für elektronische Karten Expired - Lifetime DE69507653T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9403940A FR2717902B1 (fr) 1994-03-25 1994-03-25 Procédé et dispositif d'élaboration de tests de cartes électroniques.

Publications (2)

Publication Number Publication Date
DE69507653D1 true DE69507653D1 (de) 1999-03-18
DE69507653T2 DE69507653T2 (de) 1999-06-17

Family

ID=9461716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69507653T Expired - Lifetime DE69507653T2 (de) 1994-03-25 1995-03-10 Verfahren und Vorrichtung zur Erzeugung von Tests für elektronische Karten

Country Status (3)

Country Link
EP (1) EP0674265B1 (de)
DE (1) DE69507653T2 (de)
FR (1) FR2717902B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7065464B2 (en) 2001-05-18 2006-06-20 Rohde & Schwarz Gmbh & Co. Kg Measuring device with dialog control occuring via dialog windows and corresponding method
DE10130943A1 (de) * 2001-05-18 2002-11-21 Rohde & Schwarz Signalgenerator mit Anzeigeeinrichtung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3942082A1 (de) * 1989-12-20 1991-06-27 Rustige Hayno Dipl Ing Caq - system computer-unterstuetztes-pruefsystem
JPH04211871A (ja) * 1990-05-02 1992-08-03 Toshiba Corp 論理設計の検証支援システム
EP0508619A2 (de) * 1991-04-11 1992-10-14 Hewlett-Packard Company Stimulus-Schnittstelle mit bidirektionalem Sockel für einen Logiksimulator

Also Published As

Publication number Publication date
DE69507653T2 (de) 1999-06-17
FR2717902A1 (fr) 1995-09-29
FR2717902B1 (fr) 1996-05-31
EP0674265A1 (de) 1995-09-27
EP0674265B1 (de) 1999-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition