DE69504412T2 - Grayscale control device for LCD for active addressing with split bit storage - Google Patents

Description

The present invention relates to two devices for driving a liquid crystal display in a gradual manner. It is of a simple matrix type using STN (super twisted nematic) liquid crystals, etc. The multi-line selection method or the like can also be used.

The simple matrix type liquid crystal display panel uses a liquid crystal layer held between a plurality of row electrodes and a plurality of column electrodes which define a pixel matrix. Conventionally, the liquid crystal display panel is operated by the voltage averaging method. In this method, the row electrodes are sequentially selected one by one and at the same time, a data signal indicating an on/off state is given to the column electrodes. Therefore, a voltage is applied to each pixel so that a high voltage is applied for a certain time (1/N time), while a constant bias voltage is applied for the remaining time ((N-1)/N) within an image transfer period in which all row electrodes (N rows) are selected once. If the liquid crystal material used has a relatively slow response time, the luminance of the pixel changes according to an effective amplitude of the applied voltage waveform within an image transfer period. However, if the image transfer frequency is lowered while the line pitch number is increased, the difference between the image transfer period and the response time of the liquid crystal becomes small, so that the liquid crystal responds to each pulse applied to it, and thus flickering of the luminance is generated, called "image response phenomenon", which would lower a contrast.

Recently, the multiple line selection method has been developed to solve the problem of the image response phenomenon, as disclosed in, for example, Japanese Patent Laid-Open No. 5-100642 (EP-A-2,3-507061). Unlike the conventional single line selection, the multiple line selection method is characterized in that a plurality of line electrodes are selected simultaneously to increase the image frequency and thus suppress the image response phenomenon. The line electrodes are not selected one by one but are selected simultaneously in a group, which requires a special technique for achieving a free image display. Namely, the original pixel data is processed one by one by calculation to apply a column signal to the column electrode. More specifically, a group of line signals represented by a set of orthogonal functions are applied to the line electrodes in a group sequential manner in each selection period. On the other hand, a dot product calculation is then carried out between the set of orthogonal functions and a selected set of pixel data, and the column signals whose Voltage levels determined by the calculation results are applied to the column electrodes synchronously with the group sequential scanning during each selection period.

The multi-line selection method can be extended to a grayscale display. The grayscale can be realized by various modulation modes. For example, pulse modulation mode and frame rate modulation mode can be easily combined with the multi-line selection method as taught in Japanese Patent Laid-Open No. 5-100642. In this method, the given pixel data has a multi-bit form for determining a gradation level. In the dot product calculation between the set of orthogonal functions and the set of pixel data, the set of pixel data is divided into two bit units, which are then further processed by the dot product calculation to generate column signal components corresponding to the bit units concerned. Further, the column signal components are sequentially arranged according to the order of the bit units within a selection period to form a composite column signal which is applied to the column electrodes. Now each bit unit is subjected to either pulse modulation or frame rate modulation to realize the grayscale display.

The pixel data is written once into an image memory before the dot product calculation. The image memory is required for each dot unit of pixel data in the grayscale display. If the gradation height is set to fine and the number of pixels is increased, a large image memory column is required, which would hinder the practical application of the liquid crystal display screen.

In the conventional way, all pixel data is written to the frame buffer in each frame period. The bit of the Pixel data subjected to pulse modulation must be read out for every frame to perform dot product calculation. On the other hand, the bit subjected to frame rate modulation may not be required for every frame. For example, in the case where halftone (1/2 gradation) is performed by frame rate modulation, every other frame is thinned out. Accordingly, in the prior art, the bit subjected to frame rate modulation is selected from the frame memory in a reading stage. However, in such a method, all bits of the pixel data are stored in the frame memory in a writing stage, which means no saving in the capacity of the frame memory.

In view of the above problem in the prior art, an object of the invention is to save image storage capacity when performing the gradual driving by the multi-line selection. To achieve the above object, the invention provides an apparatus for gradual driving a liquid crystal display in which a liquid crystal layer is held between a plurality of row electrodes and a plurality of column electrodes to define a pixel matrix according to pixel data composed of a plurality of bits while using both pulse modulation and frame rate modulation. The driving device includes first means for applying a group of row signals represented by a set of orthogonal functions to the row electrodes by group-sequential scanning over an image at each selection period, and second means for successively performing the dot product calculation between the set of orthogonal functions and a set of pixel data and applying a plurality of column signals to the column electrodes, the voltage levels being determined by the results of the dot product calculation at each selection period in synchronism with the group-sequential scanning. The second means includes a frame memory, dot product calculation means and driving means. The frame memory stores an image of the pixel data divided into each bit. The dot product calculation means reads out a set of the stored pixel data in a partial bit form from the frame memory to perform the dot product calculation so as to generate a column signal component corresponding to each partial bit. The driving means arranges a column signal component subject to pulse modulation and another column signal component subject to frame sequence modulation within a selection period to compose the column signal applied to the column electrode. Further characteristically, there is provided memory control means for controlling the writing of the pixel data into the frame memory so that a partial bit subject to pulse modulation is written into the frame memory for each frame while another partial bit subject to frame sequence modulation is written into the frame memory at a selected frame specified by the frame sequence modulation.

The present invention is not limited to the multi-line selection mode, but can be generally applied to all driving devices of the liquid crystal display panel which require writing the pixel data into an image memory. Namely, the invention generally relates to an apparatus for gradual driving of a liquid crystal display panel in which a liquid crystal layer is held between a plurality of row electrodes and a plurality of column electrodes to define a pixel matrix according to a pixel data composed of a plurality of bits, while applying frame rate modulation to at least one bit of the pixel data. The apparatus basically comprises first means for applying a line signal to the row electrode to carry out sequential scanning thereof, and second Means for applying a column signal having a voltage level determined by the pixel data to the column electrodes in synchronism with the sequential scanning. The second means includes a frame memory for storing an image of the pixel data divided into the individual bits, drive means for reading out the stored pixel data in divided bit form, and processing the read pixel data to form the column signal applied to the column electrodes. Further characteristically, the second means is provided with memory control means for controlling the writing of the pixel data into the frame memory so that a partial bit of the pixel data subject to the frame sequence modulation is written into a selected frame memory at a selected frame specified by the frame sequence modulation, while the remaining partial bits are written into the frame memory at each frame.

The gradated driving apparatus of the present invention performs the gray shading driving of the liquid crystal display screen according to the pixel data having the multi-bit structure while applying the pulse modulation and the frame rate modulation. For example, the pulse modulation is applied to a high-order bit and the frame rate modulation is applied to a low-order bit, thereby reducing the overall system clock frequency of the gradated driving apparatus, which is advantageous for circuit design. In this case, with respect to the bit subjected to the frame rate modulation, the writing of the pixel data on an image specified by the image modulation is carried out in batches, so that image storage capacity is saved. For example, in the case where the frame rate of 1/2 gradation is applied to the low-order bit, the pixel data for calculating the column signal is required for every other image. Therefore, the writing of the low-order bit of the pixel data is only once for every two frames, so that the capacity of the frame memory can be effectively reduced. As can be understood from the above, the data writing method of the present invention is not limited to the multi-line selection mode, but can be applied to all types of the stepped driving device which performs frame rate modulation after storing the pixel data in the frame memory. For example, in the voltage averaging mode where the row electrodes are sequentially selected one after another, the present invention is used when the display is operated in a divided mode so that a screen is divided into upper and lower sections, because such a driving mode requires a frame memory.

Fig. 1 is a block diagram of a structural example of a graded driving apparatus for a liquid crystal display panel according to the present invention.

Fig. 2 is a flow chart showing a multi-line selection operation of the driving device of Fig. 1.

Fig. 3 is a table diagram showing the grayscale processing operation of the driving device of Fig. 1.

Fig. 4 is a waveform diagram showing the grayscale editing operation.

Fig. 5 is a waveform diagram showing an example of the orthogonal functions applied in the driving device of Fig. 1.

Fig. 6 is a block diagram showing a detailed structure of the memory control means included in the driving device of Fig. 1.

Fig. 7 is a block diagram showing a detailed structure of a selector switch included in the circuit of Fig. 6.

Fig. 8 is a circuit diagram showing a detailed structure of a selection unit according to Fig. 7.

Preferred embodiments of the invention will be described in detail below with reference to the drawings. Fig. 1 is a block diagram of a structural example of a graded driving device for a liquid crystal display panel according to the present invention. As shown in the figure, the graded driving device according to the present invention is connected to a liquid crystal display panel 1 of a simple matrix type. This liquid crystal display panel 1 has a flat panel structure where a liquid crystal layer is arranged between a plurality of row electrodes 2 and a plurality of column electrodes 3. The liquid crystal layer may be made of STN liquid crystals. The present device gradedly drives the liquid crystal display panel 1 according to pixel data having a multi-bit form while using the pulse modulation and the frame rate modulation.

The stepped driving device is provided with a vertical driver 4 connected to the row electrodes 2 to drive them. Further, a horizontal driver 5 is connected to the column electrodes 3 to drive them. The present device further includes an image memory 6, orthogonal function generating means 7, and dot product calculating means 8. The image memory 6 contains input pixel data for each image. The pixel data indicates the density of pixels at intersection points. between the row electrodes 2 and the column electrodes 3. According to the invention, the pixel data has a multi-bit structure effective to determine a gradation level of the pixel density. In this connection, the image memory 6 has a multiple of bit planes corresponding to the bit units of the pixel data.

The orthogonal function generating means 7 generates a set of orthogonal functions which are at right angles to each other and applies these functions in the appropriate combination pattern to the vertical driver 4. The vertical driver 4 applies a set of line signals represented by the orthogonal functions to the row electrodes 2 in each selection period by group sequential scanning. Thus, the orthogonal function generating means 7 and the vertical driver 4 constitute the first means mentioned above.

The stepped driving device comprises second means consisting of the dot product calculation means 8 and a voltage level circuit 12 in addition to the image memory 6 and the horizontal driver 5. The second means sequentially performs the dot product calculation between a set of orthogonal functions and a set of pixel data and applies to the column electrodes 3 column signals having the voltage levels determined by the results of the dot product calculation in each selection period in synchronization with the group sequential scanning. More specifically, the product calculation means 8 reads out the set of pixel data in split-bit form from the image memory 6 and performs the dot product calculations to generate a column signal component corresponding to one split bit. The horizontal driver 5 sequentially arranges a multiple of the column signal components depending on either the pulse modulation or the frame rate modulation within a selection period to compose the column signal applied to the column electrodes 3. The voltage level circuit 12 provides the voltage levels required to generate the column signals. Furthermore, the voltage level circuit 12 sends predetermined voltage levels to the vertical driver 4. The vertical driver 4 selects the appropriate voltage levels according to the orthogonal functions to shape the row signals applied to the row electrodes 2.

The present step-by-step driving device has memory control means 10 as a characteristic element. This memory control means 10 carries out control of writing the pixel data into the frame memory 6. Bits subject to pulse modulation are written into the frame memory at every frame period, while other bits subject to frame rate modulation are written into the frame memory at a preselected frame period specified by the frame rate. The device includes a synchronous circuit 9 and drive control means 11 in addition to the memory control means 10. The synchronous circuit 9 synchronizes a reading timing of the pixel data from the frame memory 6 with a signal transmission timing from the orthogonal function generating means 7. The group sequential scanning is repeated several times within one frame to obtain the desired image. The synchronous circuit 9 also carries out timing control of the memory control means 10. As described earlier, the memory control means 10 controls the writing/reading of the pixel data with respect to the split-bit plane image storage means 6. The driver control means 11 operates under the control of the synchronous circuit 9 to send a clock signal to the vertical driver 4 and the horizontal driver 5.

As already described, the frame memory 6 stores the pixel data composed of multiple bits in separate bit planes to perform the gray scale shading by the pulse modulation and the frame rate modulation. The dot product calculation means 8 splits the set of pixel data into respective bit units, which are then subjected to the dot product calculation with a set of orthogonal functions to produce the corresponding column signal component. The horizontal driver 5 sequentially arranges the column signal components from higher order bits associated with wider pulses to lower order bits associated with narrower pulses in a selection period to form the column signal, which is then applied to the column electrode 3. In this memory, one column signal component of the higher order bit is subjected to the pulse modulation while another column signal component of the lower order bit is subjected to the frame rate modulation.

Hereinafter, the operation of the gray scale driving device of Fig. 1 will be described in detail. First, a detailed description will be given of the multi-row selection method in which, for example, seven rows of row electrodes are simultaneously selected. Fig. 2 is a waveform diagram of the seven-row selection drive. Row signals F1(t) - F8(t) are applied to the corresponding row electrodes, while column signals G1(t) - G3(t) are applied to the corresponding column electrodes. The row signal F is formed according to the Walsh function which is the complete orthogonal function in (0, 1) where "0" means - Vr and "1" means +Vr, while V0 is set in the non-selection period. Further, the voltage level V0 of the non-selection period is set to 0 V. The upper seven rows of row electrodes from the top are selected as a group, so that the group sequential scanning is carried out downwards. The scanning is repeated eight times, to perform a first half cycle corresponding to a set period of the Walsh function. In a next period, a second half cycle is performed while inverting the polarity of the signal so that a DC component drops out. In a further next period, the combination pattern of the set orthogonal function is shifted laterally to form the row signals applied to the row electrodes 2. The lateral shift may be omitted if desired.

On the other hand, the column signal applied to each column electrode is obtained by the dot product calculation of the pixel data Iij (i denotes a row number of the matrix and j denotes a column number of the matrix). Assuming that the pixel data is not in the multi-bit form but in the one-bit form, Iij = -1 is set for an on-pixel and Iij = +1 is set for an off-pixel. In such a case, the column signal Gj(t) applied to each column electrode is determined by performing the following product calculation:

[Equation]

In the calculation, the row signal has a zero level in the non-select period, so the summation of the above equation only has an effect on the selected rows. Accordingly, in the seven-row select mode, the column signal can have an eight-voltage level. This is because the column signal requires that the voltage levels be equal to the number of selected rows plus one. These voltage levels are provided by the voltage level circuit 12, as shown in Fig. 1.

The above dot product calculation is applied to the pixel data of the one-bit form having no gray shade. In the gradation display according to the present invention, the pixel data has the multi-bit structure. In such a case, the dot product calculation is performed as follows. Referring to Fig. 3, the pixel data of a three-bit form is input to display a gray shaded image with eight gradation levels. As shown in Fig. 3, the pixel data has a second bit of a higher order, a first bit of an intermediate order, and a tenth bit of a lower order. Each bit takes a binary value of "0" or "1". When all three bits have the same value of "0", the lowest 0th gradation level is set. When all three bits have the value of "1", the highest seventh gradation level is set. Desired gray levels can be generated depending on the value of each bit. The dot product calculation is performed on the pixel data of the three-bit form so that the pixel data is divided into bit units. First, the dot product calculation is performed between the set of the second-order bits and the set of the orthogonal functions to generate a column signal component corresponding to the highest-order bit. Next, the similar dot product calculation is performed between the set of the first-order bits and the same set of the orthogonal functions to generate another column signal component corresponding to the middle-order bit. Lastly, the similar dot product calculation is performed between the set of the 0-order bits and the same set of the orthogonal functions to generate another column signal component corresponding to the lower-order bit.

Fig. 4 gives an example of a column signal that is composed of a series arrangement of the column signal components. In the graph in Fig. 4, the horizontal axis a time t, and the vertical axis indicates the voltage level of the column signal G(t). The column signal G(t) takes eight voltage levels V₁-V₈ according to the results of the dot product calculation. The column signal G(t) includes the three column signal components g2, g1 and g0 corresponding to the three bits included in the pixel data within one selection period Δt. The first component g2 is obtained by the dot product calculation for the set of the second bits corresponding to the higher order. The next component g1 corresponds to the middle order, the last component g0 corresponds to the lower order.

In this embodiment, the pulse modulation is applied to the higher and middle orders, while the frame rate modulation is applied to the lower order. The component g2 corresponding to the high order has the largest pulse width P2. The next component g1 has a pulse width P1 which is half of P2. As for the column signal component g0 of the lower order, its pulse width P0 can be set to half of P1 when the pulse modulation is applied. Here, however, the present embodiment applies the frame rate modulation so that the component g0 has the pulse width identical to the pulse width P1 of the middle component g1. By this arrangement, the column signal component g0 is output alternately every other frame so that an output pulse width thereof is set to half of the pulse width P0 by averaging by the frames, thereby realizing the 1/2 gradation. In this way, the frame rate modulation is applied to the bit of the lower order to avoid an excessively narrow pulse width to eliminate a focus in the circuit design. The invention is not limited to the embodiment described, but the frame rate modulation can be freely applied to any desired bit order. Furthermore, a 1/4 gradation can be implemented instead of the 1/2 gradation. In such a case, one image out of four is thinned out.

Fig. 5 is a waveform diagram showing the Walsh functions. For example, in the case of the seven-line selection driver, the second through eighth Walsh functions are selected as a set to form the line signals. As can be seen from a comparison between Figs. 2 and 5, the line signal F1(t) corresponds to the second Walsh function at the top of the page. The second Walsh function is high in a first half of a period, and then goes low in the second half of the one period.

Accordingly, the line signal F1(t) is composed of a pulse sequence (1, 1, 1, 1, 0, 0, 0, 0). Similarly, the line signal F2(t) corresponds to the third Walsh function and has a pulse sequence (1, 1, 0, 0, 0, 0, 1, 1). Furthermore, the line signal F3(t) corresponds to the fourth Walsh function and has a pulse sequence (1, 1, 0, 0, 1, 1, 0, 0). As can be seen from the description, the set of line signals applied to a group of line electrodes is represented by an appropriate combination pattern due to the orthogonal relationships. In the case of Fig. 2, the set of row signals F8(t) - F14(t) having the same combination pattern is applied to a next group of row electrodes. Similarly, the set of row signals is applied to the third and subsequent row electrode groups according to the same combination pattern.

Next, a detailed description will be given of the practical construction of the memory control means 10 shown in Fig. 1 with reference to Fig. 6. The circuit construction of Fig. 6 includes three latch circuits LAT1, LAT2 and LAT3 for the multiplexers MX1, MX2, MX3 and MX4, a selector SLT and a flip-flop FF.

The input pixel data covers three primary color elements and is in three-bit form. The pixel data of the red color element consists of a low bit R0, a middle bit R1 and a high bit R2. R0 is subject to image modulation while R1 and R2 are subject to pulse modulation. Similarly, the pixel data of the green color element is composed of three bits G0, G1 and G2, and the pixel data of the blue color element is composed of three bits B0, B1 and B2. These pixel data are input bit by bit through IC pads PAD and input buffer INBUF. Furthermore, various clock signals are input from the pads and the input buffers for operation control. These clock signals include a signal FLM that switches between low and high at every frame. Furthermore, a pair of clock signals SHCK and LATCLK are used for the operation control of the latch circuits LATt, LAT2 and LAT3. Furthermore, the clock signals WAD-A and WAD-B are used for the operation control of the multiplexers MX1, MX2 and MX3. Furthermore, a pair of clock signals GCK0 and GCK1 are used for the operation control of the multiplexer MX4.

The description then proceeds to the operation with reference to Fig. 6. LAT1 latches R0, R1 and R2, each consisting of 8 bits. The eight bits of R0 are sequentially output as IDR1. The eight bits of R1 are sequentially output as DR2. The eight bits of R2 are sequentially output as DR3. Similarly, LAT2 latches G0, G1 and G2, each consisting of 8 bits. The eight bits of G0 are sequentially output as IDG1, the eight bits of G1 are sequentially output as DG2, and the eight bits of G2 are sequentially output as DG3. Similarly, LAT3 latches B0, B1 and B2, each consisting of 8 bits. bits. The eight bits from B0 are output sequentially as IDB1, the eight bits from B1 are output sequentially as DB2, and the eight bits from B2 are output sequentially as DB3.

The multiplexers MX1, MX2 and MX3 rearrange the eight bits of the pixel data into a sequence RGBRGB... corresponding to an RGB arrangement of the column electrodes. The multiplexer MX1 performs the RGB rearrangement for the low-order bit, the multiplexer MX2 performs the RGB rearrangement for the middle-order bit, and the multiplexer MX3 performs the RGB rearrangement for the high-order bit. In this embodiment, the middle-order DR2, DG2 and DB2 from the corresponding LAT1, LAT2 and LAT3 are input to MX2 as they are. Furthermore, the high-order DR3, DG3 and DB3 are also input to MX3 as they are. On the other hand, as seen from the figure, IDR1, IDG1 and IDB1 are converted by the selector SLT into DR1, DG1 and DB1 respectively and then input to the corresponding multiplexer MX1. The selector SLT is controlled by the flip-flop FF. The FF converts the signal FLM which inverts every frame into a signal SEL which inverts every other frame. The signal SEL is sent to a selection terminal of the selector SLT. The selector SLT operates in response to SEL and samples IDR1, IDG1 and IDB1 every other frame to provide DR1, DG1 and DB1 respectively. Thus, the selection for the low-order bits subject to frame rate modulation is performed at the write stage, effectively saving the storage capacity of the frame memory.

In this way, MX1 causes the rearrangement of the least significant bit into the RGB order to generate a data DGS1 that is fed into the multiplexer MX4. In a similar way, MX2 causes the rearrangement of the middle significant bit into the RGB order to generate a data DGS2 that is also fed into the multiplexer MX4. if input to the multiplexer MX4. Furthermore, MX3 causes the high-order bit to be rearranged into the RGB order to generate a data DGS3, which is also input to the multiplexer MX4. MX4 is operatively controlled by the clock signal pair GCK0 and GCK1 to rearrange the input data into the high-order, medium-order and low-order bit order, the result of which is output via the output buffer OUTBUF and the pads PAD. The data rearranged into the high-order, medium-order and low-order bit order is output to the outside as WD0, WD1, WD2, WD3, WD4, WD5, WD6 and WD7.

Fig. 7 is a block diagram giving a structural example of the selector SLT shown in Fig. 6. As shown in the figure, the selector SLT consists of the selector units SLT1, SLT2 and SLT3, which are provided for IDR1, IDG1 and IDB1, respectively.

Lastly, Fig. 8 is a circuit diagram giving a structural example of the selection unit shown in Fig. 7. In the figure, eight AND gate elements AND are provided corresponding to eight bits of input data IN0-IN7. Each AND has an input terminal A for receiving the selection signal SEL which alternates between high and low every other frame, and another input terminal B for receiving the corresponding input data IN. An odd number of AND circuits receives a positive input at the terminal A, while an even number of AND circuits receives a negative input at the terminal A. Accordingly, an odd number of input data IN0, IN2, IN4 and IN6 give the corresponding AND to first and second frames when SEL is high. On the other hand, even numbers of input data IN1, IN3, IN5 and IN7 give the corresponding AND to the third frame when SEL is low. In this way, in the present embodiment, half of the pixel data of the low-order bits every other frame. In other words, the frame rate modulation is performed alternately between odd and even rows of column electrodes, thus producing an averaged variation in the applied voltage across the frames.

As described above, the bit data subject to frame rate modulation is written into the frame memory at a frame period specified by the frame rate modulation, while the remaining bit data is written into the frame memory at every frame period, thereby advantageously saving frame memory capacity.

Claims (2)

1. An apparatus for stepwise driving a liquid crystal display in which a liquid crystal layer is held between a plurality of row electrodes and a plurality of column electrodes to define a pixel matrix according to a pixel data composed of a plurality of bits while using both pulse modulation and frame rate modulation, the apparatus comprising: First means (7, 4) for applying a group of line signals represented by a set of orthogonal functions to the line electrodes by group sequential scanning over an image at each selection period; and second means for successively performing the dot product calculation between the set of orthogonal functions and a set of pixel data and for applying a plurality of column signals to the column electrodes, the voltage levels being determined by the results of the dot product calculation at each selection period synchronously with the group sequential sampling, in which the second means comprises an image memory (6) for storing an image of the pixel data divided into each bit, dot product calculation means (8) for reading out a set of the stored pixel data in a partial bit form from the image memory to perform the dot product calculation so as to generate a column signal component corresponding to each partial bit, drive means (5) for arranging a column signal component subject to pulse modulation and another column signal component subject to frame sequence modulation within a selection period for composing the column signal applied to the column electrode, and memory control means (10) for controlling writing of the pixel data into the image memory so that a partial bit subject to pulse modulation is written into the image memory for each image while another partial bit subject to frame sequence modulation is written into the image memory at a selected image specified by the frame sequence modulation. 2. An apparatus for gradual driving of a liquid crystal display screen in which a liquid crystal layer is held between a plurality of row electrodes and a plurality of column electrodes to define a pixel matrix according to pixel data composed of a plurality of bits while applying frame rate modulation to at least one bit of the pixel data, the apparatus comprising: first means for applying a line signal to the line electrode for carrying out sequential scanning thereof; and second means for applying a column signal having a voltage level determined by the pixel data to the column electrodes in synchronism with the sequential scanning, wherein the second means comprises a frame memory for storing an image of the pixel data divided into the individual bits, drive means for reading out the stored pixel data in divided bit form and processing the read pixel data to form the column signal applied to the column electrodes, and memory control means for controlling the writing of the pixel data into the frame memory so that a partial bit of the pixel data subject to the frame sequence modulation is written into the frame memory at a selected frame specified by the frame sequence modulation, while the remaining partial bits are written into the frame memory at each frame.