CN113889046B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN113889046B CN113889046B CN202010629258.3A CN202010629258A CN113889046B CN 113889046 B CN113889046 B CN 113889046B CN 202010629258 A CN202010629258 A CN 202010629258A CN 113889046 B CN113889046 B CN 113889046B
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- 238000000034 method Methods 0.000 title claims abstract description 17
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- 239000010409 thin film Substances 0.000 claims description 11
- 230000002688 persistence Effects 0.000 abstract description 4
- 230000000007 visual effect Effects 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 16
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- 210000002858 crystal cell Anatomy 0.000 description 8
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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Abstract
The invention provides a display panel, a driving method thereof and a display device, wherein a pixel unit of the display panel is provided with a data storage circuit, a time sequence control circuit in the display panel controls a gray scale control circuit to output a public voltage, a gray scale driving voltage and a high-frequency pulse gray scale voltage to the pixel unit of the display panel, and the pixel unit respectively represents the gray scale driving voltage, the high-frequency pulse gray scale voltage and a gray scale level corresponding to the public voltage according to a data signal stored in the data storage circuit, so that different gray scale display is realized by using visual persistence of the high-frequency gray scale voltage, and the gray scale degree of the display panel is increased.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
Liquid Crystal Display (LCD) devices are widely used in smart wear, mobile terminals, and the like, and as users continuously make new requirements for brightness, color saturation, and resolution of LCD Display devices, power consumption of LCD Display devices increases accordingly. In order to reduce the power consumption of the LCD display device, a new type of low power consumption LCD display technology, i.e. a Pixel In Pixel (MIP) display technology, is beginning to be applied to the low power consumption LCD display device. The types of memories provided in each pixel of the LCD display device may be classified into an SRAM and a DRAM, and the memories store data voltages input to the pixels for a certain time for display, and do not need to perform a data voltage writing operation in a frame period, which can reduce the amount of data to be transmitted, thereby preventing power consumption caused by multiple data voltage writing. MIP displays are commonly used for wearable and portable devices that require little update for long endurance, such as car navigators, watches, bracelets, etc.
In the related art, the MIP technology is generally implemented using a pixel circuit as shown in fig. 1, which includes a data writing circuit 101, a data storage circuit 102, and a display driving circuit 103. Wherein Gate is scanning line, data is Data line, common electrode of liquid crystal cell LC and common voltage V COM A line, the pixel electrode of the liquid crystal cell LC is connected to a common voltage V COM Same-phase and same-phase voltage FRP signal line and V COM An inverted reverse voltage XFRP signal line. The data write circuit 101 writes a binary data signal (logic "1" or logic "0") into the data storage circuit 102 under the control of the scan signal, and the display drive circuit 103 determines that the voltage across the liquid crystal cell LC is V under the control of the binary data signal stored in the data storage circuit 102 COM And V FRP Or is V COM And V XFRP Therefore, each pixel can represent 2 gray scales, and the types of display colors are few, which may not meet the requirements of users. The commonly used scheme for increasing the color depth in the liquid crystal driving circuit is a multi-gray scale driving method, and for the display device adopting the MIP technology, each gray scale is matched with a common voltage V with the polarity reversed in each predetermined period COM In phase voltage V FRP And a reverse voltage V XFRP It is also necessary to reverse the polarity every predetermined period, which requires the introduction of a corresponding voltage output circuit and digital control circuit, significantly increasing circuit complexity, cost and power consumption, limiting the ultra-low power consumption characteristics of the MIP display device.
Disclosure of Invention
Embodiments of the present disclosure provide a display panel, a driving method thereof, and a display device.
According to an aspect of the embodiments of the present disclosure, there is provided a display panel including a plurality of pixel units, a scan driving circuit which supplies scan signals to scan lines of the plurality of pixel units, a data driving circuit which supplies data signals to data lines of the plurality of pixel units, a timing control circuit, and a gray scale control circuit, wherein:
the pixel driving circuit of the pixel unit includes a data storage circuit that selectively stores the data signal output onto the data line according to the scan signal;
the timing control circuit is configured to control the scan driving circuit, the data driving circuit, and the grayscale control circuit;
the gray scale control circuit is connected with the plurality of pixel units and is configured to output a common voltage, a gray scale driving voltage and a high-frequency pulse gray scale voltage to the plurality of pixel units under the control of the time sequence control circuit;
the plurality of pixel units respectively represent the gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the public voltage according to the data signals stored by the data storage circuit.
For example, the gray scale control circuit comprises a main control circuit, and a frequency divider, a ring counter and a data selector which are connected in sequence; wherein,
the main control circuit is connected with the data selector and is configured to accept the control of the time sequence control circuit and output the gray scale driving voltage to the plurality of pixel units and the data selector;
the frequency divider is connected with the sequential control circuit and is configured to receive the output of the sequential control circuit with a period T CLK Is divided into a clock signal of period T CLK a/N clock signal for outputting a clock signal inputted as the ring counter;
the ring counter is configured to receive the period T CLK a/N clock signal and outputting a ring counter output signal;
the data selector is configured to receive the grayscale driving voltage and the ring counter output signal, and output the high-frequency pulse grayscale voltage to the plurality of pixel units;
wherein N is an integer greater than 1. For example, the pixel driving circuit of the pixel unit further includes a data writing circuit and a display driving circuit, the data writing circuit, the data storage circuit and the display driving circuit are connected in sequence, and the common electrode of the pixel unit is configured to input the common voltage;
the data writing circuit is connected with the data line and is configured to selectively write the data signal output to the data line into the data storage circuit according to the scanning signal;
the display driving circuit is connected with the pixel electrode of the pixel unit, is configured to input the gray scale driving voltage and the high-frequency pulse gray scale voltage, and controls the pixel unit to respectively express gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the common voltage according to the data signal stored by the data storage circuit.
For example, the common voltage is a period T COM The alternating voltage of (c);
the gray scale driving voltage has a period T in phase with the AC voltage COM Has a period T of inversion of the first voltage and the alternating voltage COM Of the first voltage.
For example, the ring counter is further configured to have the period T CLK Counting every M pulses of a/N clock signal and outputting a duty ratio of 1/M and a period of T CLK A ring counter output signal of/(M.N);
the selection control end of the data selector receives the period T CLK A ring counter of N, a data input control end of the data selector receives the first voltage and the second voltage, and an output end of the data selector outputs a duty ratio of 1/M and a period of T CLK V (M.N) of the high-frequency pulse gray-scale voltage, the duty ratio is 1/M, and the period is T CLK The high-frequency pulse gray scale voltage of the/N comprises a first high-frequency pulse gray scale voltage and a second high-frequency pulse gray scale voltage which are opposite in phase;
the first voltage, the second voltage, the first high-frequency pulse gray scale voltage and the second high-frequency pulse gray scale voltage are respectively input to the pixel driving circuits of the pixel units through a first voltage signal line, a second voltage signal line, a first high-frequency pulse gray scale voltage signal line and a second high-frequency pulse gray scale voltage signal line;
wherein M is an integer greater than 1.
For example, a data buffer is further connected between the data selector and the plurality of pixel units, and the data buffer is configured to temporarily store and output the high-frequency pulse gray scale voltage to the plurality of pixel units.
For example, the data lines include first and second data lines configured to transmit first and second data signals included in the data signals, respectively;
the data storage circuit includes a first storage circuit and a second storage circuit configured to store the first data signal and the second data signal, respectively;
the display driving circuit comprises a first switching element, a second switching element, a third switching element, a fourth switching element, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, wherein the control electrodes of the switching elements of the display driving circuit are sequentially and correspondingly connected with the output ends of the AND gates of the display driving circuit, the first electrodes of the switching elements of the display driving circuit are respectively connected to a first voltage signal line, a second voltage signal line, a first high-frequency pulse gray scale voltage signal line and a second high-frequency pulse gray scale voltage signal line, and the second electrodes of the switching elements of the display driving circuit are connected with the pixel electrodes of the pixel units;
the data writing circuit includes a fifth switching element and a sixth switching element, a control pole of each switching element of the data writing circuit is connected to the scan line, a first pole of the fifth switching element is connected to the first data line, a second pole of the fifth switching element is connected to the input terminal of the first storage circuit, a first pole of the sixth switching element is connected to the second data line, and a second pole of the sixth switching element is connected to the input terminal of the second storage circuit;
the input end of the first storage circuit is connected with the first input end of the first AND gate and the first input end of the second AND gate, and the output end of the first storage circuit is connected with the first input end of the third AND gate and the first input end of the fourth AND gate;
the input end of the second storage circuit is connected with the second input end of the first AND gate and the second input end of the third AND gate, and the output end of the second storage circuit is connected with the second input end of the second AND gate and the second input end of the fourth AND gate.
For example, the first storage circuit includes a first inverter and a second inverter; the input end of the first inverter and the output end of the second inverter are connected with the second pole of the fifth switching element, the first input end of the first AND gate and the first input end of the second AND gate, and the output end of the first inverter and the input end of the second inverter are connected with the first input end of the third AND gate and the first input end of the fourth AND gate;
the second storage circuit comprises a third inverter and a fourth inverter; the input end of the third phase inverter and the output end of the fourth phase inverter are connected with the second pole of the sixth switching element, the second input end of the first AND gate and the second input end of the third AND gate, and the output end of the third phase inverter and the input end of the fourth phase inverter are connected with the second input end of the second AND gate and the second input end of the fourth AND gate.
For example, the first inverter and the second inverter include TFT inverters, each of the switching elements is a thin film transistor, and each of the and gates includes a thin film transistor and a gate; or,
the first inverter and the second inverter comprise CMOS inverters, each switch element is a CMOS transistor, and each AND gate comprises a CMOS AND gate.
According to an aspect of the embodiments of the present disclosure, there is provided a driving method of the above display panel, wherein:
providing scanning signals to scanning lines of the plurality of pixel units through the scanning driving circuit;
providing data signals to data lines of the plurality of pixel units through the data driving circuit;
selectively storing the data signal output onto the data line in a data storage circuit of each of the plurality of pixel units according to the scan signal;
and the gray scale control circuit outputs a public voltage, a gray scale driving voltage and a high-frequency pulse gray scale voltage to the pixel units, and the pixel units respectively express gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the public voltage according to data signals stored by the data storage circuit.
For example, the gray scale control circuit comprises a main control circuit, and a frequency divider, a ring counter and a data selector which are connected in sequence; the main control circuit is connected with the data selector, and the frequency divider is connected with the sequential control circuit; the driving method includes:
generating a duty ratio of 1/M and a period of T by the ring counter CLK The ring counter of the/N outputs a signal and inputs the signal to the data selector;
outputting the duty ratio of 1/M and the period of T by the data selector CLK The high-frequency pulse gray scale voltage of the/N comprises a first high-frequency pulse gray scale voltage and a second high-frequency pulse gray scale voltage which are opposite in phase;
and controlling the pixel units to respectively express the gray scale levels corresponding to the first voltage, the second voltage, the first high-frequency pulse gray scale voltage, the second high-frequency pulse gray scale voltage and the common voltage according to the data signals stored by the data storage circuit.
According to an aspect of the embodiments of the present disclosure, there is provided a display device, including the display panel as described above.
Drawings
Fig. 1 shows a schematic diagram of a pixel circuit in the related art.
Fig. 2 shows a schematic diagram of a display panel according to one or more embodiments of the present disclosure.
FIG. 3 shows a schematic diagram of a gray scale control circuit according to one or more embodiments of the present disclosure.
Fig. 4 shows a schematic diagram of a pixel driving circuit of a pixel cell according to one or more embodiments of the present disclosure.
Fig. 5 illustrates a timing diagram of a pixel driving circuit of a pixel unit according to one or more embodiments of the present disclosure.
Fig. 6 shows a specific structure diagram of a pixel driving circuit of a pixel unit according to one or more embodiments of the present disclosure.
Fig. 7 illustrates a schematic diagram of a driving method of a display panel according to one or more embodiments of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure. It should be noted that throughout the drawings, like elements are represented by like or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as limiting the disclosure in any way, but merely as exemplifications of embodiments of the disclosure. Conventional structures or configurations will be omitted when they may obscure the understanding of this disclosure. It should be noted that the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given their ordinary meanings as understood by those skilled in the art. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another.
Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate a number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In the present disclosure, unless expressly stated or limited otherwise, the terms "connected" and "coupled" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the disclosure can be understood by those of ordinary skill in the art as appropriate.
The display panel and the display device provided by the embodiments of the present disclosure are described below with reference to the drawings.
Fig. 2 is a schematic structural diagram of a display panel provided in one or more embodiments of the present disclosure. As shown in fig. 2, includes: the liquid crystal display device includes a plurality of pixel units 201, a scan driving circuit 202 which supplies a scan signal to scan lines G1 to Gm of the plurality of pixel units 201, a data driving circuit 203 which supplies a data signal to the plurality of pixel units, a timing control circuit 204, and a gray scale control circuit 205.
The pixel driving circuit of the pixel unit 201 includes a data storage circuit (not shown in fig. 2) configured to selectively store data signals output onto the data lines D1 to Dn according to a scan signal; the timing control circuit 204 is configured to control the scan driving circuit 202, the data driving circuit 203, and the grayscale control circuit 205; the gray scale control circuit 205 is connected to the pixel unit 201, and the gray scale control circuit 205 is configured to output a common voltage, a gray scale driving voltage, and a high frequency pulse gray scale voltage to the pixel unit 201 under the control of the timing control circuit 204; the pixel unit 201 represents gray scale levels corresponding to the gray scale driving voltage, the high frequency pulse gray scale voltage and the common voltage according to the data signal stored in the data storage circuit.
As for the gray-scale control circuit 205, as described in fig. 3, it includes a main control circuit 2051, and a frequency divider 2052, a ring counter 2053, and a data selector 2054, which are connected in sequence; wherein,
the main control circuit 2051 is connected to the data selector 2054, and the main control circuit 2051 is controlled by the timing control circuit 204 and outputs gray scale driving voltages to the pixel unit 201 and the data selector 2054.
The frequency divider 2052 is connected to the timing control circuit 204, and the frequency divider 2052 receives the output of the timing control circuit 204 with a period T CLK Is divided into a period of T CLK the/N clock signal, and then output as the clock signal input to the ring counter 2053.
The ring counter 2053 receives the above cycle as T CLK And after the clock signal of/N, outputting an output signal of the ring counter.
The data selector 2054 is configured to receive the gray-scale driving voltage and the output signal of the ring counter 2053 and output a high-frequency pulse gray-scale voltage to the plurality of pixel units 201. Where N is an integer greater than 1.
In one or more embodiments of the present disclosure, the gray-scale control circuit 205 may further include a data buffer 2055, wherein the data buffer 2055 is configured to temporarily store and output the high-frequency pulse voltage to the plurality of pixel units 201.
For pixel cell 201, fig. 4 shows a pixel drive circuit for a pixel cell in accordance with one or more embodiments of the present disclosure. As shown in FIG. 4, the pixel driving circuit for any pixel unit (1 ≦ i ≦ m,1 ≦ j ≦ n, which is not limited herein) of one or more embodiments of the present disclosure includes a data writing circuit 2011 and a display driving circuit in addition to the data storage circuit 2012 mentioned aboveThe circuit 2013, the data write-in circuit 2011, the data storage circuit 2012 and the display drive circuit 2013 are connected in sequence, and the common voltage V is input to the common electrode of the liquid crystal cell LC of the pixel unit 201 COM (ii) a A data write circuit 2011 is connected to the data lines, and the data write circuit 2011 is configured to selectively write the data signals output to the data lines into the data storage circuit 2012 according to the scan signals; the display driving circuit 2013 is connected to a pixel electrode of the LC of the pixel unit 201, the display driving circuit 2013 is configured to input the gray-scale driving voltage and the high-frequency pulse gray-scale voltage, and control the pixel unit 201 to respectively represent the gray-scale driving voltage, the high-frequency pulse gray-scale voltage and the common voltage V according to the data signal stored in the data storage circuit 2012 COM Corresponding gray scale levels.
In one or more embodiments of the present disclosure, the common voltage V COM Is a period T COM The alternating voltage of (c); the gray scale driving voltage has a period T in phase with the AC voltage COM Has a period T opposite to that of the AC common voltage COM Of the first voltage. The pixel unit 201 controls the common voltage V applied to the pixel electrodes of the liquid crystal cells LC of the pixel unit 201 according to the data signal stored in the data memory 2012 COM First voltage V of same phase FRP And an inverted second voltage V XFRP To enable the state of the pixel cell to be switched between a display state and a non-display state.
In one or more embodiments of the present disclosure, the ring count 2053 is further configured to have the period T CLK Counting every M pulses of a/N clock signal and outputting a duty ratio of 1/M and a period of T CLK V (M · N) ring counter output signal; the selection control terminal of the data selector 2054 receives the signal with the period T CLK V (M.N) ring counter output signal, the data input control terminal of the data selector 2054 receives the first voltage V FRP And a second voltage V XFRP The output duty ratio of the output end of the data selector 2054 is 1/M and the period is T CLK V (M.N) of the high frequency pulse gray scale voltage, the dutyRatio of 1/M and period of T CLK The high frequency pulse gray scale voltage of/includes a first high frequency pulse gray scale voltage V with opposite phase L0 And a second high-frequency pulse gray-scale voltage V L1 . Wherein M is an integer greater than 1. As shown in fig. 4, the first voltage V FRP A second voltage V XFRP A first high frequency pulse gray scale voltage V L0 And a second high-frequency pulse gray-scale voltage V L1 The signals are respectively input to the display driving circuits of the plurality of pixel units through a first voltage signal line FRP, a second voltage signal line XFRP, a first high-frequency pulse gray scale voltage signal line L0 and a second high-frequency pulse gray scale voltage signal line L1. Wherein M is an integer greater than 1. The high-order pulse gray scale driving voltages with different duty ratios can form different gray scales. For the display panel disclosed above, the first voltage V may be represented FRP A second voltage V XFRP A first high frequency pulse gray scale voltage V L0 And a second high-frequency pulse gray-scale voltage V L1 And said common voltage V COM The corresponding four gray levels increase the gray scale of the display panel.
Fig. 5 illustrates a timing diagram of a pixel driving circuit of a pixel unit according to one or more embodiments of the present disclosure. Specifically, as shown in fig. 5, the common voltage is a period T COM Ac voltage V of COM The gray scale driving voltage has a period T in phase with the AC voltage COM First voltage V of FRP And the period of the phase inversion with the common voltage is T COM Second voltage V XFRP . For the high-frequency pulse gray-scale voltage, a first high-frequency pulse gray-scale voltage V L0 Is at T COM In period of (2), with V COM In phase, pulse duty ratio of 1/M, T CLK V (M.N) high frequency pulse, under this condition, at a time T COM During the time, the voltage between the common electrode of the liquid crystal cell LC of the pixel unit and the two ends of the pixel electrode is T CLK V (M.N) is the period fast flip, when T CLK When the value is small,/(M · N), the L0 gray scale is displayed according to the persistence of vision effect of human eyes. And a second high-frequency pulse gray-scale voltage V L1 Is at T COM In period of (2), with V COM Inverse phaseThe pulse duty ratio is 1/M, T CLK /(M.N) high frequency pulse at a T COM During the time, the voltage between the common electrode of the liquid crystal cell LC of the pixel unit and the two ends of the pixel electrode is T CLK /(M.N) is the period flipping rapidly when T CLK when/(M · N) is small, it appears to display the L1 gray scale, also according to the effect of persistence of vision of human eyes. In order to avoid screen flicker and improve viewing experience, the period T of the high-frequency pulse is adjusted according to the PWM dimming principle CLK If the selection criterion of the/(/) is less than 10ms, namely the flicker frequency is higher than 100Hz, human eyes cannot feel flicker due to the vision retention phenomenon. With the development of liquid crystal technology, liquid crystal with response time less than 1ms, T, generally exists CLK And/or (M.N) can be as low as 1ms, namely, the flicker frequency is higher than 1kHz, the flicker is avoided while the gray scale is expressed, and the viewing experience is improved.
In one or more embodiments of the disclosure, every T COM Time, common voltage V COM And the gray scale driving voltage (V) FRP 、V XFRP 、V L0 、V L1 ) The positive and negative are turned over, so that the voltage at two ends of the LC unit jumps, and the polarization of the liquid crystal is avoided.
In one or more embodiments of the present disclosure, as shown in fig. 4, the data lines include a first data line Dja and a second data line Djb configured to transmit a first data signal and a second data signal included in the data signal, respectively. With respect to a specific structure of the pixel driving circuit of the pixel circuit, the following will be described in detail with reference to fig. 6.
As shown in fig. 6, for the case where the data line includes a first data line Dja and a second data line Djb, correspondingly, the data storage circuit 2012 in fig. 4 includes a first storage circuit 501 and a second storage circuit 502 configured to store the first data signal and the second data signal, respectively. The display driving circuit 2013 in fig. 4 includes a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a first and gate Y1, a second and gate Y2, a third and gate Y3, and a fourth and gate Y4, wherein control electrodes of the switching elements of the display driving circuit are sequentially connected to output ends of the and gates of the display driving circuit, first electrodes of the switching elements of the display driving circuit are respectively connected to a second high-frequency pulse gray-scale voltage signal line L1, a first high-frequency pulse gray-scale voltage signal line L0, a second voltage signal line XFRP, and a first voltage signal line FRP, and second electrodes of the switching elements of the display driving circuit are connected to pixel electrodes of the liquid crystal cells LC of the pixel units. The connection sequence of the first poles of the respective light-emitting elements in fig. 6 and the signal lines is merely an example, and the connection sequence is not limited in practice.
As for the data write circuit 2011 in fig. 4, as shown in fig. 6, the data write circuit includes a fifth switching element T5 and a sixth switching element T6, a control pole of each switching element of the data write circuit is connected to the scan line Gi, a first pole of the fifth switching element T5 is connected to the first data line Dja, a second pole of the fifth switching element T5 is connected to the input terminal of the first storage circuit 501, a first pole of the sixth switching element T6 is connected to the second data line Djb, and a second pole of the sixth switching element T6 is connected to the input terminal of the second storage circuit 502. The input end of the first storage circuit 501 is connected with the first input end of the first and gate Y1 and the first input end of the second and gate Y2, and the output end of the first storage circuit 501 is connected with the first input end of the third and gate Y3 and the first input end of the fourth and gate Y4; the input end of the second storage circuit 502 is connected to the second input end of the first and gate Y1 and the second input end of the third and gate Y3, and the output end of the second storage circuit 502 is connected to the second input end of the second and gate Y2 and the second input end of the fourth and gate Y4.
For the first storage circuit 501 and the second storage circuit 502, as shown In fig. 6, the first storage circuit 501 includes a first inverter In1 and a second inverter In2, an input end of the first inverter In1 and an output end of the second inverter In2 are connected to the second pole of the fifth switching element T5, a first input end of the first and gate Y1 and a first input end of the second and gate Y2, and an output end of the first inverter In1 and an input end of the second inverter In2 are connected to a first input end of the third and gate Y3 and a first input end of the fourth and gate Y4. The second storage circuit 502 includes a third inverter In3 and a fourth inverter In4, an input end of the third inverter In3 and an output end of the fourth inverter In4 are connected to the second pole of the sixth switching element T6, the second input end of the first and gate Y1 and the second input end of the third and gate Y3, and an output end of the third inverter In3 and an input end of the fourth inverter In4 are connected to the second input end of the second and gate Y2 and the second input end of the fourth and gate Y4.
In one or more embodiments of the present disclosure, the first inverter In1 and the second inverter In2 include TFT inverters, each of the switching elements is a thin film transistor, and each of the and gates includes a thin film transistor and gate; or, the first inverter and the second inverter comprise CMOS inverters, each switch element is a CMOS transistor, and each and gate comprises a CMOS and gate.
All of which may be thin film transistors or field effect transistors or other devices of the same characteristics are employed in one or more embodiments of the present disclosure. Preferably, the thin film transistor used in one or more embodiments of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the thin film transistor used herein are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, one of the source and the drain is referred to as a first pole, and the other of the source and the drain is referred to as a second pole. The description is made taking an N-type thin film transistor as an example in one or more examples of the present disclosure. It will be understood by those skilled in the art that the embodiments of the present disclosure can be also applied to the case of P-type thin film transistors.
The above is given only an example of the display panel of the present disclosure, and the embodiments of the present disclosure are not limited thereto, and the configuration and the number of the data storage circuit, the data line, the signal line to which the gray scale voltage is input, and the configuration of the gray scale control circuit and the number of the high frequency pulse gray scale voltages output may be set as needed for the pixel unit of the display panel. Here, the number of data storage circuits, data lines, and signal lines to which gray scale voltages are input is proportional to each other. Compared with the pixel circuit of the related art shown in fig. 1, the present disclosure can provide a larger number of gray scale voltage signals to the pixel unit to obtain a desired gray scale of the display panel, and can meet a wider range of user requirements.
According to an aspect of the embodiments of the present disclosure, there is provided a driving method of the above display panel, which is applicable to the display panel of any of the above embodiments, and will be described below with reference to the display panel of fig. 2. As shown in fig. 7, the driving method includes:
step S601: the scan driving circuit 202 supplies scan signals to the scan lines G1 to Gm of the plurality of pixel units 201.
Step S602: data signals are supplied to the data lines D1 to Dn of the plurality of pixel units 201 through the data driving circuit 203.
Step S603: the data signals output to the data lines D1 to Dn are selectively stored in the data storage circuits of the respective pixel units 201 according to the scan signal.
Step S604: the gray scale control circuit 205 outputs a common voltage, a gray scale driving voltage and a high frequency pulse gray scale voltage to the plurality of pixel units 201, and the plurality of pixel units 201 here respectively represent gray scale levels corresponding to the gray scale driving voltage, the high frequency pulse gray scale voltage and the common voltage according to the data signals stored by the data storage circuit.
According to one or more embodiments of the present disclosure, as shown in fig. 3, the gray-scale control circuit 205 may further include a main control circuit 2051, and a frequency divider 2052, a ring counter 2053, and a data selector 2054 that are connected in sequence; the main control circuit 2051 is connected to the data selector 2054, and the frequency divider 2052 is connected to the timing control circuit 204 in fig. 2. In this case, step S604 of the above driving method further includes: generating a duty cycle of 1/M and a period of T by a ring counter 2053 CLK The ring counter of/(M · N) outputs a signal and is input to the data selector 2054; the duty ratio is 1/M and the period is T are output through a data selector 2054 CLK The high-frequency pulse gray scale voltage of/M.N comprises a first high-frequency pulse gray scale voltage and a second high-frequency pulse gray scale voltage which are opposite in phase; controlling a plurality of pixel units 201 to respectively express the first voltage, the second voltage and the first high-frequency pulse gray scale voltage according to the data signal stored in the data storage circuitAnd the second high-frequency pulse gray scale voltage and the gray scale level corresponding to the public voltage. Wherein M is an integer greater than 1.
According to an aspect of embodiments of the present disclosure, there is provided a display device including the display panel shown in any one of the above-described embodiments. For example, the display device may be any one of a reflective type, a transflective type, a transparent liquid crystal display device, and the like, and any product or component having a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, and the like, which includes the display device, so that the scope of the present disclosure should not be limited to a specific type of display device.
According to the embodiment of the disclosure, the pixel driving circuit which adjusts the liquid crystal voltage by adopting the high-frequency pulse voltage is combined with the corresponding time sequence, and different gray scale display is realized by using the visual persistence of human eyes, so that the multi-gray scale display of the display panel with the storage circuit can be realized fundamentally, and the wider user requirements are met; on the other hand, the pixel circuit complexity of the embodiment of the present disclosure is lower than that of the multi-gray-scale scheme of the MIP in the prior art, and there is a certain substitutable advantage in terms of reducing the design cost and reducing the power consumption.
Further, the driving method according to the present disclosure may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer non-transitory readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method of the present disclosure.
Further, it should be appreciated that the computer-readable storage media (e.g., memories) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.
Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.
Claims (11)
1. The display panel is characterized by comprising a plurality of pixel units, a scanning driving circuit for providing scanning signals for scanning lines of the pixel units, a data driving circuit for providing data signals for data lines of the pixel units, a time sequence control circuit and a gray scale control circuit; wherein,
the pixel driving circuit of the pixel unit includes a data storage circuit selectively storing the data signal output onto the data line according to the scan signal; the timing control circuit is configured to control the scan driving circuit, the data driving circuit, and the grayscale control circuit;
the gray scale control circuit comprises a main control circuit, and a frequency divider, an annular counter and a data selector which are sequentially connected; the main control circuit is connected with the data selector and is configured to accept the control of the time sequence control circuit and output gray scale driving voltage to the plurality of pixel units and the data selector; the frequency divider is connected with the time sequence control circuit, is configured to receive the clock signal with the period of TCLK output by the time sequence control circuit, divides the clock signal into clock signals with the period of TCLK/N and outputs the clock signals as the input of the ring counter; the ring counter is configured to receive the clock signal having a period of TCLK/N and output a ring counter output signal; the data selector is configured to receive the gray scale driving voltage and the ring counter output signal and output a high frequency pulse gray scale voltage to the plurality of pixel units; wherein N is an integer greater than 1; the gray scale control circuit is connected with the plurality of pixel units and is configured to output a common voltage, a gray scale driving voltage and a high-frequency pulse gray scale voltage to the plurality of pixel units under the control of the time sequence control circuit;
the pixel units respectively express the gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the public voltage according to the data signals stored by the data storage circuit.
2. The display panel according to claim 1,
the pixel driving circuit of the pixel unit further comprises a data writing circuit and a display driving circuit, the data writing circuit, the data storage circuit and the display driving circuit are sequentially connected, and a common electrode of the pixel unit is configured to input the common voltage;
the data writing circuit is connected with the data line and is configured to selectively write the data signal output to the data line into the data storage circuit according to the scanning signal;
the display driving circuit is connected with the pixel electrode of the pixel unit, is configured to input the gray scale driving voltage and the high-frequency pulse gray scale voltage, and controls the pixel unit to respectively express gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the common voltage according to the data signal stored by the data storage circuit.
3. The display panel according to any one of claims 1-2,
the common voltage is in a period T COM The alternating voltage of (c);
the gray scale driving voltage has a period T in phase with the AC voltage COM Has a period of T opposite to that of the alternating voltage COM Of the first voltage.
4. The display panel according to claim 3,
the ring counter is further configured to have the period T CLK Counting every M pulses of a clock signal of/N and outputting a duty ratio of 1/M and a period of T CLK V (M · N) ring counter output signal;
the selection control end of the data selector receives the period T CLK A ring counter of N, a data input control end of the data selector receives the first voltage and the second voltage, and an output end of the data selector outputs a duty ratio of 1/M and a period of T CLK V (M.N) of the high-frequency pulse gray-scale voltage, the duty ratio is 1/M, and the period is T CLK The high-frequency pulse gray scale voltage of the/N comprises a first high-frequency pulse gray scale voltage and a second high-frequency pulse gray scale voltage which are opposite in phase;
the first voltage, the second voltage, the first high-frequency pulse gray scale voltage and the second high-frequency pulse gray scale voltage are respectively input to the pixel driving circuits of the pixel units through a first voltage signal line, a second voltage signal line, a first high-frequency pulse gray scale voltage signal line and a second high-frequency pulse gray scale voltage signal line;
wherein M is an integer greater than 1.
5. The display panel according to claim 1,
and a data buffer is connected between the data selector and the plurality of pixel units, and is configured to temporarily store and output the high-frequency pulse gray scale voltage to the plurality of pixel units.
6. The display panel according to claim 2,
the data lines include first and second data lines configured to transmit first and second data signals included in the data signals, respectively;
the data storage circuit includes a first storage circuit and a second storage circuit configured to store the first data signal and the second data signal, respectively;
the display driving circuit comprises a first switching element, a second switching element, a third switching element, a fourth switching element, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, wherein control electrodes of the switching elements of the display driving circuit are sequentially and correspondingly connected with output ends of the AND gates of the display driving circuit, first electrodes of the switching elements of the display driving circuit are respectively connected to a first voltage signal line, a second voltage signal line, a first high-frequency pulse gray-scale voltage signal line and a second high-frequency pulse gray-scale voltage signal line, and second electrodes of the switching elements of the display driving circuit are connected with pixel electrodes of the pixel units;
the data writing circuit includes a fifth switching element and a sixth switching element, a control pole of each switching element of the data writing circuit is connected to the scan line, a first pole of the fifth switching element is connected to the first data line, a second pole of the fifth switching element is connected to the input terminal of the first storage circuit, a first pole of the sixth switching element is connected to the second data line, and a second pole of the sixth switching element is connected to the input terminal of the second storage circuit;
the input end of the first storage circuit is connected with the first input end of the first AND gate and the first input end of the second AND gate, and the output end of the first storage circuit is connected with the first input end of the third AND gate and the first input end of the fourth AND gate;
the input end of the second storage circuit is connected with the second input end of the first AND gate and the second input end of the third AND gate, and the output end of the second storage circuit is connected with the second input end of the second AND gate and the second input end of the fourth AND gate.
7. The display panel according to claim 6,
the first storage circuit includes a first inverter and a second inverter; the input end of the first inverter and the output end of the second inverter are connected with the second pole of the fifth switching element, the first input end of the first AND gate and the first input end of the second AND gate, and the output end of the first inverter and the input end of the second inverter are connected with the first input end of the third AND gate and the first input end of the fourth AND gate;
the second storage circuit comprises a third inverter and a fourth inverter; the input end of the third phase inverter and the output end of the fourth phase inverter are connected with the second pole of the sixth switching element, the second input end of the first AND gate and the second input end of the third AND gate, and the output end of the third phase inverter and the input end of the fourth phase inverter are connected with the second input end of the second AND gate and the second input end of the fourth AND gate.
8. The display panel according to claim 7, wherein the first inverter and the second inverter comprise TFT inverters, each of the switching elements is a thin film transistor, and each of the and gates comprises a thin film transistor and gate; or,
the first inverter and the second inverter comprise CMOS inverters, each switch element is a CMOS transistor, and each AND gate comprises a CMOS AND gate.
9. A driving method of a display panel applied to the display panel according to any one of claims 1 to 8,
providing scanning signals to scanning lines of the pixel units through the scanning driving circuit;
providing data signals to data lines of the plurality of pixel units through the data driving circuit;
selectively storing the data signal output onto the data line in a data storage circuit of each of the plurality of pixel units according to the scan signal;
and the gray scale control circuit outputs a public voltage, a gray scale driving voltage and a high-frequency pulse gray scale voltage to the pixel units, and the pixel units respectively express gray scale levels corresponding to the gray scale driving voltage, the high-frequency pulse gray scale voltage and the public voltage according to data signals stored by the data storage circuit.
10. The method for driving the display panel according to claim 9,
the gray scale control circuit comprises a main control circuit, and a frequency divider, an annular counter and a data selector which are sequentially connected; the main control circuit is connected with the data selector, and the frequency divider is connected with the sequential control circuit; the driving method includes:
generating a duty ratio of 1/M and a period of T by the ring counter CLK A ring counter of/(M.N) outputs a signal and inputs to the data selector;
outputting the duty ratio of 1/M and the period of T by the data selector CLK The high-frequency pulse gray scale voltage of the/N comprises a first high-frequency pulse gray scale voltage and a second high-frequency pulse gray scale voltage which are opposite in phase;
and controlling the pixel units to respectively express the gray scale levels corresponding to the first voltage, the second voltage, the first high-frequency pulse gray scale voltage, the second high-frequency pulse gray scale voltage and the public voltage according to the data signals stored by the data storage circuit.
11. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.
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