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DE69232311D1 - Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung - Google Patents

Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung

Info

Publication number
DE69232311D1
DE69232311D1 DE69232311T DE69232311T DE69232311D1 DE 69232311 D1 DE69232311 D1 DE 69232311D1 DE 69232311 T DE69232311 T DE 69232311T DE 69232311 T DE69232311 T DE 69232311T DE 69232311 D1 DE69232311 D1 DE 69232311D1
Authority
DE
Germany
Prior art keywords
manufactured
integrated
manufacturing
devices
integrated device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69232311T
Other languages
English (en)
Inventor
Giuseppe Crisenza
Cesare Clementi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69232311D1 publication Critical patent/DE69232311D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69232311T 1992-09-30 1992-09-30 Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung Expired - Lifetime DE69232311D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830542A EP0591599B1 (de) 1992-09-30 1992-09-30 Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung

Publications (1)

Publication Number Publication Date
DE69232311D1 true DE69232311D1 (de) 2002-01-31

Family

ID=8212182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232311T Expired - Lifetime DE69232311D1 (de) 1992-09-30 1992-09-30 Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung

Country Status (4)

Country Link
US (2) US5464784A (de)
EP (1) EP0591599B1 (de)
JP (1) JPH06224377A (de)
DE (1) DE69232311D1 (de)

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JP3123921B2 (ja) * 1995-05-18 2001-01-15 三洋電機株式会社 半導体装置および不揮発性半導体メモリ
KR0183730B1 (ko) * 1995-08-24 1999-04-15 김광호 소자 분리 특성을 향상시킨 반도체 기억 장치 및 그 제조방법
US5789295A (en) * 1995-11-17 1998-08-04 Advanced Micro Devices, Inc. Method of eliminating or reducing poly1 oxidation at stacked gate edge in flash EPROM process
DE69630944D1 (de) * 1996-03-29 2004-01-15 St Microelectronics Srl Hochspannungsfester MOS-Transistor und Verfahren zur Herstellung
US5879954A (en) * 1996-05-20 1999-03-09 Raytheon Company Radiation-hard isoplanar cryo-CMOS process suitable for sub-micron devices
JP3123924B2 (ja) * 1996-06-06 2001-01-15 三洋電機株式会社 不揮発性半導体メモリ
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
TW360955B (en) * 1997-09-10 1999-06-11 United Microelectronics Corp Method for producing ETOX cell by self-aligned source etching
US6388288B1 (en) * 1998-03-30 2002-05-14 Texas Instruments Incorporated Integrating dual supply voltages using a single extra mask level
FR2778018B1 (fr) * 1998-04-28 2000-06-23 Sgs Thomson Microelectronics Procede de fabrication de dispositifs eeprom
US6524895B2 (en) 1998-12-25 2003-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6624473B1 (en) 1999-03-10 2003-09-23 Matsushita Electric Industrial Co., Ltd. Thin-film transistor, panel, and methods for producing them
US6384451B1 (en) 1999-03-24 2002-05-07 John Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6534816B1 (en) 1999-03-24 2003-03-18 John M. Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US20040021170A1 (en) * 1999-03-24 2004-02-05 Caywood John M. Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
KR100590380B1 (ko) * 1999-12-28 2006-06-15 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
WO2002072787A2 (en) * 2001-03-13 2002-09-19 Sierra Sciences, Inc. Telomerase expression repressor proteins and methods of using the same
US6436760B1 (en) * 2001-04-19 2002-08-20 International Business Machines Corporation Method for reducing surface oxide in polysilicon processing
US6710424B2 (en) 2001-09-21 2004-03-23 Airip RF chipset architecture
US7393710B2 (en) * 2004-10-26 2008-07-01 Samsung Electro-Mechanics Co., Ltd Fabrication method of multi-wavelength semiconductor laser device
US7820512B2 (en) * 2007-12-28 2010-10-26 Intel Corporation Spacer patterned augmentation of tri-gate transistor gate length

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JPS5412565A (en) * 1977-06-29 1979-01-30 Toshiba Corp Production of semiconductor device
DE3037744A1 (de) * 1980-10-06 1982-05-19 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten zwei-transistor-speicherzelle in mos-technik
IT1196997B (it) * 1986-07-25 1988-11-25 Sgs Microelettronica Spa Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati
JPH0834310B2 (ja) * 1987-03-26 1996-03-29 沖電気工業株式会社 半導体装置の製造方法
KR970003903B1 (en) * 1987-04-24 1997-03-22 Hitachi Mfg Kk Semiconductor device and fabricating method thereof
FR2625608B1 (fr) * 1988-01-04 1990-06-15 Sgs Thomson Microelectronics Procede de fabrication d'un circuit integre comprenant des elements a deux niveaux de grille
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
JPH03218637A (ja) * 1989-11-01 1991-09-26 Matsushita Electric Ind Co Ltd 電界効果型半導体装置とその製造方法
US5202277A (en) * 1989-12-08 1993-04-13 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device
JPH03245575A (ja) * 1990-02-22 1991-11-01 Mitsubishi Electric Corp 半導体記憶装置及びその製造方法
JP2548994B2 (ja) * 1990-03-19 1996-10-30 富士通株式会社 電界効果型トランジスタ及びその製造方法
GB9127093D0 (en) * 1991-02-26 1992-02-19 Samsung Electronics Co Ltd Field-effect transistor
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor
JPH0521811A (ja) * 1991-07-12 1993-01-29 Sony Corp 半導体装置及びその製造方法
US5273923A (en) * 1991-10-09 1993-12-28 Motorola, Inc. Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions
KR940009644B1 (ko) * 1991-11-19 1994-10-15 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법

Also Published As

Publication number Publication date
US5977586A (en) 1999-11-02
EP0591599B1 (de) 2001-12-19
EP0591599A1 (de) 1994-04-13
JPH06224377A (ja) 1994-08-12
US5464784A (en) 1995-11-07

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Legal Events

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