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DE69222586D1 - Mehrlagige Verbindungsstruktur für eine Halbleiter- vorrichtung und Verfahren zu ihrer Herstellung - Google Patents

Mehrlagige Verbindungsstruktur für eine Halbleiter- vorrichtung und Verfahren zu ihrer Herstellung

Info

Publication number
DE69222586D1
DE69222586D1 DE69222586T DE69222586T DE69222586D1 DE 69222586 D1 DE69222586 D1 DE 69222586D1 DE 69222586 T DE69222586 T DE 69222586T DE 69222586 T DE69222586 T DE 69222586T DE 69222586 D1 DE69222586 D1 DE 69222586D1
Authority
DE
Germany
Prior art keywords
production
semiconductor device
connection structure
layer connection
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69222586T
Other languages
English (en)
Other versions
DE69222586T2 (de
Inventor
Yasuyuki Morishita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69222586D1 publication Critical patent/DE69222586D1/de
Application granted granted Critical
Publication of DE69222586T2 publication Critical patent/DE69222586T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69222586T 1991-07-23 1992-07-23 Mehrlagige Verbindungsstruktur für eine Halbleiter- vorrichtung und Verfahren zu ihrer Herstellung Expired - Fee Related DE69222586T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20656491A JP3166221B2 (ja) 1991-07-23 1991-07-23 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69222586D1 true DE69222586D1 (de) 1997-11-13
DE69222586T2 DE69222586T2 (de) 1998-05-07

Family

ID=16525485

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69222586T Expired - Fee Related DE69222586T2 (de) 1991-07-23 1992-07-23 Mehrlagige Verbindungsstruktur für eine Halbleiter- vorrichtung und Verfahren zu ihrer Herstellung

Country Status (4)

Country Link
US (1) US5529956A (de)
EP (1) EP0524818B1 (de)
JP (1) JP3166221B2 (de)
DE (1) DE69222586T2 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221174A (ja) * 1993-12-10 1995-08-18 Canon Inc 半導体装置及びその製造方法
JP2737762B2 (ja) * 1993-12-28 1998-04-08 日本電気株式会社 半導体装置の製造方法
US5594278A (en) * 1994-04-22 1997-01-14 Nippon Steel Corporation Semiconductor device having a via hole with an aspect ratio of not less than four, and interconnections therein
DE4435585C2 (de) * 1994-10-05 2001-02-01 Micronas Gmbh Anschlußstruktur für Doppelschichten, insbesondere zur Verwendung in integrierten Halbleiterschaltkreisen
KR0161731B1 (ko) * 1994-10-28 1999-02-01 김주용 반도체소자의 미세콘택 형성방법
JPH08321545A (ja) * 1995-05-24 1996-12-03 Yamaha Corp 配線形成法
JP3538970B2 (ja) * 1995-05-24 2004-06-14 ヤマハ株式会社 配線形成法
US6420725B1 (en) * 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
TW318261B (de) * 1995-09-21 1997-10-21 Handotai Energy Kenkyusho Kk
US5960318A (en) * 1995-10-27 1999-09-28 Siemens Aktiengesellschaft Borderless contact etch process with sidewall spacer and selective isotropic etch process
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US6653733B1 (en) 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5756396A (en) * 1996-05-06 1998-05-26 Taiwan Semiconductor Manufacturing Company Ltd Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US6337266B1 (en) 1996-07-22 2002-01-08 Micron Technology, Inc. Small electrode for chalcogenide memories
JPH1098100A (ja) * 1996-09-20 1998-04-14 Nec Corp コンタクトホール／スルーホール形成方法
US5891805A (en) * 1996-12-13 1999-04-06 Intel Corporation Method of forming contacts
US6015977A (en) 1997-01-28 2000-01-18 Micron Technology, Inc. Integrated circuit memory cell having a small active area and method of forming same
US6969866B1 (en) * 1997-10-01 2005-11-29 Ovonyx, Inc. Electrically programmable memory element with improved contacts
US6211073B1 (en) 1998-02-27 2001-04-03 Micron Technology, Inc. Methods for making copper and other metal interconnections in integrated circuits
US6284656B1 (en) 1998-08-04 2001-09-04 Micron Technology, Inc. Copper metallurgy in integrated circuits
US6288442B1 (en) 1998-09-10 2001-09-11 Micron Technology, Inc. Integrated circuit with oxidation-resistant polymeric layer
JP2000150647A (ja) * 1998-11-11 2000-05-30 Sony Corp 配線構造およびその製造方法
US20020127845A1 (en) * 1999-03-01 2002-09-12 Paul A. Farrar Conductive structures in integrated circuits
US6265301B1 (en) 1999-05-12 2001-07-24 Taiwan Semiconductor Manufacturing Company Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures
EP1087432A1 (de) 1999-09-24 2001-03-28 Interuniversitair Micro-Elektronica Centrum Vzw Verbesserung der Qualität einer in einem Metallisierungsbad abgeschiedenen Schicht
EP1063696B1 (de) * 1999-06-22 2007-08-22 Interuniversitair Micro-Elektronica Centrum Vzw Verbesserung der Qualität einer in einem Plattierungsbad abgeschiedenen metallhaltigen Schicht
US7262130B1 (en) 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US7211512B1 (en) 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6440837B1 (en) 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US6563156B2 (en) 2001-03-15 2003-05-13 Micron Technology, Inc. Memory elements and methods for making same
US6617689B1 (en) 2000-08-31 2003-09-09 Micron Technology, Inc. Metal line and method of suppressing void formation therein
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
JP2007149866A (ja) * 2005-11-25 2007-06-14 Elpida Memory Inc 半導体シリコン基板の製造方法およびその製造装置
DE102007004884A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht
WO2009069020A1 (en) * 2007-11-27 2009-06-04 Nxp B.V. Contact structure for an electronic circuit substrate and electronic circuit comprising said contact structure
JP5498751B2 (ja) * 2009-10-05 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2013095433A1 (en) * 2011-12-21 2013-06-27 Intel Corporation Electroless filled conductive structures
TWI527189B (zh) * 2013-12-24 2016-03-21 矽品精密工業股份有限公司 半導體基板及其製法
JP6963396B2 (ja) 2017-02-28 2021-11-10 キヤノン株式会社 電子部品の製造方法
US20230343697A1 (en) * 2022-04-20 2023-10-26 Samsung Electronics Co., Ltd. Semiconductor device including spacer via structure and method of manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3507756A (en) * 1967-08-04 1970-04-21 Bell Telephone Labor Inc Method of fabricating semiconductor device contact
JPS63299251A (ja) * 1987-05-29 1988-12-06 Toshiba Corp 半導体装置の製造方法
US4977105A (en) * 1988-03-15 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing interconnection structure in semiconductor device
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
US4898841A (en) * 1988-06-16 1990-02-06 Northern Telecom Limited Method of filling contact holes for semiconductor devices and contact structures made by that method
JP2623812B2 (ja) * 1989-01-25 1997-06-25 日本電気株式会社 半導体装置の製造方法
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
JP3118785B2 (ja) * 1991-05-23 2000-12-18 ソニー株式会社 バリヤメタル構造の形成方法
US5209817A (en) * 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
JPH05206064A (ja) * 1991-12-10 1993-08-13 Nec Corp 半導体装置の製造方法
JPH05283362A (ja) * 1992-04-03 1993-10-29 Sony Corp 多層配線の形成方法
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers

Also Published As

Publication number Publication date
EP0524818A1 (de) 1993-01-27
JP3166221B2 (ja) 2001-05-14
EP0524818B1 (de) 1997-10-08
DE69222586T2 (de) 1998-05-07
JPH0529315A (ja) 1993-02-05
US5529956A (en) 1996-06-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee