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DE69124773D1 - Verfahren zur Herstellung eines Substrates mit dielektrischer Trennung - Google Patents

Verfahren zur Herstellung eines Substrates mit dielektrischer Trennung

Info

Publication number
DE69124773D1
DE69124773D1 DE69124773T DE69124773T DE69124773D1 DE 69124773 D1 DE69124773 D1 DE 69124773D1 DE 69124773 T DE69124773 T DE 69124773T DE 69124773 T DE69124773 T DE 69124773T DE 69124773 D1 DE69124773 D1 DE 69124773D1
Authority
DE
Germany
Prior art keywords
substrate
production
dielectric separation
dielectric
separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124773T
Other languages
English (en)
Other versions
DE69124773T2 (de
Inventor
Konomu Ohki
Yutaka Ohta
Masatake Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69124773D1 publication Critical patent/DE69124773D1/de
Application granted granted Critical
Publication of DE69124773T2 publication Critical patent/DE69124773T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
DE69124773T 1990-11-15 1991-11-05 Verfahren zur Herstellung eines Substrates mit dielektrischer Trennung Expired - Fee Related DE69124773T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2310201A JPH0770589B2 (ja) 1990-11-15 1990-11-15 誘電体分離基板の製造方法

Publications (2)

Publication Number Publication Date
DE69124773D1 true DE69124773D1 (de) 1997-04-03
DE69124773T2 DE69124773T2 (de) 1997-09-18

Family

ID=18002399

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124773T Expired - Fee Related DE69124773T2 (de) 1990-11-15 1991-11-05 Verfahren zur Herstellung eines Substrates mit dielektrischer Trennung

Country Status (4)

Country Link
US (1) US5124274A (de)
EP (1) EP0486201B1 (de)
JP (1) JPH0770589B2 (de)
DE (1) DE69124773T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2848162B2 (ja) * 1992-11-12 1999-01-20 日本電気株式会社 半導体装置用誘電体分離基板
US5540810A (en) * 1992-12-11 1996-07-30 Micron Technology Inc. IC mechanical planarization process incorporating two slurry compositions for faster material removal times
US5262346A (en) * 1992-12-16 1993-11-16 International Business Machines Corporation Nitride polish stop for forming SOI wafers
KR940016630A (ko) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 반도체 장치 및 제조방법
US5318663A (en) * 1992-12-23 1994-06-07 International Business Machines Corporation Method for thinning SOI films having improved thickness uniformity
JPH07326664A (ja) * 1994-05-31 1995-12-12 Fuji Electric Co Ltd ウエハの誘電体分離溝の充填方法
JPH07326663A (ja) * 1994-05-31 1995-12-12 Fuji Electric Co Ltd ウエハの誘電体分離方法
US5436190A (en) * 1994-11-23 1995-07-25 United Microelectronics Corporation Method for fabricating semiconductor device isolation using double oxide spacers
CA2589206A1 (en) * 2004-12-07 2006-06-15 Griffin Analytical Technologies Apparatus and method for mobile collection of atmospheric sample for chemical analysis
CN100468029C (zh) * 2005-03-03 2009-03-11 清华大学 标准漏孔及其制作方法
US20070207622A1 (en) * 2006-02-23 2007-09-06 Micron Technology, Inc. Highly selective doped oxide etchant
US8176801B2 (en) 2006-12-22 2012-05-15 Griffin Analytical Technology, L.L.C. Interface port for connection of a sampling device to an analytical instrument
US8146448B2 (en) 2007-06-29 2012-04-03 Griffin Analytical Technologies, Llc Apparatus for mobile collection of atmospheric sample for chemical analysis
US9287123B2 (en) 2014-04-28 2016-03-15 Varian Semiconductor Equipment Associates, Inc. Techniques for forming angled structures for reduced defects in heteroepitaxy of semiconductor films

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969168A (en) * 1974-02-28 1976-07-13 Motorola, Inc. Method for filling grooves and moats used on semiconductor devices
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
US4255207A (en) * 1979-04-09 1981-03-10 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4554728A (en) * 1984-06-27 1985-11-26 International Business Machines Corporation Simplified planarization process for polysilicon filled trenches
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
KR910009318B1 (ko) * 1987-09-08 1991-11-09 미쓰비시 뎅끼 가부시기가이샤 반도체 장치의 제조 및 고내압 파묻음 절연막 형성방법

Also Published As

Publication number Publication date
JPH0770589B2 (ja) 1995-07-31
US5124274A (en) 1992-06-23
EP0486201A2 (de) 1992-05-20
JPH04180648A (ja) 1992-06-26
EP0486201B1 (de) 1997-02-26
EP0486201A3 (en) 1993-02-10
DE69124773T2 (de) 1997-09-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee