DE69021616D1 - Verzögerungsschaltung. - Google Patents

Verzögerungsschaltung.

Info

Publication number: DE69021616D1
Authority: DE; Germany
Prior art keywords: delay circuit; delay; circuit
Prior art date: 1989-04-20
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE69021616T

Other languages

English (en)

Other versions

DE69021616T2 (de

Inventor

Masaya Tanno

Masato Onaya

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Sanyo Electric Co Ltd

Original Assignee

Sanyo Electric Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1989-04-20

Filing date

1990-04-20

Publication date

1995-09-21

1990-04-20 Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd

1995-09-21 Application granted granted Critical

1995-09-21 Publication of DE69021616D1 publication Critical patent/DE69021616D1/de

1996-04-18 Publication of DE69021616T2 publication Critical patent/DE69021616T2/de

2010-04-21 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00273—Layout of the delay element using circuits having two logic levels using digital comparators

Landscapes

Physics & Mathematics (AREA)
Nonlinear Science (AREA)
Analogue/Digital Conversion (AREA)
Noise Elimination (AREA)
Pulse Circuits (AREA)

DE69021616T 1989-04-20 1990-04-20 Verzögerungsschaltung. Expired - Fee Related DE69021616T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP1100775A JPH02279015A (ja)	1989-04-20	1989-04-20	遅延回路

Publications (2)

Publication Number	Publication Date
DE69021616D1 true DE69021616D1 (de)	1995-09-21
DE69021616T2 DE69021616T2 (de)	1996-04-18

Family

ID=14282855

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69021616T Expired - Fee Related DE69021616T2 (de)	1989-04-20	1990-04-20	Verzögerungsschaltung.

Country Status (6)

Country	Link
US (1)	US5073733A (de)
EP (1)	EP0393716B1 (de)
JP (1)	JPH02279015A (de)
KR (1)	KR970000561B1 (de)
CA (1)	CA2014969C (de)
DE (1)	DE69021616T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP2740063B2 (ja) *	1990-10-15	1998-04-15	株式会社東芝	半導体記憶装置
JP3053658B2 (ja) *	1991-03-04	2000-06-19	沖電気工業株式会社	電圧／パルス幅変調回路
JP2996328B2 (ja) *	1992-12-17	1999-12-27	三菱電機株式会社	半導体集積回路、およびそれを用いた半導体集積回路組合回路
JPH06188839A (ja) *	1992-12-21	1994-07-08	Nippon Precision Circuits Kk	サンプリングレートコンバータ
US5521499A (en) *	1992-12-23	1996-05-28	Comstream Corporation	Signal controlled phase shifter
JPH08203265A (ja) *	1995-01-26	1996-08-09	Nec Eng Ltd	遅延回路
JP2001069129A (ja) *	1999-08-31	2001-03-16	Mitsubishi Electric Corp	受信装置及び通信システム
US7942350B2 (en)	2008-09-16	2011-05-17	Shoap Stephen D	Method and system for fluid transmission along significant distances
US9615760B2 (en) *	2013-06-17	2017-04-11	Biosense Webster (Israel), Ltd.	Multiple bipolar sampling

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3760280A (en) *	1972-06-07	1973-09-18	Taft Broadcasting Corp	Method and apparatus for delaying an electrical signal
US4035661A (en) *	1974-06-27	1977-07-12	University Of Alabama In Birmingham	Electronic timer
US4271483A (en) *	1977-08-04	1981-06-02	Independent Broadcasting Authority	Delay circuits
JPS5592012A (en) *	1978-12-29	1980-07-12	Fujitsu Ltd	Variable delay circuit
US4468624A (en) *	1980-07-23	1984-08-28	The United States Of America As Represented By The Secretary Of The Air Force	Programmable synchronous digital delay line
JPS6056097B2 (ja) *	1981-08-17	1985-12-09	日立化成工業株式会社	ポリオレフィン樹脂発泡体の製法
JPS58215123A (ja) *	1982-06-07	1983-12-14	Advantest Corp	多相タイミング発生装置
JPS5963813A (ja) *	1982-10-02	1984-04-11	Kazuyoshi Kanematsu	遅延回路
JPS6094523A (ja) *	1983-10-28	1985-05-27	Nec Corp	可変ビツト遅延回路
US4731835A (en) *	1984-11-19	1988-03-15	Nippon Gakki Seizo Kabushiki Kaisha	Reverberation tone generating apparatus
JPS62231508A (ja) *	1986-03-31	1987-10-12	Kokusai Electric Co Ltd	デイジタル遅延回路
JPS6332595A (ja) *	1986-07-25	1988-02-12	松下電器産業株式会社	エコ−ミユ−テイング装置

1989
- 1989-04-20 JP JP1100775A patent/JPH02279015A/ja active Pending
1990
- 1990-04-18 US US07/510,702 patent/US5073733A/en not_active Expired - Lifetime
- 1990-04-19 CA CA002014969A patent/CA2014969C/en not_active Expired - Lifetime
- 1990-04-19 KR KR1019900005479A patent/KR970000561B1/ko not_active IP Right Cessation
- 1990-04-20 DE DE69021616T patent/DE69021616T2/de not_active Expired - Fee Related
- 1990-04-20 EP EP90107577A patent/EP0393716B1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
DE69021616T2 (de)	1996-04-18
JPH02279015A (ja)	1990-11-15
KR900017291A (ko)	1990-11-15
KR970000561B1 (ko)	1997-01-13
CA2014969A1 (en)	1990-10-20
EP0393716A2 (de)	1990-10-24
EP0393716A3 (de)	1991-05-15
US5073733A (en)	1991-12-17
EP0393716B1 (de)	1995-08-16
CA2014969C (en)	1999-11-09

Publication	Publication Date	Title
DE69019670D1 (de)	1995-06-29	Verzögerungsmessschaltung.
DE69016850D1 (de)	1995-03-23	Lade-Entladeschaltung.
DE69018108D1 (de)	1995-05-04	Servo-Stromkreis.
DE3850629D1 (de)	1994-08-18	Adaptierbarer Schaltkreis.
FI890607A0 (fi)	1989-02-08	Kopplingsanordning.
DE59003933D1 (de)	1994-02-03	Bauelement.
DE3881855D1 (de)	1993-07-22	Signalverzoegerungsschaltung.
DE69023817D1 (de)	1996-01-11	Verzögerungsschaltung mit stabiler Verzögerungszeit.
DE69017601D1 (de)	1995-04-13	Schaltungsanordnung.
DE59009760D1 (de)	1995-11-16	Bremskreis.
DE69008464D1 (de)	1994-06-01	Schaltungsanordnung.
DE69001914D1 (de)	1993-07-22	Kommutierende schaltung.
DE68901985D1 (de)	1992-08-13	Verzoegerungsschaltung.
ATE106630T1 (de)	1994-06-15	Speiseschaltung.
DE68916093D1 (de)	1994-07-21	Integrierte Schaltung.
EP0333864A4 (de)	1989-12-18	Emitterfolgerschaltung.
DE59009679D1 (de)	1995-10-26	Baugruppenträger.
DE69018587D1 (de)	1995-05-18	Steuerschaltung.
DE69021616D1 (de)	1995-09-21	Verzögerungsschaltung.
DE69023971D1 (de)	1996-01-18	Schaltungsmodul.
DE69023395D1 (de)	1995-12-14	Arbitrierungsschaltung.
DE69023358D1 (de)	1995-12-14	Logische Schaltung.
DE3888007D1 (de)	1994-04-07	Schutzschalter.
DE69008930D1 (de)	1994-06-23	Boostschaltung.
DE58906111D1 (de)	1993-12-09	Oszillatorschaltung.

Legal Events

Date	Code	Title	Description
1996-09-12	8364	No opposition during term of opposition
2010-02-18	8339	Ceased/non-payment of the annual fee