DE69014707D1 - Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren. - Google Patents
Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren.Info
- Publication number
- DE69014707D1 DE69014707D1 DE69014707T DE69014707T DE69014707D1 DE 69014707 D1 DE69014707 D1 DE 69014707D1 DE 69014707 T DE69014707 T DE 69014707T DE 69014707 T DE69014707 T DE 69014707T DE 69014707 D1 DE69014707 D1 DE 69014707D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- field effect
- effect transistors
- cmos field
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/345,875 US4874713A (en) | 1989-05-01 | 1989-05-01 | Method of making asymmetrically optimized CMOS field effect transistors |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69014707D1 true DE69014707D1 (de) | 1995-01-19 |
DE69014707T2 DE69014707T2 (de) | 1995-07-27 |
Family
ID=23356881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69014707T Expired - Lifetime DE69014707T2 (de) | 1989-05-01 | 1990-04-27 | Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4874713A (de) |
EP (1) | EP0396357B1 (de) |
JP (1) | JP2942998B2 (de) |
DE (1) | DE69014707T2 (de) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006477A (en) * | 1988-11-25 | 1991-04-09 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
US5079180A (en) * | 1988-12-22 | 1992-01-07 | Texas Instruments Incorporated | Method of fabricating a raised source/drain transistor |
US5286998A (en) * | 1989-05-31 | 1994-02-15 | Fujitsu Limited | Semiconductor device having two transistors forming a memory cell and a peripheral circuit, wherein the impurity region of the first transistor is not subjected to an etching atmosphere |
US5070029A (en) * | 1989-10-30 | 1991-12-03 | Motorola, Inc. | Semiconductor process using selective deposition |
US5296401A (en) * | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
IT1239707B (it) * | 1990-03-15 | 1993-11-15 | St Microelectrics Srl | Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain |
KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
US6078079A (en) * | 1990-04-03 | 2000-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US5262344A (en) * | 1990-04-27 | 1993-11-16 | Digital Equipment Corporation | N-channel clamp for ESD protection in self-aligned silicided CMOS process |
US5045486A (en) * | 1990-06-26 | 1991-09-03 | At&T Bell Laboratories | Transistor fabrication method |
US5286664A (en) * | 1991-10-01 | 1994-02-15 | Nec Corporation | Method for fabricating the LDD-MOSFET |
EP0575688B1 (de) * | 1992-06-26 | 1998-05-27 | STMicroelectronics S.r.l. | Programmierung von LDD-ROM-Zellen |
US5342798A (en) * | 1993-11-23 | 1994-08-30 | Vlsi Technology, Inc. | Method for selective salicidation of source/drain regions of a transistor |
US6720627B1 (en) | 1995-10-04 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device having junction depths for reducing short channel effect |
US5960319A (en) | 1995-10-04 | 1999-09-28 | Sharp Kabushiki Kaisha | Fabrication method for a semiconductor device |
KR0161885B1 (ko) * | 1995-12-26 | 1999-02-01 | 문정환 | 반도체 소자와 그의 제조방법 |
US6037254A (en) * | 1996-10-31 | 2000-03-14 | Texas Instruments Incorporated | Method of making a surface protective layer for improved silicide formation |
JPH1168103A (ja) * | 1997-08-22 | 1999-03-09 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
TW359886B (en) * | 1997-09-02 | 1999-06-01 | United Microelectronics Corp | Electrostatic discharge protection device and production process therefor |
US6001721A (en) * | 1998-02-19 | 1999-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide and salicide on the same chip |
US6710424B2 (en) | 2001-09-21 | 2004-03-23 | Airip | RF chipset architecture |
JP4483179B2 (ja) * | 2003-03-03 | 2010-06-16 | 株式会社デンソー | 半導体装置の製造方法 |
US20060267130A1 (en) * | 2003-06-26 | 2006-11-30 | Rj Mears, Llc | Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween |
US9000525B2 (en) | 2010-05-19 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3686080A (en) * | 1971-07-21 | 1972-08-22 | Rca Corp | Method of fabrication of semiconductor devices |
US3747200A (en) * | 1972-03-31 | 1973-07-24 | Motorola Inc | Integrated circuit fabrication method |
JPS567304B2 (de) * | 1972-08-28 | 1981-02-17 | ||
US4267012A (en) * | 1979-04-30 | 1981-05-12 | Fairchild Camera & Instrument Corp. | Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer |
US4622735A (en) * | 1980-12-12 | 1986-11-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device utilizing self-aligned silicide regions |
US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
JPS5950567A (ja) * | 1982-09-16 | 1984-03-23 | Hitachi Ltd | 電界効果トランジスタの製造方法 |
US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
JPH0695563B2 (ja) * | 1985-02-01 | 1994-11-24 | 株式会社日立製作所 | 半導体装置 |
US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
US4722909A (en) * | 1985-09-26 | 1988-02-02 | Motorola, Inc. | Removable sidewall spacer for lightly doped drain formation using two mask levels |
US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
US4711701A (en) * | 1986-09-16 | 1987-12-08 | Texas Instruments Incorporated | Self-aligned transistor method |
EP0292042B1 (de) * | 1987-05-14 | 1992-08-26 | Koninklijke Philips Electronics N.V. | Verfahren zur Halbleiterherstellung, wobei unter Verwendung einer Hilfsoxidation die Tunnelausbildung bei der Wolframabscheidung reduziert wird |
-
1989
- 1989-05-01 US US07/345,875 patent/US4874713A/en not_active Expired - Lifetime
-
1990
- 1990-04-23 JP JP2105493A patent/JP2942998B2/ja not_active Expired - Lifetime
- 1990-04-27 DE DE69014707T patent/DE69014707T2/de not_active Expired - Lifetime
- 1990-04-27 EP EP90304631A patent/EP0396357B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02303157A (ja) | 1990-12-17 |
DE69014707T2 (de) | 1995-07-27 |
EP0396357A1 (de) | 1990-11-07 |
US4874713A (en) | 1989-10-17 |
EP0396357B1 (de) | 1994-12-07 |
JP2942998B2 (ja) | 1999-08-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR |
|
8328 | Change in the person/name/address of the agent |
Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US |