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DE69012345D1 - Methode und vorrichtung für fehlanalyse in halbleiterfabrikation. - Google Patents

Methode und vorrichtung für fehlanalyse in halbleiterfabrikation.

Info

Publication number
DE69012345D1
DE69012345D1 DE69012345T DE69012345T DE69012345D1 DE 69012345 D1 DE69012345 D1 DE 69012345D1 DE 69012345 T DE69012345 T DE 69012345T DE 69012345 T DE69012345 T DE 69012345T DE 69012345 D1 DE69012345 D1 DE 69012345D1
Authority
DE
Germany
Prior art keywords
failure analysis
semiconductor factory
factory
semiconductor
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69012345T
Other languages
English (en)
Other versions
DE69012345T2 (de
Inventor
Alain Comeau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne Digital Imaging Inc
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Publication of DE69012345D1 publication Critical patent/DE69012345D1/de
Application granted granted Critical
Publication of DE69012345T2 publication Critical patent/DE69012345T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Environmental & Geological Engineering (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69012345T 1989-12-01 1990-11-26 Methode und vorrichtung für fehlanalyse in halbleiterfabrikation. Expired - Fee Related DE69012345T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002004436A CA2004436C (en) 1989-12-01 1989-12-01 Test chip for use in semiconductor fault analysis
PCT/CA1990/000416 WO1991008585A1 (en) 1989-12-01 1990-11-26 Method and device for semiconductor fabrication fault analasys

Publications (2)

Publication Number Publication Date
DE69012345D1 true DE69012345D1 (de) 1994-10-13
DE69012345T2 DE69012345T2 (de) 1995-05-11

Family

ID=4143687

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69012345T Expired - Fee Related DE69012345T2 (de) 1989-12-01 1990-11-26 Methode und vorrichtung für fehlanalyse in halbleiterfabrikation.

Country Status (7)

Country Link
US (1) US5329228A (de)
EP (1) EP0502884B1 (de)
JP (1) JP2997048B2 (de)
KR (1) KR100213393B1 (de)
CA (1) CA2004436C (de)
DE (1) DE69012345T2 (de)
WO (1) WO1991008585A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US5829128A (en) 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
US5751621A (en) * 1994-11-17 1998-05-12 Hitachi, Ltd. Multiply-add unit and data processing apparatus using it
US5751015A (en) * 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
US5889410A (en) * 1996-05-22 1999-03-30 International Business Machines Corporation Floating gate interlevel defect monitor and method
US5872018A (en) * 1997-05-05 1999-02-16 Vanguard International Semiconductor Corporation Testchip design for process analysis in sub-micron DRAM fabrication
TW559970B (en) * 2001-04-05 2003-11-01 Kawasaki Microelectronics Inc Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit
JP2006024598A (ja) 2004-07-06 2006-01-26 Fujitsu Ltd 半導体装置の製造方法
USD1012421S1 (en) 2020-08-07 2024-01-30 Zuru (Singapore) Pte. Ltd. Confectionery
AU2020329071A1 (en) 2019-08-09 2022-02-24 Zuru (Singapore) Pte. Ltd. Gummy confectionery-coated non-edible container
KR102479995B1 (ko) * 2020-11-16 2022-12-21 충남대학교 산학협력단 신소자 테스트 시스템 및 신소자 테스트 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits
US4719411A (en) * 1985-05-13 1988-01-12 California Institute Of Technology Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation
US4835466A (en) * 1987-02-06 1989-05-30 Fairchild Semiconductor Corporation Apparatus and method for detecting spot defects in integrated circuits
US4961192A (en) * 1988-07-29 1990-10-02 International Business Machines Corporation Data error detection and correction

Also Published As

Publication number Publication date
KR100213393B1 (ko) 1999-08-02
EP0502884B1 (de) 1994-09-07
US5329228A (en) 1994-07-12
JPH05504442A (ja) 1993-07-08
CA2004436C (en) 1999-06-29
CA2004436A1 (en) 1991-06-01
DE69012345T2 (de) 1995-05-11
EP0502884A1 (de) 1992-09-16
JP2997048B2 (ja) 2000-01-11
WO1991008585A1 (en) 1991-06-13
KR920704345A (ko) 1992-12-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ZARLINK SEMICONDUCTOR INC., KANATA, ONTARIO, CA

8327 Change in the person/name/address of the patent owner

Owner name: DALSA SEMICONDUCTOR INC., WATERLOO, ONTARIO, CA

8328 Change in the person/name/address of the agent

Representative=s name: VONNEMANN, KLOIBER & KOLLEGEN, 80796 MUENCHEN

8339 Ceased/non-payment of the annual fee