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DE69004932D1 - Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen. - Google Patents

Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen.

Info

Publication number
DE69004932D1
DE69004932D1 DE90110401T DE69004932T DE69004932D1 DE 69004932 D1 DE69004932 D1 DE 69004932D1 DE 90110401 T DE90110401 T DE 90110401T DE 69004932 T DE69004932 T DE 69004932T DE 69004932 D1 DE69004932 D1 DE 69004932D1
Authority
DE
Germany
Prior art keywords
production
semiconductor devices
dielectric trenches
wide dielectric
wide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE90110401T
Other languages
English (en)
Other versions
DE69004932T2 (de
Inventor
Michael L Kerbaugh
Iii Charles W Koburger
Brian J Machesney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69004932D1 publication Critical patent/DE69004932D1/de
Publication of DE69004932T2 publication Critical patent/DE69004932T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)
DE69004932T 1989-10-25 1990-06-01 Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen. Expired - Lifetime DE69004932T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42715389A 1989-10-25 1989-10-25

Publications (2)

Publication Number Publication Date
DE69004932D1 true DE69004932D1 (de) 1994-01-13
DE69004932T2 DE69004932T2 (de) 1994-05-19

Family

ID=23693699

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69004932T Expired - Lifetime DE69004932T2 (de) 1989-10-25 1990-06-01 Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen.

Country Status (3)

Country Link
EP (1) EP0424608B1 (de)
JP (1) JPH0779129B2 (de)
DE (1) DE69004932T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5246884A (en) * 1991-10-30 1993-09-21 International Business Machines Corporation Cvd diamond or diamond-like carbon for chemical-mechanical polish etch stop
KR100252692B1 (ko) * 1991-11-29 2000-04-15 이데이 노부유끼 폴리쉬공정을 구비한 트렌치아이솔레이션의 형성방법 및 반도체장치의 제조방법
DE69232648T2 (de) * 1991-11-29 2003-02-06 Sony Corp., Tokio/Tokyo Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung
JP2874486B2 (ja) * 1991-11-29 1999-03-24 ソニー株式会社 ポリッシュ工程を備えたトレンチアイソレーションの形成方法及び半導体装置の製造方法
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
US5382541A (en) * 1992-08-26 1995-01-17 Harris Corporation Method for forming recessed oxide isolation containing deep and shallow trenches
EP0597603A3 (de) * 1992-11-13 1998-03-11 Digital Equipment Corporation Planarization eines Isolationsgrabens mittels einer harten Maske
FR2717307B1 (fr) * 1994-03-11 1996-07-19 Maryse Paoli Procede d'isolement de zones actives d'un substrat semi-conducteur par tranchees peu profondes quasi planes, et dispositif correspondant
KR100329061B1 (ko) * 1994-03-15 2002-11-13 내셔널 세미콘덕터 코포레이션 평면화된트렌치및전계산화물분리방법
JP2757784B2 (ja) * 1994-08-29 1998-05-25 日本電気株式会社 半導体装置の製造方法
KR100361761B1 (ko) * 1995-06-02 2003-02-05 주식회사 하이닉스반도체 반도체소자의소자분리절연막형성방법
EP0853335A3 (de) * 1997-01-10 1999-01-07 Texas Instruments Incorporated Suspension und Verfahren zum mechnisch-chemischen Polieren von Halbleiteranordnungen
EP0855739A1 (de) * 1997-01-24 1998-07-29 Texas Instruments Inc. Verfahren zum Ätzen eines abgeschrägten Dielektrikums für das Rückätzen einer Grabenisolation
US5804490A (en) * 1997-04-14 1998-09-08 International Business Machines Corporation Method of filling shallow trenches
JPH11233609A (ja) * 1998-02-13 1999-08-27 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6284560B1 (en) * 1998-12-18 2001-09-04 Eastman Kodak Company Method for producing co-planar surface structures

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5976442A (ja) * 1982-10-26 1984-05-01 Toshiba Corp 半導体装置の製造方法
JPH0620098B2 (ja) * 1983-01-27 1994-03-16 日本電気株式会社 半導体装置の素子分離方法
JPS59141243A (ja) * 1983-02-02 1984-08-13 Mitsubishi Electric Corp 素子間分離の形成方法
JPS59217339A (ja) * 1983-05-26 1984-12-07 Toshiba Corp 半導体装置の製造方法
JPS6039835A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 基板表面の平坦化方法
JPS6217861A (ja) * 1985-07-17 1987-01-26 Hitachi Ltd 文書作成装置
US4671970A (en) * 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
FR2599892B1 (fr) * 1986-06-10 1988-08-26 Schiltz Andre Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique
NL8701717A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw.
US4962064A (en) * 1988-05-12 1990-10-09 Advanced Micro Devices, Inc. Method of planarization of topologies in integrated circuit structures

Also Published As

Publication number Publication date
EP0424608A1 (de) 1991-05-02
JPH03148155A (ja) 1991-06-24
JPH0779129B2 (ja) 1995-08-23
DE69004932T2 (de) 1994-05-19
EP0424608B1 (de) 1993-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)