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DE68924363D1 - Dielektrisch isolierte Bauelemente mit hoher Geschwindigkeit mit vergrabenen Silicid-Gebieten und Verfahren zu deren Herstellung. - Google Patents

Dielektrisch isolierte Bauelemente mit hoher Geschwindigkeit mit vergrabenen Silicid-Gebieten und Verfahren zu deren Herstellung.

Info

Publication number
DE68924363D1
DE68924363D1 DE68924363T DE68924363T DE68924363D1 DE 68924363 D1 DE68924363 D1 DE 68924363D1 DE 68924363 T DE68924363 T DE 68924363T DE 68924363 T DE68924363 T DE 68924363T DE 68924363 D1 DE68924363 D1 DE 68924363D1
Authority
DE
Germany
Prior art keywords
production
high speed
dielectrically insulated
silicide areas
buried silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924363T
Other languages
English (en)
Other versions
DE68924363T2 (de
Inventor
William Graham Easter
Anatoly Feygenson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE68924363D1 publication Critical patent/DE68924363D1/de
Publication of DE68924363T2 publication Critical patent/DE68924363T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/019Contacts of silicides
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/123Polycrystalline diffuse anneal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/147Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE68924363T 1988-03-30 1989-03-21 Dielektrisch isolierte Bauelemente mit hoher Geschwindigkeit mit vergrabenen Silicid-Gebieten und Verfahren zu deren Herstellung. Expired - Fee Related DE68924363T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/175,016 US4839309A (en) 1988-03-30 1988-03-30 Fabrication of high-speed dielectrically isolated devices utilizing buried silicide outdiffusion

Publications (2)

Publication Number Publication Date
DE68924363D1 true DE68924363D1 (de) 1995-11-02
DE68924363T2 DE68924363T2 (de) 1996-05-15

Family

ID=22638486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924363T Expired - Fee Related DE68924363T2 (de) 1988-03-30 1989-03-21 Dielektrisch isolierte Bauelemente mit hoher Geschwindigkeit mit vergrabenen Silicid-Gebieten und Verfahren zu deren Herstellung.

Country Status (5)

Country Link
US (1) US4839309A (de)
EP (1) EP0335557B1 (de)
JP (1) JP2641291B2 (de)
CA (1) CA1286038C (de)
DE (1) DE68924363T2 (de)

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* Cited by examiner, † Cited by third party
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US5343067A (en) * 1987-02-26 1994-08-30 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
US5227660A (en) * 1987-11-09 1993-07-13 Hitachi, Ltd. Semiconductor device
US4929996A (en) * 1988-06-29 1990-05-29 Texas Instruments Incorporated Trench bipolar transistor
JP2852679B2 (ja) * 1989-09-01 1999-02-03 富士通株式会社 半導体装置及びその製造方法
US5306942A (en) * 1989-10-11 1994-04-26 Nippondenso Co., Ltd. Semiconductor device having a shield which is maintained at a reference potential
US5098861A (en) * 1991-01-08 1992-03-24 Unitrode Corporation Method of processing a semiconductor substrate including silicide bonding
US5268326A (en) * 1992-09-28 1993-12-07 Motorola, Inc. Method of making dielectric and conductive isolated island
DE4306565C2 (de) * 1993-03-03 1995-09-28 Telefunken Microelectron Verfahren zur Herstellung eines blauempfindlichen Photodetektors
US5726084A (en) * 1993-06-24 1998-03-10 Northern Telecom Limited Method for forming integrated circuit structure
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
US5872044A (en) * 1994-06-15 1999-02-16 Harris Corporation Late process method for trench isolation
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
US5643821A (en) * 1994-11-09 1997-07-01 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
US6232649B1 (en) 1994-12-12 2001-05-15 Hyundai Electronics America Bipolar silicon-on-insulator structure and process
US5904535A (en) * 1995-06-02 1999-05-18 Hyundai Electronics America Method of fabricating a bipolar integrated structure
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
DE19716102C2 (de) * 1997-04-17 2003-09-25 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Bauelementen und Verfahren zu deren Herstellung
KR100244271B1 (ko) * 1997-05-06 2000-02-01 김영환 반도체소자 구조 및 제조방법
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
US6524890B2 (en) 1999-11-17 2003-02-25 Denso Corporation Method for manufacturing semiconductor device having element isolation structure
US6508363B1 (en) 2000-03-31 2003-01-21 Lucent Technologies Slurry container
US6544888B2 (en) * 2001-06-28 2003-04-08 Promos Technologies, Inc. Advanced contact integration scheme for deep-sub-150 nm devices
KR100414735B1 (ko) * 2001-12-10 2004-01-13 주식회사 하이닉스반도체 반도체소자 및 그 형성 방법
GB0314392D0 (en) * 2003-06-20 2003-07-23 Koninkl Philips Electronics Nv Trench mos structure
DE102004050740A1 (de) * 2004-10-19 2006-04-20 Atmel Germany Gmbh Halbleitergegenstand und Verfahren zur Herstellung
TWI274402B (en) * 2005-06-17 2007-02-21 Powerchip Semiconductor Corp Non-volatile memory and fabricating method thereof
DE102008000811A1 (de) 2007-03-29 2008-10-09 Basf Se Verfahren zur Herstellung von Papier
US8338265B2 (en) 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL144775B (nl) * 1964-09-23 1975-01-15 Philips Nv Halfgeleiderinrichting met meer dan een halfgeleiderschakelelement in een lichaam.
US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US3469147A (en) * 1966-07-05 1969-09-23 Union Carbide Corp Dielectrically isolated structures and method
US3653120A (en) * 1970-07-27 1972-04-04 Gen Electric Method of making low resistance polycrystalline silicon contacts to buried collector regions using refractory metal silicides
JPS4871574A (de) * 1971-12-25 1973-09-27
US3938176A (en) * 1973-09-24 1976-02-10 Texas Instruments Incorporated Process for fabricating dielectrically isolated semiconductor components of an integrated circuit
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
FR2480501A1 (fr) * 1980-04-14 1981-10-16 Thomson Csf Dispositif semi-conducteur a grille profonde accessible par la surface et procede de fabrication
US4553318A (en) * 1983-05-02 1985-11-19 Rca Corporation Method of making integrated PNP and NPN bipolar transistors and junction field effect transistor
JPS60198814A (ja) * 1984-03-23 1985-10-08 Nec Corp 半導体装置の製造方法
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer
US4593458A (en) * 1984-11-02 1986-06-10 General Electric Company Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices
JPS61248476A (ja) * 1985-04-26 1986-11-05 Hitachi Ltd 半導体装置の製造方法
JPS62190721A (ja) * 1986-02-17 1987-08-20 Seiko Epson Corp 半導体装置の製造方法
JPS62232965A (ja) * 1986-04-03 1987-10-13 Hitachi Ltd 半導体装置
JPH0638424B2 (ja) * 1986-07-31 1994-05-18 株式会社日立製作所 半導体装置の製造方法

Also Published As

Publication number Publication date
DE68924363T2 (de) 1996-05-15
EP0335557A3 (en) 1989-11-23
US4839309A (en) 1989-06-13
EP0335557A2 (de) 1989-10-04
JPH02216846A (ja) 1990-08-29
CA1286038C (en) 1991-07-09
EP0335557B1 (de) 1995-09-27
JP2641291B2 (ja) 1997-08-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee