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DE68915211D1 - Standardzelle. - Google Patents

Standardzelle.

Info

Publication number
DE68915211D1
DE68915211D1 DE68915211T DE68915211T DE68915211D1 DE 68915211 D1 DE68915211 D1 DE 68915211D1 DE 68915211 T DE68915211 T DE 68915211T DE 68915211 T DE68915211 T DE 68915211T DE 68915211 D1 DE68915211 D1 DE 68915211D1
Authority
DE
Germany
Prior art keywords
standard cell
cell
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915211T
Other languages
English (en)
Other versions
DE68915211T2 (de
Inventor
Tsuneaki Kudo
Hiroyuki Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE68915211D1 publication Critical patent/DE68915211D1/de
Application granted granted Critical
Publication of DE68915211T2 publication Critical patent/DE68915211T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE68915211T 1988-06-28 1989-06-28 Standardzelle. Expired - Fee Related DE68915211T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63158005A JP2739958B2 (ja) 1988-06-28 1988-06-28 スタンダードセル

Publications (2)

Publication Number Publication Date
DE68915211D1 true DE68915211D1 (de) 1994-06-16
DE68915211T2 DE68915211T2 (de) 1994-09-29

Family

ID=15662174

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915211T Expired - Fee Related DE68915211T2 (de) 1988-06-28 1989-06-28 Standardzelle.

Country Status (5)

Country Link
US (1) US5401988A (de)
EP (1) EP0348933B1 (de)
JP (1) JP2739958B2 (de)
KR (1) KR940001393B1 (de)
DE (1) DE68915211T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140505A (ja) * 1992-10-28 1994-05-20 Mitsubishi Electric Corp 半導体集積回路装置
US5675501A (en) * 1994-03-15 1997-10-07 Kabushiki Kaisha Toshiba Method of designing semiconductor integrated circuit apparatus having no dead space
DE69517693T2 (de) * 1995-12-29 2001-03-01 Stmicroelectronics S.R.L., Agrate Brianza Standardzellenbibliothek für den Entwurf von integrierten Schaltungen
US5949261A (en) 1996-12-17 1999-09-07 Cypress Semiconductor Corp. Method and circuit for reducing power and/or current consumption
US6255675B1 (en) * 1998-07-10 2001-07-03 Xilinx, Inc. Programmable capacitor for an integrated circuit
US6963510B1 (en) 1998-07-10 2005-11-08 Xilinx, Inc. Programmable capacitor and method of operating same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1579419A (en) * 1977-06-15 1980-11-19 Seiko Instr & Electronics Static induction transistor logic semi-conductor devices and integrated injection logic semi-conductor devices
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
US4198695A (en) * 1978-07-19 1980-04-15 Texas Instruments Incorporated Static semiconductor memory cell using data lines for voltage supply
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method
US4423432A (en) * 1980-01-28 1983-12-27 Rca Corporation Apparatus for decoding multiple input lines
JPS5827343A (ja) * 1981-08-10 1983-02-18 Matsushita Electronics Corp 半導体集積回路
JPS58142544A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体集積回路
JPS58166742A (ja) * 1982-03-29 1983-10-01 Nec Corp マスタ−スライス基板
US4516040A (en) * 1982-06-14 1985-05-07 Standard Microsystems Corporation High-speed merged plane logic function array
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
JPS60198843A (ja) * 1984-03-23 1985-10-08 Fujitsu Ltd マスタ−スライス方式集積回路
JPS6124250A (ja) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
JPS61185964A (ja) * 1985-02-13 1986-08-19 Toshiba Corp 半導体メモリ
JPS6320440U (de) * 1986-07-25 1988-02-10
US4949149A (en) * 1987-03-31 1990-08-14 Unisys Corporation Semicustom chip whose logic cells have narrow tops and wide bottoms
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
JPS6437034A (en) * 1987-08-01 1989-02-07 Ricoh Kk Standard cell
US4851893A (en) * 1987-11-19 1989-07-25 Exar Corporation Programmable active/passive cell structure

Also Published As

Publication number Publication date
JP2739958B2 (ja) 1998-04-15
EP0348933A2 (de) 1990-01-03
KR900001007A (ko) 1990-01-31
DE68915211T2 (de) 1994-09-29
JPH029149A (ja) 1990-01-12
KR940001393B1 (ko) 1994-02-21
EP0348933B1 (de) 1994-05-11
US5401988A (en) 1995-03-28
EP0348933A3 (en) 1990-11-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee