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DE68910841D1 - Verfahren zum Herstellen einer Halbleiteranordnung, wobei auf selbstregistrierende Art und Weise Metallsilicid angebracht wird. - Google Patents

Verfahren zum Herstellen einer Halbleiteranordnung, wobei auf selbstregistrierende Art und Weise Metallsilicid angebracht wird.

Info

Publication number
DE68910841D1
DE68910841D1 DE89200132T DE68910841T DE68910841D1 DE 68910841 D1 DE68910841 D1 DE 68910841D1 DE 89200132 T DE89200132 T DE 89200132T DE 68910841 T DE68910841 T DE 68910841T DE 68910841 D1 DE68910841 D1 DE 68910841D1
Authority
DE
Germany
Prior art keywords
self
manufacturing
semiconductor device
metal silicide
registering manner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89200132T
Other languages
English (en)
Other versions
DE68910841T2 (de
Inventor
Kazimierz Osinski
Ingrid Johanna Voors
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE68910841D1 publication Critical patent/DE68910841D1/de
Publication of DE68910841T2 publication Critical patent/DE68910841T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE68910841T 1988-01-29 1989-01-24 Verfahren zum Herstellen einer Halbleiteranordnung, wobei auf selbstregistrierende Art und Weise Metallsilicid angebracht wird. Expired - Fee Related DE68910841T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8800222A NL8800222A (nl) 1988-01-29 1988-01-29 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht.

Publications (2)

Publication Number Publication Date
DE68910841D1 true DE68910841D1 (de) 1994-01-05
DE68910841T2 DE68910841T2 (de) 1994-05-19

Family

ID=19851680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68910841T Expired - Fee Related DE68910841T2 (de) 1988-01-29 1989-01-24 Verfahren zum Herstellen einer Halbleiteranordnung, wobei auf selbstregistrierende Art und Weise Metallsilicid angebracht wird.

Country Status (6)

Country Link
US (1) US4885259A (de)
EP (1) EP0327152B1 (de)
JP (1) JPH025435A (de)
KR (1) KR890012402A (de)
DE (1) DE68910841T2 (de)
NL (1) NL8800222A (de)

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JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
US5374576A (en) * 1988-12-21 1994-12-20 Hitachi, Ltd. Method of fabricating stacked capacitor cell memory devices
US20010008288A1 (en) * 1988-01-08 2001-07-19 Hitachi, Ltd. Semiconductor integrated circuit device having memory cells
US5153145A (en) * 1989-10-17 1992-10-06 At&T Bell Laboratories Fet with gate spacer
US5306655A (en) * 1990-07-24 1994-04-26 Matsushita Electric Industrial Co., Ltd. Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions
JPH04217373A (ja) * 1990-12-18 1992-08-07 Sharp Corp 不揮発性記憶装置およびその製造方法
JP3061891B2 (ja) * 1991-06-21 2000-07-10 キヤノン株式会社 半導体装置の製造方法
KR960000225B1 (ko) * 1991-08-26 1996-01-03 가부시키가이샤 한도오따이 에네루기 겐큐쇼 절연게이트형 반도체장치의 제작방법
JP2997123B2 (ja) * 1992-04-03 2000-01-11 株式会社東芝 半導体装置の製造方法
US5411907A (en) * 1992-09-01 1995-05-02 Taiwan Semiconductor Manufacturing Company Capping free metal silicide integrated process
JPH06140396A (ja) * 1992-10-23 1994-05-20 Yamaha Corp 半導体装置とその製法
KR0140464B1 (ko) * 1993-08-26 1998-07-15 세끼자와 다다시 실리사이드 전극을 갖는 반도체장치의 제조방법
TW297142B (de) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
US6777763B1 (en) 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
JP3030368B2 (ja) 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US5438006A (en) * 1994-01-03 1995-08-01 At&T Corp. Method of fabricating gate stack having a reduced height
JPH07263684A (ja) * 1994-03-25 1995-10-13 Mitsubishi Electric Corp 電界効果トランジスタの製造方法
US6200871B1 (en) * 1994-08-30 2001-03-13 Texas Instruments Incorporated High performance self-aligned silicide process for sub-half-micron semiconductor technologies
FR2734402B1 (fr) * 1995-05-15 1997-07-18 Brouquet Pierre Procede pour l'isolement electrique en micro-electronique, applicable aux cavites etroites, par depot d'oxyde a l'etat visqueux et dispositif correspondant
US5858844A (en) * 1995-06-07 1999-01-12 Advanced Micro Devices, Inc. Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process
US6009476A (en) * 1995-11-21 1999-12-28 Diamond Multimedia Systems, Inc. Device driver architecture supporting emulation environment
US6289396B1 (en) 1995-11-21 2001-09-11 Diamond Multimedia Systems, Inc. Dynamic programmable mode switching device driver architecture
US5752032A (en) * 1995-11-21 1998-05-12 Diamond Multimedia Systems, Inc. Adaptive device driver using controller hardware sub-element identifier
US6393495B1 (en) 1995-11-21 2002-05-21 Diamond Multimedia Systems, Inc. Modular virtualizing device driver architecture
KR100206878B1 (ko) * 1995-12-29 1999-07-01 구본준 반도체소자 제조방법
JPH104092A (ja) * 1996-06-14 1998-01-06 Nec Corp 半導体装置の製造方法
US5705417A (en) * 1996-06-19 1998-01-06 Vanguard International Semiconductor Corporation Method for forming self-aligned silicide structure
US5691212A (en) * 1996-09-27 1997-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. MOS device structure and integration method
US5753557A (en) * 1996-10-07 1998-05-19 Vanguard International Semiconductor Company Bridge-free self aligned silicide process
US5744395A (en) * 1996-10-16 1998-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure
US5783486A (en) * 1996-10-18 1998-07-21 Vanguard International Semiconductor Corporation Bridge-free self aligned silicide process
TW346652B (en) * 1996-11-09 1998-12-01 Winbond Electronics Corp Semiconductor production process
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6603180B1 (en) * 1997-11-28 2003-08-05 Advanced Micro Devices, Inc. Semiconductor device having large-area silicide layer and process of fabrication thereof
US6015736A (en) * 1997-12-19 2000-01-18 Advanced Micro Devices, Inc. Method and system for gate stack reoxidation control
US5895244A (en) * 1998-01-08 1999-04-20 Texas Instruments - Acer Incorporated Process to fabricate ultra-short channel nMOSFETs with self-aligned silicide contact
US6821855B2 (en) 2002-08-29 2004-11-23 Micron Technology, Inc. Reverse metal process for creating a metal silicide transistor gate structure
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EP2230684B1 (de) * 2003-07-08 2013-10-30 Infineon Technologies AG Herstellungsverfahren für integrierte Schaltungsanordnung mit niederohmigen Kontakten
JP2006237453A (ja) * 2005-02-28 2006-09-07 Toshiba Corp 半導体装置及びその製造方法
CN101987985B (zh) * 2009-08-04 2013-05-22 财团法人工业技术研究院 一种组合物及其用途
US8741704B2 (en) 2012-03-08 2014-06-03 International Business Machines Corporation Metal oxide semiconductor (MOS) device with locally thickened gate oxide

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US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
JPS58154270A (ja) * 1982-03-09 1983-09-13 Toshiba Corp 半導体装置の製造方法
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US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
US4587710A (en) * 1984-06-15 1986-05-13 Gould Inc. Method of fabricating a Schottky barrier field effect transistor
US4587718A (en) * 1984-11-30 1986-05-13 Texas Instruments Incorporated Process for forming TiSi2 layers of differing thicknesses in a single integrated circuit
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US4663191A (en) * 1985-10-25 1987-05-05 International Business Machines Corporation Salicide process for forming low sheet resistance doped silicon junctions
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers

Also Published As

Publication number Publication date
US4885259A (en) 1989-12-05
KR890012402A (ko) 1989-08-26
JPH025435A (ja) 1990-01-10
NL8800222A (nl) 1989-08-16
DE68910841T2 (de) 1994-05-19
EP0327152B1 (de) 1993-11-24
EP0327152A1 (de) 1989-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee