DE60143643D1 - Integriertes halbleiterschaltungsbauelement - Google Patents
Integriertes halbleiterschaltungsbauelementInfo
- Publication number
- DE60143643D1 DE60143643D1 DE60143643T DE60143643T DE60143643D1 DE 60143643 D1 DE60143643 D1 DE 60143643D1 DE 60143643 T DE60143643 T DE 60143643T DE 60143643 T DE60143643 T DE 60143643T DE 60143643 D1 DE60143643 D1 DE 60143643D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit element
- semiconductor circuit
- integrated semiconductor
- integrated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B28/00—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements
- C04B28/02—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing hydraulic cements other than calcium sulfates
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
- H10D89/105—Integrated device layouts adapted for thermal considerations
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2103/00—Function or property of ingredients for mortars, concrete or artificial stone
- C04B2103/0068—Ingredients with a function or property not provided for elsewhere in C04B2103/00
- C04B2103/0097—Anion- and far-infrared-emitting materials
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00017—Aspects relating to the protection of the environment
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00439—Physico-chemical properties of the materials not provided for elsewhere in C04B2111/00
- C04B2111/00456—Odorless cements
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
- C04B2111/00482—Coating or impregnation materials
- C04B2111/00517—Coating or impregnation materials for masonry
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/20—Resistance against chemical, physical or biological attack
- C04B2111/2092—Resistance against biological degradation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nanotechnology (AREA)
- Inorganic Chemistry (AREA)
- Structural Engineering (AREA)
- Theoretical Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Organic Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000038167A JP4191355B2 (ja) | 2000-02-10 | 2000-02-10 | 半導体集積回路装置 |
PCT/JP2001/000887 WO2001059789A1 (en) | 2000-02-10 | 2001-02-08 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60143643D1 true DE60143643D1 (de) | 2011-01-27 |
Family
ID=18561945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60143643T Expired - Lifetime DE60143643D1 (de) | 2000-02-10 | 2001-02-08 | Integriertes halbleiterschaltungsbauelement |
Country Status (9)
Country | Link |
---|---|
US (3) | US6611458B2 (de) |
EP (1) | EP1262996B1 (de) |
JP (1) | JP4191355B2 (de) |
KR (2) | KR100817343B1 (de) |
CN (2) | CN100590739C (de) |
AU (1) | AU2001232248A1 (de) |
DE (1) | DE60143643D1 (de) |
TW (1) | TW506135B (de) |
WO (1) | WO2001059789A1 (de) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BR9815420A (pt) * | 1997-11-28 | 2001-07-17 | Abb Ab | Método e dispositivo para controlar o fluxo magnético com um enrolamento auxiliar em uma máquina rotativa de alta voltagem de corrente alternada |
US6829737B1 (en) * | 2000-08-30 | 2004-12-07 | Micron Technology, Inc. | Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results |
JP4043703B2 (ja) * | 2000-09-04 | 2008-02-06 | 株式会社ルネサステクノロジ | 半導体装置、マイクロコンピュータ、及びフラッシュメモリ |
DE10120670B4 (de) * | 2001-04-27 | 2008-08-21 | Qimonda Ag | Verfahren zur Reparatur von Hardwarefehlern in Speicherbausteinen |
US7068544B2 (en) | 2001-08-30 | 2006-06-27 | Micron Technology, Inc. | Flash memory with low tunnel barrier interpoly insulators |
US7135734B2 (en) * | 2001-08-30 | 2006-11-14 | Micron Technology, Inc. | Graded composition metal oxide tunnel barrier interpoly insulators |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7075829B2 (en) * | 2001-08-30 | 2006-07-11 | Micron Technology, Inc. | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US7087954B2 (en) * | 2001-08-30 | 2006-08-08 | Micron Technology, Inc. | In service programmable logic arrays with low tunnel barrier interpoly insulators |
US6963103B2 (en) * | 2001-08-30 | 2005-11-08 | Micron Technology, Inc. | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
JP3821697B2 (ja) | 2001-12-07 | 2006-09-13 | エルピーダメモリ株式会社 | 半導体集積回路装置のベリファイ方法および半導体集積回路装置 |
US6943575B2 (en) * | 2002-07-29 | 2005-09-13 | Micron Technology, Inc. | Method, circuit and system for determining burn-in reliability from wafer level burn-in |
JP2004079138A (ja) * | 2002-08-22 | 2004-03-11 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
EP1453062B1 (de) * | 2003-02-27 | 2006-06-28 | STMicroelectronics S.r.l. | Eingebautes Testverfahren in einem Flash Speicher |
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- 2000-02-10 JP JP2000038167A patent/JP4191355B2/ja not_active Expired - Lifetime
-
2001
- 2001-01-30 TW TW090101806A patent/TW506135B/zh not_active IP Right Cessation
- 2001-02-08 KR KR1020077023259A patent/KR100817343B1/ko not_active Expired - Lifetime
- 2001-02-08 WO PCT/JP2001/000887 patent/WO2001059789A1/ja active Application Filing
- 2001-02-08 CN CN01804803A patent/CN100590739C/zh not_active Expired - Lifetime
- 2001-02-08 AU AU2001232248A patent/AU2001232248A1/en not_active Abandoned
- 2001-02-08 KR KR1020027006867A patent/KR100816924B1/ko not_active Expired - Lifetime
- 2001-02-08 CN CN201010003815.7A patent/CN101916591B/zh not_active Expired - Lifetime
- 2001-02-08 EP EP01904349A patent/EP1262996B1/de not_active Expired - Lifetime
- 2001-02-08 DE DE60143643T patent/DE60143643D1/de not_active Expired - Lifetime
- 2001-02-12 US US09/780,393 patent/US6611458B2/en not_active Expired - Lifetime
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2003
- 2003-06-25 US US10/602,684 patent/US6894944B2/en not_active Expired - Lifetime
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- 2005-03-07 US US11/072,309 patent/US7149113B2/en not_active Expired - Lifetime
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EP1262996A1 (de) | 2002-12-04 |
KR20020080340A (ko) | 2002-10-23 |
KR100817343B1 (ko) | 2008-03-27 |
US6611458B2 (en) | 2003-08-26 |
JP2001229690A (ja) | 2001-08-24 |
AU2001232248A1 (en) | 2001-08-20 |
JP4191355B2 (ja) | 2008-12-03 |
EP1262996A4 (de) | 2007-06-27 |
US20040004879A1 (en) | 2004-01-08 |
WO2001059789A1 (en) | 2001-08-16 |
CN1398407A (zh) | 2003-02-19 |
TW506135B (en) | 2002-10-11 |
US7149113B2 (en) | 2006-12-12 |
KR20070108570A (ko) | 2007-11-12 |
CN101916591A (zh) | 2010-12-15 |
US20010019499A1 (en) | 2001-09-06 |
CN101916591B (zh) | 2014-05-07 |
US6894944B2 (en) | 2005-05-17 |
EP1262996B1 (de) | 2010-12-15 |
US20050152186A1 (en) | 2005-07-14 |
CN100590739C (zh) | 2010-02-17 |
KR100816924B1 (ko) | 2008-03-26 |
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