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DE60042416D1 - Verfahren und vorrichtung zur ladebefehlsausführung - Google Patents

Verfahren und vorrichtung zur ladebefehlsausführung

Info

Publication number
DE60042416D1
DE60042416D1 DE60042416T DE60042416T DE60042416D1 DE 60042416 D1 DE60042416 D1 DE 60042416D1 DE 60042416 T DE60042416 T DE 60042416T DE 60042416 T DE60042416 T DE 60042416T DE 60042416 D1 DE60042416 D1 DE 60042416D1
Authority
DE
Germany
Prior art keywords
loading commands
commands
loading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60042416T
Other languages
English (en)
Inventor
Marc Tremblay
Jeffrey Meng Chan
Subramania Sudharsanan
Sharada Yeluri
Biyu Pan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60042416D1 publication Critical patent/DE60042416D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
DE60042416T 1999-10-01 2000-09-29 Verfahren und vorrichtung zur ladebefehlsausführung Expired - Lifetime DE60042416D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/410,842 US6542988B1 (en) 1999-10-01 1999-10-01 Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file
PCT/US2000/026873 WO2001025904A1 (en) 1999-10-01 2000-09-29 Method and apparatus for processing load instructions

Publications (1)

Publication Number Publication Date
DE60042416D1 true DE60042416D1 (de) 2009-07-30

Family

ID=23626462

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60042416T Expired - Lifetime DE60042416D1 (de) 1999-10-01 2000-09-29 Verfahren und vorrichtung zur ladebefehlsausführung

Country Status (6)

Country Link
US (1) US6542988B1 (de)
EP (1) EP1221088B1 (de)
JP (1) JP2004520634A (de)
AU (1) AU7988900A (de)
DE (1) DE60042416D1 (de)
WO (1) WO2001025904A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7188232B1 (en) * 2000-05-03 2007-03-06 Choquette Jack H Pipelined processing with commit speculation staging buffer and load/store centric exception handling
US6681317B1 (en) * 2000-09-29 2004-01-20 Intel Corporation Method and apparatus to provide advanced load ordering
US6725338B2 (en) * 2000-11-21 2004-04-20 Sun Microsystems, Inc. Method and apparatus for preventing cache pollution in microprocessors with speculative address loads
US20030005423A1 (en) * 2001-06-28 2003-01-02 Dong-Yuan Chen Hardware assisted dynamic optimization of program execution
US7124331B2 (en) 2002-05-14 2006-10-17 Sun Microsystems, Inc. Method and apparatus for providing fault-tolerance for temporary results within a CPU
US7360220B2 (en) * 2002-10-31 2008-04-15 Intel Corporation Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm
US8667252B2 (en) * 2002-11-21 2014-03-04 Stmicroelectronics, Inc. Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US7200742B2 (en) 2005-02-10 2007-04-03 International Business Machines Corporation System and method for creating precise exceptions
US8447962B2 (en) * 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
US10387151B2 (en) 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US7984273B2 (en) 2007-12-31 2011-07-19 Intel Corporation System and method for using a mask register to track progress of gathering elements from memory
US8239843B2 (en) * 2008-03-11 2012-08-07 Oracle America, Inc. Value predictable variable scoping for speculative automatic parallelization with transactional memory
US8380964B2 (en) 2009-04-03 2013-02-19 International Business Machines Corporation Processor including age tracking of issue queue instructions
US10175990B2 (en) 2009-12-22 2019-01-08 Intel Corporation Gathering and scattering multiple data elements
US8972697B2 (en) 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US9626333B2 (en) 2012-06-02 2017-04-18 Intel Corporation Scatter using index array and finite state machine
US9395990B2 (en) * 2013-06-28 2016-07-19 Intel Corporation Mode dependent partial width load to wider register processors, methods, and systems
US10936321B2 (en) * 2019-02-01 2021-03-02 International Business Machines Corporation Instruction chaining

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893233A (en) * 1988-04-18 1990-01-09 Motorola, Inc. Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit
US5689653A (en) * 1995-02-06 1997-11-18 Hewlett-Packard Company Vector memory operations
US5903918A (en) 1995-08-23 1999-05-11 Sun Microsystems, Inc. Program counter age bits
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5781790A (en) * 1995-12-29 1998-07-14 Intel Corporation Method and apparatus for performing floating point to integer transfers and vice versa
US5987598A (en) * 1997-07-07 1999-11-16 International Business Machines Corporation Method and system for tracking instruction progress within a data processing system
US6615338B1 (en) 1998-12-03 2003-09-02 Sun Microsystems, Inc. Clustered architecture in a VLIW processor
US6336168B1 (en) * 1999-02-26 2002-01-01 International Business Machines Corporation System and method for merging multiple outstanding load miss instructions
AU7622400A (en) 1999-10-01 2001-05-10 Sun Microsystems, Inc. A method for precise trap handling in case of speculative and out-of-order loads
US6598122B2 (en) * 2000-04-19 2003-07-22 Hewlett-Packard Development Company, L.P. Active load address buffer

Also Published As

Publication number Publication date
EP1221088A1 (de) 2002-07-10
AU7988900A (en) 2001-05-10
EP1221088B1 (de) 2009-06-17
US6542988B1 (en) 2003-04-01
WO2001025904A1 (en) 2001-04-12
JP2004520634A (ja) 2004-07-08

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