DE3852911D1 - In einer einzelnen Wanne enthaltender Transistor sowie Verfahren zu dessen Herstellung. - Google Patents
In einer einzelnen Wanne enthaltender Transistor sowie Verfahren zu dessen Herstellung.Info
- Publication number
- DE3852911D1 DE3852911D1 DE3852911T DE3852911T DE3852911D1 DE 3852911 D1 DE3852911 D1 DE 3852911D1 DE 3852911 T DE3852911 T DE 3852911T DE 3852911 T DE3852911 T DE 3852911T DE 3852911 D1 DE3852911 D1 DE 3852911D1
- Authority
- DE
- Germany
- Prior art keywords
- making
- same
- single well
- transistor contained
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
- H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/051—Manufacture or treatment of vertical BJTs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/068,373 US4772566A (en) | 1987-07-01 | 1987-07-01 | Single tub transistor means and method |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3852911D1 true DE3852911D1 (de) | 1995-03-16 |
DE3852911T2 DE3852911T2 (de) | 1995-10-05 |
Family
ID=22082145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3852911T Expired - Fee Related DE3852911T2 (de) | 1987-07-01 | 1988-06-13 | In einer einzelnen Wanne enthaltender Transistor sowie Verfahren zu dessen Herstellung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4772566A (de) |
EP (1) | EP0297335B1 (de) |
JP (1) | JP2632931B2 (de) |
KR (1) | KR970004458B1 (de) |
DE (1) | DE3852911T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812417A (en) * | 1986-07-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making self aligned external and active base regions in I.C. processing |
GB2236901A (en) * | 1989-09-20 | 1991-04-17 | Philips Nv | A method of manufacturing a semiconductor device |
US5281544A (en) * | 1990-07-23 | 1994-01-25 | Seiko Epson Corporation | Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors |
DE4434108A1 (de) * | 1994-09-23 | 1996-03-28 | Siemens Ag | Verfahren zur Erzeugung eines niederohmigen Kontaktes zwischen einer Metallisierungsschicht und einem Halbleitermaterial |
JP3489265B2 (ja) * | 1995-05-19 | 2004-01-19 | ソニー株式会社 | 半導体装置の製法 |
JP2907323B2 (ja) * | 1995-12-06 | 1999-06-21 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5786623A (en) * | 1996-10-22 | 1998-07-28 | Foveonics, Inc. | Bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region |
US6262472B1 (en) | 1999-05-17 | 2001-07-17 | National Semiconductor Corporation | Bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
US6043130A (en) * | 1999-05-17 | 2000-03-28 | National Semiconductor Corporation | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
JP2003017408A (ja) * | 2001-06-29 | 2003-01-17 | Sanyo Electric Co Ltd | 半導体膜、半導体膜の形成方法、半導体装置の製造方法 |
US7300850B2 (en) * | 2005-09-30 | 2007-11-27 | Semiconductor Components Industries, L.L.C. | Method of forming a self-aligned transistor |
US8735289B2 (en) * | 2010-11-29 | 2014-05-27 | Infineon Technologies Ag | Method of contacting a doping region in a semiconductor substrate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4127931A (en) * | 1974-10-04 | 1978-12-05 | Nippon Electric Co., Ltd. | Semiconductor device |
NL7900280A (nl) * | 1979-01-15 | 1980-07-17 | Philips Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
US4338622A (en) * | 1979-06-29 | 1982-07-06 | International Business Machines Corporation | Self-aligned semiconductor circuits and process therefor |
DE2946963A1 (de) * | 1979-11-21 | 1981-06-04 | Siemens AG, 1000 Berlin und 8000 München | Schnelle bipolare transistoren |
US4545114A (en) * | 1982-09-30 | 1985-10-08 | Fujitsu Limited | Method of producing semiconductor device |
DE3330895A1 (de) * | 1983-08-26 | 1985-03-14 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen |
JPS60194558A (ja) * | 1984-03-16 | 1985-10-03 | Hitachi Ltd | 半導体装置の製造方法 |
US4640721A (en) * | 1984-06-06 | 1987-02-03 | Hitachi, Ltd. | Method of forming bipolar transistors with graft base regions |
NL8402856A (nl) * | 1984-09-18 | 1986-04-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US4641416A (en) * | 1985-03-04 | 1987-02-10 | Advanced Micro Devices, Inc. | Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter |
US4571817A (en) * | 1985-03-15 | 1986-02-25 | Motorola, Inc. | Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion implantations |
US4740478A (en) * | 1987-01-30 | 1988-04-26 | Motorola Inc. | Integrated circuit method using double implant doping |
-
1987
- 1987-07-01 US US07/068,373 patent/US4772566A/en not_active Expired - Lifetime
-
1988
- 1988-06-13 EP EP88109369A patent/EP0297335B1/de not_active Expired - Lifetime
- 1988-06-13 DE DE3852911T patent/DE3852911T2/de not_active Expired - Fee Related
- 1988-06-23 JP JP63153674A patent/JP2632931B2/ja not_active Expired - Fee Related
- 1988-06-28 KR KR1019880007811A patent/KR970004458B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0297335A3 (en) | 1990-06-13 |
EP0297335B1 (de) | 1995-02-01 |
KR970004458B1 (ko) | 1997-03-27 |
DE3852911T2 (de) | 1995-10-05 |
JPS6422063A (en) | 1989-01-25 |
JP2632931B2 (ja) | 1997-07-23 |
KR890003029A (ko) | 1989-04-12 |
EP0297335A2 (de) | 1989-01-04 |
US4772566A (en) | 1988-09-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |