DE3744467C1 - Fail-safe digital filter - Google Patents

Abstract

A simple fail-safe digital filter is to be created for monitoring an input signal which is subject to tolerances, which can be constructed of non-safe filters and which can be used for monitoring the significant errors of an input signal. According to the invention, the filter is constructed of more than three, preferably four identical mutually parallel and intrinsically non-safe filter channels (I to IV) which are ANDed (5) at the output end, the filter channels (I to IV) being supplied with derived pulses (1) of the differentiated rectified input signal (f) for monitoring the frequency and duty ratio of the input signal (f), which filter channels cause a subsequent channel monostable flip flop (18) to output a continuous-1 signal (7) as long as these pulses (1) fall within the defined window time ( DELTA t) of a 2nd filter monostable flip flop (17) which is controlled by a preceding 1st filter monostable flip flop (16> and, for monitoring for pulse overshoots and break-HAZARDS, each of the filter channels (I to IV) is connected in parallel with an arrangement in which detector monostable flip flops (22, 23) respond to irregularly collapsing edges of the input signal (f) during defined test times (ttest) of preceding monostable flip flops (20, 21) and activate a turn-off monostable flip flop (24), the signal (6) of which turns off the associated channel monostable flip flop (18). <IMAGE>

Description

The invention is based on a signal-safe digital filter for monitoring a tolerant input signal.

Such digital filters are u. a. for failsafe shutdowns in safety-relevant Controls z. B. the railway technology needed where a signal defined frequency as a "live signal" is an indication of a travel authorization. This "live signal" can e.g. B. from a control center via line conductors Train sent and evaluated as a 1 signal for trip approval. At The train must not drive a 0 signal. Neither if the filter fails. In terms of signal technology, safe means that the filter output in such errors always on the safe side, d. H. 0 signal must go.

Such filters are difficult and expensive to implement.

The object of the invention is a simple, signal-safe To create digital filters that are made up of unsafe filters and with which the whole range of possible errors of an input signal can be monitored. Such errors are exceptions, for example the clock frequency tolerance, errors in the duty cycle and random errors due to signal peaks or dips.

The task is performed according to the characterizing features of the claim 1 solved. Advantageous configurations are the subclaims removable.

The invention results in a simple, clear circuit,  which fits as a multiple filter on a plug-in board in terms of component expenditure. Inexpensive common components can be used. Advantageous is also the low power consumption.

Using schematic exemplary embodiments and pulse diagrams the invention is explained in more detail below.

Show it:

Fig. 1 is an overview diagram of a complete fail safe filter,

Fig. 2 is a block diagram for one channel of the filter with the monitoring circuit,

Fig. 3 to 9 pulse diagrams for the circuit of FIG. 2 for various operating and error conditions.

According to Fig. 1 a to be monitored signal f is an input E multiple, here four parallel filter channels I, II, III, IV with identical, non-reactive and independent filter circuits 1, 2, 3, 4 are fed, which itself is not to be signaltechnich sure need. The outputs a of the individual digital filter circuits 1 to 4 are then routed via a signal-safe AND link 5 . The signal security is indicated here by the blackened corner. The actual signal output of the complete filter is labeled A. Instead of the AND link 5 , a safe parallel comparator can also be used.

Only if all four digital filter circuits have the same initial condition a = 1, the filter output A are logically from the first Quadruple availability is e.g. Currently accepted as a signal-safe standard by the DB and may be used in safety-relevant systems. It is not to be assumed that the same errors will occur in all four channels simultaneously within a certain failure disclosure time.

According to the invention, each digital filter circuit 1 to 4 also includes a monitoring circuit (watchdog circuit) (not shown here in more detail in FIG. 1) for special errors, which will only be discussed in FIG. 2 below. Fig. 2 shows in a block diagram the structure of the filter according to the invention in more detail, but only in sections for one channel including monitoring circuit, here z. B. for filter channel I. The other channels II to IV are identical.

Then each channel of the digital filter consists of an input stage, consisting of the components 6 to 15 and the actual digital filter circuit with the filter monoflops 16 and 17 , a channel monoflop 18 and a NAND gate 19 , and the monitoring circuit (watchdog circuit), consisting of the series monoflops 20, 21 , detector monoflops 22, 23 , a switch-off monoflop 24 and a further NAND gate 25 .

The signal f to be monitored, which is present at the input E and is subject to frequency tolerance, reaches an inverter 7 via a blocking diode chain 6 arranged in the blocking direction, and the supply voltage + U _V is also present at its input via a limiting resistor 8 . The circuit is designed so that the positive supply voltage + U _{V is} sucked off at each low level at input E , so that a low signal is also present at the inverter 7 in a mirrored manner. The inverting signal at the output of the inverter 7 is fed to the actual filter circuit via differentiating frequency high-pass elements 9 and 10 or 13, 14 . In this case passes on a rising edge of the input signal f is a pulse via diode 11 and a negative edge inverted by inverter 12, a pulse via a diode 11 to the filter circuit. A terminating resistor is designated by 15 .

In addition to the actual filter circuit with the elements16 to 19th the monitoring circuit is still important as an additional circuit. they is framed by dash-dotted lines and is composed of the retriggerable ones (NT) ballast monoflops20, 21that are inverted by the different edges of the Signalf are controlled and the reset inputs  not retriggerable (NNT) detector monoflops22, 23 act upon. These will from the edges of the signalf controlled directly. The exits  the detector monoflops 22, 23 are via another NAND gate25th linked one Switch-off monoflop24th supplied that the channel monoflop when random errors occur  18th switches off.

To function

When switching on the supply voltage +U _V will initially - not closer shown - for the canal monoflop18th a short reset signal at the input  with which the channel monoflop18th set to zero and the output undefined signals is prevented.

The normal operation of the filter circuit according to FIG. 2 can be seen in FIG. 3. The input signal of a certain fundamental frequency f _G present at input E , which is to be monitored, is shown under f . The signal images occurring at defined points in the circuit according to FIG. 2 are designated by.

The input signal has a fundamental frequencyf _G and the duty cycle 1: 1 the same timest _H andt _L. In the input circuit afterFig. 2nd with the elements9, 10, 11 and12, 13, 14, 11 a the 0/1 edges and the 1/0 edges of the input signalf differentiated (signal). With the rising edge of each differentiated input signal will retriggerable (NT = retriggerable) monoflop16 kicked off the one 1 signal of limited durationt _min outputs (signal) unless it is again is triggered with a positive edge of. The falling edge The signal in turn encounters the non-retriggerable (NNT = not retriggerable) filter monoflop17th which is a 1 signal of duration Δ _t  (Window time) outputs (signal). This signal as well as the impulses of the input signal are in the NAND gate19th linked and result in a Signal. The falling edge of this signal hits the retriggerable Canal monoflop18th with the hold timet _Stop at. The canal monoflop18th becomes normally always beforet _Stop retriggered and gives error-free operation, a constant 1 signal off (signal). The hold time by Kanalomonoflop18th is approximately 1.5 ×t _H or 1.5 ×t _L. signal is the correct output signal of the filter circuit.  

For the holding timest _min and Δ t the filter monoflops16 and17th applies with an upper limit frequencyf _O and a lower cutoff frequencyf _u:

t _min = 0.5 /f _O for filter monoflop16 and
Δ t = 0.5 /f _u-t _min for filter monoflop17th.

The monoflops16, 17, 18, 20, 21 need to be relatively accurate on their hold time be compared. This must be done with particular care for filter monoflop16  ont _min and filter monoflop17th on Δ t happen since these times are the Determine filter bandwidth. The holding times of the monoflops22, 23 and24th  are not so relevant for the function of the filter circuit. With the Further figures show the behavior of the filter circuit in the event of deviations described in frequency and duty cycle.

Figs. 4 and 5 show the behavior of the filter circuit for breach of the duty cycle t _{H: L} t of the input frequency f. In FIG. 4 is t _H <t _L; in Fig. 5 is t _H < t _L. In both cases, as can be seen, the channel monoflop 18 is only retriggered once for the signal after the error has occurred. A further retriggering does not take place since the differentiated input edges of the signal and the pulses of filter monoflop 17 then no longer overlap in time. The NAND gate 19 with signal remains permanently at 1, as a result of which there is no longer an edge available for triggering channel monoflop 18 . In both cases of FIGS. 4 and 5 , a drop in the signal, ie an error, can be determined.

FIGS. 6 and 7 show the behavior of the filter circuit at a frequency f is above an upper limit frequency f _o and unterhalbt a lower limit frequency f _u. The same applies to Figures 4 and 5. Signal goes to 0, the error can be determined.

As can be seen, the output of a 1 signal is based on the outputa the filter circuit on the fact that the signal is permanent and timely Signal change occurs through which the channel monoflop18th is retriggered. If the frequency or duty cycle drifts out, the short 1 peak falls from the signal no longer in the window interval Δ t by Filtermonoflop 17th with signal, whereby the signal remains high and no 0-dip with evaluable falling edge for channel monoflop18th more available stands. Outputa with signal then goes to 0 after the hold time has expired.

Description of the function of the further monitoring

If there is a shorter 0-dip or a 1-peak in the input signal f during the window time t (signal) cf. Fig. 8, the circuit described so far may be of such a random error (which is also intended to lead to the shutdown of the filter) not detect. As shown in Fig. 8, namely, the trigger then the resultant multiple-1 peaks of the signal channel monostable 18 after. That is, despite this error, the signal would remain high.

The additional monitoring circuit can also be the occurrence of such random errors to recognize and provide for a shutdown at the output a (see. Fig. 9).

The output signals of ballast monoflops 20 (signal) and ballast monoflop 21 (signal) are already entered in FIG. 3 in the case of error-free operation.

The ballast monoflop20th is in each case from a rising edge, i.e. H. here through inverter7, by the inverted, falling edge of the input signal f triggered and gives a 1-pulse (signal) of length t _{check 1} on the reset input  from detector monoflop23. This makes the detector monoflop 23 armed for the detection of a rising edge During this timet _{check 1}. Ballast monoflop21st is falling from the Edge of the input signalf triggered and gives a 1 pulse of length  t _{check 2} on the reset input  from detector monoflop22. This makes the detector monoflop 22 armed for the detection of a falling edge During the timet _{check 2}.

The series monoflops 20 and 21 are retriggerable (NT). The times t _{check 1} for signal and t _{check 2} for signal are the same, but the signals are _staggered .

In FIG. 3, as described "watchdog circuit" is still ineffective because no random errors. Even in the cases shown in FIGS. 4 to 7, the watchdog circuit does not affect the switch-off behavior of the filter circuit.

Fig. 9 shows the function when a 1-peak occurs within the Window time Δ t. Detector monoflop22 is - as described - by the Ballast monoflop21st for the timet _{check 2} (Signal) armed and can directly recognize and give the rising edge of the 1-peak a 0 pulse of lengtht _p (Signal) to his -Output that over the NAND gate25th on the switch-off monoflop24th works. Detector monoflop23, that reacts to falling edges leads during this time on the output side also 0 (signal), so that the NAND gate25th at his negated output a 1 pulse of lengtht _p can map. The starting monoflop 24th reacts to the positive edge and switches his -Exit (Signal) for timet _{switch off} to 0 and thus causes the reset by Filtermonoflop18th, which immediately switches to 0 (signal). The same thing happens when falling edges of 0-dips are detected, only that then the detector monoflop23 comes into play first when it gets through the ballast monoflop20th for the timet _{check 2} (Signal) armed is.

Due to the signal-safe filter according to the invention, the tasks can be solved easily and safely.

Claims (7)

1. Signal-safe digital filter for monitoring a tolerant input signal, characterized in that the filter is made up of more than three identical, parallel and even unsafe filter channels (I to IV), which are AND-linked on the output side ( 5 ), whereby for frequency and duty cycle monitoring of the input signal (f), the filter channels ( I to IV) derived pulses () of the differentiated, rectified input signal (f) are fed, which - as long as these pulses () into the defined window time ( Δ t) of a second Filter monoflops ( 17 ) fall, which is controlled by an upstream first filter monoflop ( 16 ) - cause a downstream channel monoflop ( 18 ) to emit a permanent 1 signal () and, for monitoring for pulse-like random errors, each of the filter channels (I to IV) an arrangement is connected in parallel, in the detector monoflops ( 22, 23 ) during defined test _times (t _test ) of ballast Respond to monoflops ( 20, 21 ) on irregularly incident edges of the input signal (f) and activate a switch-off monoflop ( 24 ) whose signal () switches off the associated channel monoflop ( 18 ). 2. Digital filter according to claim 1, characterized in that the input signal (f) via a reverse blocking diode chain ( 6 ) is fed to the input of an inverter ( 7 ) to which the supply voltage (+ U _V ) is additionally supplied via a limiting resistor ( 8 ) ) connected. 3. Digital filter according to claim 1 or 2, characterized in that the output of the inverter ( 7 ) via a first differentiating high-pass filter ( 9, 10 ) and a diode ( 11 ) and via a further inverter ( 12 ) and a second high-pass filter ( 13 , 14 ) with a subsequent diode ( 11 a) is connected on the one hand to the input of the first filter monoflop ( 16 ) responding to rising edges for a retriggerable hold time (t _min ) and on the other hand is connected to an input of a NAND gate ( 19 ). 4. Digital filter according to claim 3, characterized in that the output (Q) of the first filter monoflop ( 16 ) is connected to the input of a responding to falling edge, non-retriggerable second filter monoflop ( 17 ) for the window time ( Δ t) , whose output (Q) applied to the second input of the NAND gate ( 19 ). 5. Digital filter according to one of claims 1 to 4, characterized in that the inverting output of the NAND gate ( 19 ) is connected to the input of a channel monoflop ( 18 ) responding to a falling edge for a retriggerable hold time (t _stop ), the output of which (a) leads to the AND link ( 5 ). 6. Digital filter according to claim 1 or 2, characterized in that the input signal (f) once directly and before the inverter ( 7 ) to two non-retriggerable, responsive to rising and falling edge detector monoflops ( 22, 23 ) and once indirectly behind Inverters ( 7 ) inverted to two retriggerable ballast monoflops ( 20, 21 ) responsive to rising and falling flanks for the test _times (t _{test 1} , t _{test 2} ) and with their signals () to the reset inputs () of the corresponding detector - Monoflops ( 22, 23 ) are laid. 7. Digital filter according to claim 6, characterized in that the signals at the two outputs () of the detector monoflops ( 22, 23 ) via a linking NAND gate ( 25 ) to the input of a responding to rising edge, retriggerable switch-off monoflops ( 24 ) are placed, the output () (signal) of which is connected to the reset connection () of the associated channel monoflop ( 18 ).