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DE3621917A1 - Method for producing electrical connections inside semiconductor components and electrical connection for semiconductor components - Google Patents

Method for producing electrical connections inside semiconductor components and electrical connection for semiconductor components

Info

Publication number
DE3621917A1
DE3621917A1 DE19863621917 DE3621917A DE3621917A1 DE 3621917 A1 DE3621917 A1 DE 3621917A1 DE 19863621917 DE19863621917 DE 19863621917 DE 3621917 A DE3621917 A DE 3621917A DE 3621917 A1 DE3621917 A1 DE 3621917A1
Authority
DE
Germany
Prior art keywords
semiconductor chip
semiconductor components
bond
contact surface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19863621917
Other languages
German (de)
Inventor
Dieter Dipl Phys Dr Seipler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE19863621917 priority Critical patent/DE3621917A1/en
Priority to JP62156720A priority patent/JPS6310535A/en
Priority to KR1019870006604A priority patent/KR880001046A/en
Publication of DE3621917A1 publication Critical patent/DE3621917A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Due to the fact that in a semiconductor component, bonding first occurs to contact areas outside the semiconductor chip and only then at the semiconductor chip, considerable advantages are produced with respect to alignment accuracy, less risk of short circuits and simpler test and repair possibilities. <IMAGE>

Description

Stand der TechnikState of the art

Die Erfindung bezieht sich auf ein Verfahren zur Her­ stellung elektrischer Verbindungen innerhalb von Halb­ leiterbauelementen und eine elektrische Verbindung für Halb­ leiterbauelemente.The invention relates to a method for Her position of electrical connections within half conductor components and an electrical connection for half ladder components.

Zur Herstellung elektrischer Verbindungen innerhalb von Halbleiterbauelementen werden sehr dünne Drähte mit Durchmesser von beispielsweise 33 µm verwendet. Das Verfahren zur Anbringung der Verbindungsdrähte wird üblicherweise als Bonden bezeichnet, wobei als Bond­ drähte dünne Aluminiumdrähte verwendet werden. Die Bond­ drähte werden auf den zu verbindenden Kontaktflächen unter Anwendung von Ultraschall an ihren Enden ver­ schweißt. Es können hierfür auch Gold-Bonddrähte verwendet werden. Das Bonden wird von Bond-Automaten durchgeführt, wobei aufgrund der geringen Abmessungen der Kontaktflächen eine äußerst hohe Präzision erfor­ derlich ist. Die in herkömmlicher Technik hergestellten Bond-Verbindungen werden dabei dadurch hergestellt, daß zunächst auf einem Halbleiter-Chip das Ende des Bond­ Drahtes angeschweißt wird und danach die gewünschte Kontaktierung auf einer Kontaktfläche des Substrats vorgenommen wird. jedes Ende der Verbindung besitzt nur einen Schweißpunkt, weshalb es vorkommt, daß manche dieser Verbindungen sich nachträglich lösen oder nur mangelhaften Kontakt mit den Kontaktflächen eingehen.To make electrical connections within Semiconductor components are made with very thin wires Diameter of 33 microns used, for example. The Procedure for attaching the connecting wires usually referred to as bonding, whereby as a bond thin aluminum wires can be used. The bond wires are on the contact surfaces to be connected using ultrasound at their ends ver welds. Gold bond wires can also be used for this be used. The bonding is done by bond machines performed, due to the small dimensions the contact surfaces require extremely high precision is such. The manufactured in conventional technology Bond connections are made by that first the end of the bond on a semiconductor chip  Wire is welded and then the desired Contacting on a contact surface of the substrate is made. owns each end of the connection only one spot weld, which is why it happens that some of these connections become detached or only make poor contact with the contact surfaces.

Vorteile der ErfindungAdvantages of the invention

Das erfindungsgemäße Verfahren hat demgegenüber den Vorteil, daß die Treffergenauigkeit bezüglich der Kon­ taktflächen verbessert wird und eine Kurzschlußgefahr in Bezug auf benachbarte Leiterbahnen nicht besteht. Dies ergibt sich dadurch, daß zuerst auf den Kontakt­ flächen des Substrats eine Kontaktierung erfolgt und erst anschließend die Kontaktierung auf dem Halblei­ ter-Chip vorgenommen wird. Auf dem Halbleiter-Chip endet der Bonddraht exakt am Schweißpunkt, während bei umgekehrter Vorgehensweise, bei der die erste Kontaktierung auf dem Halbleiter-Chip erfolgt, am Halbleiter- Chip aufgrund des geringfügig abstehenden Drahtendes (Bondschwänzchen) Kurzschlußgefahr besteht. Außerdem wird der Draht bei der Bildung der Draht­ schleife (Loop) zwischen erster Kontaktierung und zweiter Kontaktierung zusätzlich ausgerichtet und beidseitig geführt, wodurch keine zusätzlichen Tole­ ranzen zwischen Draht und Bondkeil beim Abreißen und Wiedervorschieben auftreten. Dadurch erhält man eine Verbesserung der seitlichen Genauigkeit um ca. 5 µm.In contrast, the method according to the invention has the Advantage that the hit accuracy with regard to the Kon tact areas is improved and a risk of short circuit does not exist in relation to adjacent conductor tracks. This is because first on the contact surfaces of the substrate are contacted and only then the contact on the half lead ter chip is made. On the semiconductor chip the bond wire ends exactly at the welding point while with the reverse procedure, in which the first Contacting takes place on the semiconductor chip, on Semiconductor chip due to the slightly protruding There is a risk of a short circuit (wire tail). It also helps the wire form the wire Loop between first contact and second contacting additionally aligned and guided on both sides, which means no additional toles knot between wire and bond wedge when tearing and Re-advancing occur. This gives you an improvement in lateral accuracy of approx. 5 µm.

Der Übergang zum Schweißpunkt (Bond) auf dem Chip ist nicht mehr vorgeschwächt und erfährt keine Doppel­ biegung bei der Schleifenbildung. Außerdem wird der auf dem Halbleiter-Chip befindliche Bond beim Abrei­ ßen des Drahtes zerstörungsfrei geprüft.The transition to the weld spot (bond) on the chip is no longer weakened and no longer experiences double bend in loop formation. In addition, the bond on the semiconductor chip during the wiping  The wire is tested non-destructively.

Besonders vorteilhaft ist es, wenn die Verbindung so hergestellt wird, daß zunächst auf der Kontaktfläche auf dem Substrat zwei hintereinander angeordnete Schweißpunkte angebracht werden und dann erst die Kontaktierung auf dem Halbleiter-Chip erfolgt. Durch einen solchen Doppel-Bond, der auch als Doppel-Stitch- Bond bezeichnet werden kann, kann die Einstellung des elektrischen Kontakts auf dem Substrat optimiert wer­ den. Da nur einer der beiden Bonds halten muß und ei­ ne größere Goldoberfläche an den Kontaktflächen vor­ handen ist, wird eine sichere Kontaktierung erreicht. Es besteht dabei auch die Möglichkeit, einen der bei­ den auf dem Substrat befindlichen Schweißpunkte be­ züglich Haftung und den anderen bezüglich Querschnitt (Festigkeit) zu optimieren.It is particularly advantageous if the connection is so is made that first on the contact surface two arranged one behind the other on the substrate Welding spots are attached and only then Contacting takes place on the semiconductor chip. By such a double bond, which is also known as a double stitch Bond can be called, the attitude of the electrical contact on the substrate is optimized the. Since only one of the two bonds has to hold and egg ne larger gold surface on the contact surfaces safe contact is achieved. There is also the possibility of one of the the welding spots on the substrate regarding liability and the other regarding cross-section Optimize (strength).

Durch die Bondreihenfolge- zwei Bonds auf dem Substrat, danach Bond auf dem Halbleiter-Chip- können fehler­ hafte Bonds durch den Bond-Automat erkannt werden, bevor der Halbleiter-Chip kontaktiert wird. Unmittel­ bar nach Erkennen eines fehlerhaften Bonds kann eine sofortige Reparatur durchgeführt werden.Because of the bond order - two bonds on the substrate, then bond on the semiconductor chip can fail bonded bonds are recognized by the bond machine, before the semiconductor chip is contacted. Immediately cash after detection of a defective bond immediate repair can be done.

Das erfindungsgemäße Verfahren (Reverse-Bonden) bringt für Dickschicht-Layouts den Vorteil, daß der Abstand von Bauteilen zu benachbarten Bond-Kontaktstellen wesentlich reduziert werden kann, d.h. die Bauteile- Dichte kann erheblich erhöht werden. Daraus resultiert eine geringere Substratfläche bzw. eine höhere Funk­ tionsdichte.The inventive method (reverse bonding) brings for thick film layouts the advantage that the distance from components to neighboring bond contact points can be significantly reduced, i.e. the components Density can be increased significantly. This results a smaller substrate area or a higher radio density.

Eine nach dem erfindungsgemäßen Verfahren hergestellte elektrische Verbindung, bei der zwei Bond-Stellen auf der Kontaktfläche des Substrats und eine Bond-Stelle auf dem Halbleiter-Chip angebracht ist, besitzt die oben aufgeführten Vorteile.A manufactured by the method according to the invention electrical connection at which two bond points  the contact area of the substrate and a bond site attached to the semiconductor chip has the advantages listed above.

Zeichnungdrawing

Die Erfindung wird nachfolgend anhand der Zeichnung näher erläutert. Es zeigenThe invention is described below with reference to the drawing explained in more detail. Show it

Fig. 1 eine herkömmliche Drahtverbindung zwischen einer auf einem Substrat befindlichen Kontaktfläche und einer Kontaktfläche eines Halbleiter-Chips und Fig. 1 shows a conventional wire connection between a contact surface located on a substrate and a contact surface of a semiconductor chip and

Fig. 2 eine erfindungsgemäße Draht-Verbindung inner­ halb eines Halbleiter-Bauelements. Fig. 2 shows a wire connection according to the invention within half of a semiconductor device.

Bei der in Fig. 1 dargestellten Draht-Verbindung ist der Draht 1 (Bonddraht) nach Kontaktierung auf einem Halbleiter-Chip 2 mit der Kontaktfläche 3 ver­ schweißt worden, wobei der Halbleiter-Chip 2 und die Kontaktfläche 3 auf einem gemeinsamen Substrat 4 an­ geordnet sind.In the wire connection shown in FIG. 1, the wire 1 (bonding wire) has been welded after contacting on a semiconductor chip 2 with the contact surface 3 , the semiconductor chip 2 and the contact surface 3 being arranged on a common substrate 4 are.

Die in Fig. 2 dargestellte Verbindung besitzt zwei Schweißpunkte 5, 6, die auch als Bond-Stellen bezeich­ net werden können, zwischen denen der Draht 10 (Bond- Draht) eine kleine Schleife bildet. Nach der Kontak­ tierung am Punkt 5 und der darauffolgenden Kontaktie­ rung am Punkt 6 wird der Draht 10 in einer größeren Schleife zu einer auf dem Halbleiter-Chip 2 befindlichen Kontaktfläche 7 geführt, dort verschweißt und abge­ rissen. Der sogenannte Doppel-Bond (5, 6) bringt außer einer höheren Treffsicherheit eine sicherere Kontak­ tierung mit sich, jedoch kann anstelle eines solchen Doppel-Bonds auch ein Einzel-Bond an der Kontaktfläche 3 vorgesehen sein, wodurch sich bereits beträchtliche Vorteile ergeben, die bereits in der Beschreibungs­ einleitung dargelegt sind.The connection shown in Fig. 2 has two welding points 5 , 6 , which can also be referred to as bond points, between which the wire 10 (bond wire) forms a small loop. After contacting at point 5 and the subsequent contacting at point 6 , the wire 10 is guided in a larger loop to a contact surface 7 located on the semiconductor chip 2 , welded there and torn off. The so-called double bond ( 5 , 6 ) brings with it a higher accuracy, a more secure contact, but instead of such a double bond, a single bond can also be provided on the contact surface 3 , which already gives considerable advantages are already set out in the introduction to the description.

Claims (3)

1. Verfahren zur Herstellung elektrischer Verbindungen mittels sehr dünner Drähte innerhalb von Halblei­ ter-Bauelementen mit wenigstens einem auf einem Substrat angeordneten Halbleiter-Chip, wobei die Drähte unter Anwendung von Ultraschall mit den Kon­ taktflächen verschweißt werden, dadurch gekenn­ zeichnet, daß die Drähte (10) je­ weils zuerst mit einer auf dem Substrat (4) be­ findlichen Kontaktfläche (3) und dann mit einer auf dem Halbleiter-Chip (2) befindlichen Kontaktfläche (7) verschweißt werden.1. A method for producing electrical connections by means of very thin wires within semiconductor components with at least one semiconductor chip arranged on a substrate, the wires being welded to the contact surfaces using ultrasound, characterized in that the wires ( 10 ) each Weil first with a on the substrate ( 4 ) be sensitive contact surface ( 3 ) and then with a on the semiconductor chip ( 2 ) located contact surface ( 7 ) are welded. 2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Drähte (10) mit der auf dem Substrat (4) befindlichen Kontaktflächen (3) an zwei im Abstand voneinander angeordneten Kontaktstellen (5, 6) und erst danach mit der Kontaktfläche (7) des Halblei­ ter-Chips (2) verschweißt werden.2. The method according to claim 1, characterized in that the wires ( 10 ) with the on the substrate ( 4 ) located contact surfaces ( 3 ) at two spaced-apart contact points ( 5 , 6 ) and only then with the contact surface ( 7 ) the semiconductor chip ( 2 ) are welded. 3. Elektrische Verbindung für Halbleiter-Bauelemente zwischen Halbleiter-Chip und einer auf einem Sub­ strat angeordneten Kontaktfläche, bei der sehr dünne Drähte mit den Kontaktflächen verschweißt sind, dadurch gekennzeichnet, daß die Drähte (10) auf der Kontaktfläche (3) des Substrats (4) jeweils an zwei Schweißpunkten (5, 6) und an der Kontakt­ fläche (7) des Halbleiter-Chips (2) an einem Schweiß­ punkt verschweißt sind.3. Electrical connection for semiconductor components between the semiconductor chip and a arranged on a sub strat contact surface, in which very thin wires are welded to the contact surfaces, characterized in that the wires ( 10 ) on the contact surface ( 3 ) of the substrate ( 4 ) are welded to two welding points ( 5 , 6 ) and to the contact surface ( 7 ) of the semiconductor chip ( 2 ) at one welding point.
DE19863621917 1986-06-30 1986-06-30 Method for producing electrical connections inside semiconductor components and electrical connection for semiconductor components Ceased DE3621917A1 (en)

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DE19863621917 DE3621917A1 (en) 1986-06-30 1986-06-30 Method for producing electrical connections inside semiconductor components and electrical connection for semiconductor components
JP62156720A JPS6310535A (en) 1986-06-30 1987-06-25 Manufacture of electrical connection in semiconductor structural element
KR1019870006604A KR880001046A (en) 1986-06-30 1987-06-29 Electrical connection method inside the semiconductor component

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US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method
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CN103311142B (en) * 2013-06-21 2016-08-17 深圳市振华微电子有限公司 Encapsulating structure and packaging technology thereof
CN105355617A (en) * 2015-11-25 2016-02-24 江苏欧密格光电科技股份有限公司 Structure for enhancing reliability of bonding wire in technology of bare chip and method thereof

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US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method
SG143060A1 (en) * 2005-05-10 2008-06-27 Kaijo Kk Wire loop, semiconductor device having same and wire bonding method
US8016182B2 (en) 2005-05-10 2011-09-13 Kaijo Corporation Wire loop, semiconductor device having same and wire bonding method

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JPS6310535A (en) 1988-01-18

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