[go: up one dir, main page]

DE3482679D1 - Verfahren zum herstellen elektrischer verbindungen auf einem halbleitersubstrat. - Google Patents

Verfahren zum herstellen elektrischer verbindungen auf einem halbleitersubstrat.

Info

Publication number
DE3482679D1
DE3482679D1 DE8484110060T DE3482679T DE3482679D1 DE 3482679 D1 DE3482679 D1 DE 3482679D1 DE 8484110060 T DE8484110060 T DE 8484110060T DE 3482679 T DE3482679 T DE 3482679T DE 3482679 D1 DE3482679 D1 DE 3482679D1
Authority
DE
Germany
Prior art keywords
semiconductor substrate
electrical connections
producing electrical
producing
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484110060T
Other languages
English (en)
Inventor
Mousa Hanna Ishaq
Stanley Roberts
James Gardner Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3482679D1 publication Critical patent/DE3482679D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8484110060T 1983-09-29 1984-08-23 Verfahren zum herstellen elektrischer verbindungen auf einem halbleitersubstrat. Expired - Lifetime DE3482679D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/537,128 US4490193A (en) 1983-09-29 1983-09-29 Method for making diffusions into a substrate and electrical connections thereto using rare earth boride materials

Publications (1)

Publication Number Publication Date
DE3482679D1 true DE3482679D1 (de) 1990-08-16

Family

ID=24141334

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484110060T Expired - Lifetime DE3482679D1 (de) 1983-09-29 1984-08-23 Verfahren zum herstellen elektrischer verbindungen auf einem halbleitersubstrat.

Country Status (4)

Country Link
US (1) US4490193A (de)
EP (1) EP0137980B1 (de)
JP (1) JPS6079721A (de)
DE (1) DE3482679D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137317A (ja) * 1984-12-10 1986-06-25 Agency Of Ind Science & Technol 半導体装置用電極材料
US5086016A (en) * 1990-10-31 1992-02-04 International Business Machines Corporation Method of making semiconductor device contact including transition metal-compound dopant source
DE19528991C2 (de) * 1995-08-07 2002-05-16 Infineon Technologies Ag Herstellungsverfahren für eine nichtflüchtige Speicherzelle
TW471123B (en) * 2000-07-06 2002-01-01 United Microelectronics Corp Manufacturing method for bit lines of mask ROM
JP2004241711A (ja) * 2003-02-07 2004-08-26 Matsushita Electric Ind Co Ltd 半導体装置
US6785120B1 (en) * 2003-07-03 2004-08-31 Micron Technology, Inc. Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and capacitor constructions comprising hafnium oxide

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340108A (en) * 1963-07-09 1967-09-05 Semi Elements Inc Laser materials
US3601888A (en) * 1969-04-25 1971-08-31 Gen Electric Semiconductor fabrication technique and devices formed thereby utilizing a doped metal conductor
JPS567304B2 (de) * 1972-08-28 1981-02-17
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4364166A (en) * 1979-03-01 1982-12-21 International Business Machines Corporation Semiconductor integrated circuit interconnections
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
US4227944A (en) * 1979-06-11 1980-10-14 General Electric Company Methods of making composite conductive structures in integrated circuits
US4245796A (en) * 1979-06-15 1981-01-20 Chromalloy American Corporation System for handling flexible sheet rolls
US4389255A (en) * 1980-01-14 1983-06-21 Burroughs Corporation Method of forming buried collector for bipolar transistor in a semiconductor by selective implantation of poly-si followed by oxidation and etch-off
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
US4378628A (en) * 1981-08-27 1983-04-05 Bell Telephone Laboratories, Incorporated Cobalt silicide metallization for semiconductor integrated circuits
US4481046A (en) * 1983-09-29 1984-11-06 International Business Machines Corporation Method for making diffusions into a substrate and electrical connections thereto using silicon containing rare earth hexaboride materials

Also Published As

Publication number Publication date
JPS6079721A (ja) 1985-05-07
US4490193A (en) 1984-12-25
EP0137980A2 (de) 1985-04-24
JPH0260054B2 (de) 1990-12-14
EP0137980A3 (en) 1987-09-02
EP0137980B1 (de) 1990-07-11

Similar Documents

Publication Publication Date Title
DE3586109D1 (de) Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung.
DE3381509D1 (de) Verfahren zum herstellen von halbleiteranordnungen.
DE3686600D1 (de) Verfahren zum herstellen einer harzumhuellten halbleiteranordnung.
DE3586732D1 (de) Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
DE3583934D1 (de) Verfahren zum herstellen einer halbleiterverbundanordnung.
DE3685970D1 (de) Verfahren zum herstellen eines halbleiterbauelements.
DE3483280D1 (de) Verfahren zum herstellen einer mehrschicht-halbleiteranordnung.
DE3786914D1 (de) Verfahren zum herstellen einer integrierten schaltungspackungsstruktur.
DE3483531D1 (de) Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.
DE3684759D1 (de) Verfahren zur herstellungeiner halbleitervorrichtung.
DE3780369D1 (de) Verfahren zum herstellen einer halbleiterstruktur.
DE3483579D1 (de) Verfahren zum herstellen einer leiterbahn.
DE3686453D1 (de) Verfahren zum herstellen einer duennen halbleiterschicht.
DE3584757D1 (de) Verfahren zum herstellen einer zwei-wannen-cmos-halbleiterstruktur.
DE3587231D1 (de) Verfahren zum herstellen einer dmos-halbleiteranordnung.
DE3381156D1 (de) Verfahren zum herstellen eines kondensators auf einem substrat.
DE3586439D1 (de) Elektrischer steckverbinder und verfahren zum herstellen desselben.
DE3684676D1 (de) Verfahren zum herstellen von halbleitersubstraten.
DE3583472D1 (de) Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode.
DE3583183D1 (de) Verfahren zur herstellung eines halbleitersubstrates.
DE3671583D1 (de) Verfahren zum herstellen eines halbleiter-speicherbauelementes.
DE3482352D1 (de) Verfahren zum herstellen eines dielektrischen substrats.
DE3382563D1 (de) Verfahren zum unterscheiden zwischen komplexen zeichenvorraeten.
DE68914939D1 (de) Verfahren zum Untereinanderverbinden von elektrischen Dünnschichtkreisen.
DE3778639D1 (de) Verfahren zum stapelverbinden von draehten.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee