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DE3376721D1 - Mos logic circuit - Google Patents

Mos logic circuit

Info

Publication number
DE3376721D1
DE3376721D1 DE8383107169T DE3376721T DE3376721D1 DE 3376721 D1 DE3376721 D1 DE 3376721D1 DE 8383107169 T DE8383107169 T DE 8383107169T DE 3376721 T DE3376721 T DE 3376721T DE 3376721 D1 DE3376721 D1 DE 3376721D1
Authority
DE
Germany
Prior art keywords
logic circuit
mos logic
mos
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383107169T
Other languages
English (en)
Inventor
Kenji Matsuo
Itsuo Sasaki
Hiroaki Suzuki
Mitsuyuki Kunieda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57133576A external-priority patent/JPS5923925A/ja
Priority claimed from JP57133541A external-priority patent/JPS5923924A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3376721D1 publication Critical patent/DE3376721D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE8383107169T 1982-07-30 1983-07-21 Mos logic circuit Expired DE3376721D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57133576A JPS5923925A (ja) 1982-07-30 1982-07-30 論理回路
JP57133541A JPS5923924A (ja) 1982-07-30 1982-07-30 論理回路

Publications (1)

Publication Number Publication Date
DE3376721D1 true DE3376721D1 (de) 1988-06-23

Family

ID=26467864

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383107169T Expired DE3376721D1 (de) 1982-07-30 1983-07-21 Mos logic circuit

Country Status (3)

Country Link
US (1) US4716308A (de)
EP (1) EP0101896B1 (de)
DE (1) DE3376721D1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102342A (ja) * 1986-10-20 1988-05-07 Mitsubishi Electric Corp 半導体集積回路装置の配線構造
US4849751A (en) * 1987-06-08 1989-07-18 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS Integrated circuit digital crossbar switching arrangement
DE3788132T2 (de) * 1987-12-01 1994-05-11 Ibm Logische Schaltkreisfamilie von Multibasis-bi-CMOS.
US5301349A (en) * 1988-12-28 1994-04-05 Kabushiki Kaisha Toshiba Single chip computer having ground wire formed immediately parallel a data bus and drivers formed directly under the data bus for high speed data transfer
US5170160A (en) * 1989-05-09 1992-12-08 Gte Laboratories Incorporated Broadband tree switch architecture for reducing pulse width narrowing and power dissipation
US5250823A (en) * 1989-10-24 1993-10-05 U.S. Philips Corp. Integrated CMOS gate-array circuit
JPH0472755A (ja) * 1990-07-13 1992-03-06 Sumitomo Electric Ind Ltd 化合物半導体集積装置
US5317204A (en) * 1991-04-12 1994-05-31 Hewlett-Packard Company Mitigating the adverse effects of charge sharing in dynamic logic circuits
JP2897507B2 (ja) * 1992-01-23 1999-05-31 三菱電機株式会社 半導体論理回路
JPH06104667A (ja) * 1992-09-18 1994-04-15 Takayama:Kk ヴォルテージ・フォロワ回路
GB9308944D0 (en) * 1993-04-30 1993-06-16 Inmos Ltd Ring oscillator
FR2714550B1 (fr) * 1993-12-24 1996-02-02 Bull Sa Arbre de portes logiques OU-Exclusif et multiplieur de fréquence l'incorporant.
US5426384A (en) * 1993-12-27 1995-06-20 Motorola, Inc. Voltage controlled oscillator (VCO) with symmetrical output and logic gate for use in same
US5612637A (en) * 1995-05-26 1997-03-18 National Semiconductor Corporation Supply and interface configurable input/output buffer
JP3202601B2 (ja) * 1996-07-01 2001-08-27 日本電気株式会社 論理回路及び半導体集積回路配列
JP3119177B2 (ja) * 1996-10-24 2000-12-18 日本電気株式会社 半導体装置
JP3173408B2 (ja) * 1997-03-13 2001-06-04 日本電気株式会社 信号多重化回路
US6130559A (en) * 1997-04-04 2000-10-10 Board Of Regents Of The University Of Texas System QMOS digital logic circuits
US5889416A (en) * 1997-10-27 1999-03-30 Cypress Semiconductor Corporation Symmetrical nand gates
US6097222A (en) * 1997-10-27 2000-08-01 Cypress Semiconductor Corp. Symmetrical NOR gates
GB9903253D0 (en) * 1999-02-12 1999-04-07 Sgs Thomson Microelectronics Logic circuit
JP2001077308A (ja) * 1999-06-28 2001-03-23 Ando Electric Co Ltd 論理積回路
KR100666475B1 (ko) * 2004-07-22 2007-01-09 삼성전자주식회사 고속 듀얼 모듈러스 프리스케일러를 구비한 분주기 및분주 방법
FR2938670B1 (fr) * 2008-11-17 2012-02-10 Stmicroelectronics Crolles Sas Dispositif de controle de l'activite de modules d'un reseau de modules de memoire
US8053814B2 (en) * 2009-04-08 2011-11-08 International Business Machines Corporation On-chip embedded thermal antenna for chip cooling
CN102136838A (zh) * 2010-12-16 2011-07-27 苏州华芯微电子股份有限公司 一种上拉电阻电路结构
JP2012217065A (ja) * 2011-04-01 2012-11-08 Fujitsu Ltd 可変遅延回路
CN108735163B (zh) 2018-05-30 2020-11-17 京东方科技集团股份有限公司 用于阵列基板行驱动单元的或逻辑运算电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4963371A (de) * 1972-10-19 1974-06-19
JPS5620734B2 (de) * 1973-07-31 1981-05-15
US3900742A (en) * 1974-06-24 1975-08-19 Us Navy Threshold logic using complementary mos device
US3986043A (en) * 1974-12-20 1976-10-12 International Business Machines Corporation CMOS digital circuits with active shunt feedback amplifier
JPS5641580A (en) * 1979-09-13 1981-04-18 Toshiba Corp Mos decoder circuit
JPS56125854A (en) * 1980-03-10 1981-10-02 Nec Corp Integrated circuit
US4367420A (en) * 1980-06-02 1983-01-04 Thompson Foss Incorporated Dynamic logic circuits operating in a differential mode for array processing
US4489246A (en) * 1980-12-24 1984-12-18 Fujitsu Limited Field effect transistor logic circuit having high operating speed and low power consumption
JPS58101525A (ja) * 1981-12-14 1983-06-16 Fujitsu Ltd 論理回路

Also Published As

Publication number Publication date
US4716308A (en) 1987-12-29
EP0101896A2 (de) 1984-03-07
EP0101896A3 (en) 1985-07-31
EP0101896B1 (de) 1988-05-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)