DE3176784D1 - A memory device, more particularly word line drive circuitry for a memory device - Google Patents
A memory device, more particularly word line drive circuitry for a memory deviceInfo
- Publication number
- DE3176784D1 DE3176784D1 DE8181301402T DE3176784T DE3176784D1 DE 3176784 D1 DE3176784 D1 DE 3176784D1 DE 8181301402 T DE8181301402 T DE 8181301402T DE 3176784 T DE3176784 T DE 3176784T DE 3176784 D1 DE3176784 D1 DE 3176784D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- word line
- line drive
- drive circuitry
- particularly word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55042489A JPS598913B2 (ja) | 1980-04-01 | 1980-04-01 | 記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3176784D1 true DE3176784D1 (en) | 1988-07-14 |
Family
ID=12637468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8181301402T Expired DE3176784D1 (en) | 1980-04-01 | 1981-03-31 | A memory device, more particularly word line drive circuitry for a memory device |
Country Status (5)
Country | Link |
---|---|
US (1) | US4536860A (de) |
EP (1) | EP0037285B1 (de) |
JP (1) | JPS598913B2 (de) |
DE (1) | DE3176784D1 (de) |
IE (1) | IE54461B1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61104394A (ja) * | 1984-10-22 | 1986-05-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
US4730275A (en) * | 1985-11-22 | 1988-03-08 | Motorola, Inc. | Circuit for reducing the row select voltage swing in a memory array |
JPH07105160B2 (ja) * | 1989-05-20 | 1995-11-13 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JPH0442495A (ja) * | 1990-06-07 | 1992-02-13 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6452858B1 (en) | 1999-11-05 | 2002-09-17 | Hitachi, Ltd. | Semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3541531A (en) * | 1967-02-07 | 1970-11-17 | Bell Telephone Labor Inc | Semiconductive memory array wherein operating power is supplied via information paths |
US3703711A (en) * | 1971-01-04 | 1972-11-21 | Honeywell Inf Systems | Memory cell with voltage limiting at transistor control terminals |
JPS5736670B2 (de) * | 1974-04-24 | 1982-08-05 | ||
US3986178A (en) * | 1975-07-28 | 1976-10-12 | Texas Instruments | Integrated injection logic random access memory |
JPS5833634B2 (ja) * | 1979-02-28 | 1983-07-21 | 富士通株式会社 | メモリセルアレイの駆動方式 |
-
1980
- 1980-04-01 JP JP55042489A patent/JPS598913B2/ja not_active Expired
-
1981
- 1981-03-31 DE DE8181301402T patent/DE3176784D1/de not_active Expired
- 1981-03-31 EP EP81301402A patent/EP0037285B1/de not_active Expired
- 1981-04-01 IE IE748/81A patent/IE54461B1/en unknown
-
1984
- 1984-01-06 US US06/568,952 patent/US4536860A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0037285A2 (de) | 1981-10-07 |
IE54461B1 (en) | 1989-10-25 |
JPS56140586A (en) | 1981-11-02 |
JPS598913B2 (ja) | 1984-02-28 |
EP0037285B1 (de) | 1988-06-08 |
EP0037285A3 (en) | 1983-05-18 |
US4536860A (en) | 1985-08-20 |
IE810748L (en) | 1981-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |