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DE3132645C2 - - Google Patents

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Publication number
DE3132645C2
DE3132645C2 DE3132645A DE3132645A DE3132645C2 DE 3132645 C2 DE3132645 C2 DE 3132645C2 DE 3132645 A DE3132645 A DE 3132645A DE 3132645 A DE3132645 A DE 3132645A DE 3132645 C2 DE3132645 C2 DE 3132645C2
Authority
DE
Germany
Prior art keywords
layer
glass
sio
zno
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3132645A
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German (de)
Other versions
DE3132645A1 (en
Inventor
Seiichi Suwa Nagano Jp Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suwa Seikosha KK
Original Assignee
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11502780A external-priority patent/JPS5739554A/en
Priority claimed from JP55115026A external-priority patent/JPS5739539A/en
Application filed by Suwa Seikosha KK filed Critical Suwa Seikosha KK
Publication of DE3132645A1 publication Critical patent/DE3132645A1/en
Application granted granted Critical
Publication of DE3132645C2 publication Critical patent/DE3132645C2/de
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

Die Erfindung betrifft ein Halbleiterbauelement nach dem Oberbegriff des Patentanspruchs.The invention relates to a semiconductor device according to the Preamble of the claim.

Ein solches Halbleiterbauelement ist aus der DE 28 09 233 A1 bekannt (dort insbesondere Fig. 3). Bei dem bekannten Halbleiterbauelement besteht die Glasschicht aus einem Phosphorsilikat. Die Glasschicht hat im Bereich der Kon­ taktlöcher beträchtliche Stufen. Diese Stufen wirken sich nachteilig auf die darüberliegenden Schichten aus, insbe­ sondere auf eine oberhalb der Glasschicht befindliche Iso­ lierschicht und die auf dieser Isolierschicht befindliche Verdrahtungsschicht, da sich die Konturen der Stufen auf diese Schichten übertragen, was zu einer Beeinträchtigung der Betriebssicherheit des Bauelements führen kann.Such a semiconductor component is known from DE 28 09 233 A1 (there in particular FIG. 3). In the known semiconductor component, the glass layer consists of a phosphorus silicate. The glass layer has considerable steps in the area of the contact holes. These steps have a disadvantageous effect on the layers above, in particular on an insulating layer located above the glass layer and the wiring layer located on this insulating layer, since the contours of the steps are transferred to these layers, which can impair the operational reliability of the component .

Dieses Problem ist in der US-PS 38 87 733 angesprochen. Dort ist ein Bauelement beschrieben, bei dem sich auf der Oberfläche eines Substrats über einer darauf befindlichen dielektrischen Schicht eine polykristalline Siliciumschicht befindet, an deren seitlichen Enden Stufen vorhanden sind. Diese Stufen sowie unerwünschte Unregelmäßigkeiten prägen sich auf die darüberliegenden Schichten durch. Um hier Ab­ hilfe zu schaffen, erfolgt eine Wärmebehandlung zur Glättung der über der polykristallinen Siliciumschicht befindlichen Isolierschicht. Die Wärmebehandlung erfolgt bei einer Tempe­ ratur von mehr als 1000°C. Während des Verfahrensablaufs entsteht eine Glasschicht aus Phosphorsilikat. This problem is addressed in US Pat. No. 3,887,733. There is a component described in which on the Surface of a substrate over an existing one dielectric layer is a polycrystalline silicon layer there are steps at the lateral ends. These levels and undesirable irregularities characterize through the layers above. To here from To help create a heat treatment for smoothing that overlying the polycrystalline silicon layer Insulating layer. The heat treatment takes place at a temperature temperature of more than 1000 ° C. During the process a glass layer of phosphorus silicate is created.  

Aufgrund der hohen Prozeßtemperatur kann es zu unerwünsch­ ten Diffusionsvorgängen im Inneren des Bauelements kommen. Es können weiterhin Verunreinigungen aus der Phosphor­ silikatschicht in das Innere des Halbleiterbauelements eindiffundieren.Due to the high process temperature, it can be undesirable diffusion processes occur inside the component. It can continue to contaminate the phosphorus silicate layer in the interior of the semiconductor device diffuse in.

In der US-PS 37 52 701 ist ein Halbleiterbauelement mit ei­ ner Glasbeschichtung beschrieben, wobei im Hinblick auf die genannten Probleme die Glasbeschichtung eine solche Zusam­ mensetzung aufweisen soll, daß sie sich zum Beschichten von Halbleiterbauelementen eignet, aber nicht zu den genannten Nachteilen führt. Vorgeschlagen wird ein Borsilikatglas mit einem wesentlichen Anteil von Zink. Dieses Glas hat einen relativ niedrigen Schmelzpunkt, so daß es für die ge­ nannten Zwecke geeignet erscheint. Über 90% des Glases be­ stehen aus ZnO, B2O3 und SiO2. Mögliche Zusätze sind PbO und Al2O3. Ein wesentliches Problem bei den hier in Rede stehenden Halbleiterbauelementen ist die relativ geringe Wasserbeständigkeit. Zurückzuführen ist dieser Mangel auf die Tatsache, daß die Phosphorsilikatschicht eine starke Neigung hat, Wasser zu absorbieren. Das Borsilikatglas nach der US-PS 37 52 701 besitzt je nach spezieller Ausfüh­ rungsform 50 bis 60 Gewichtsprozent ZnO, etwa 25% B2O2 und zwischen 6 und 13% SiO2.In US-PS 37 52 701 a semiconductor device with egg ner glass coating is described, with regard to the problems mentioned the glass coating should have such a composition that it is suitable for coating semiconductor devices, but does not lead to the disadvantages mentioned. A borosilicate glass with a substantial proportion of zinc is proposed. This glass has a relatively low melting point, so that it appears suitable for the named purposes. Over 90% of the glass consists of ZnO, B 2 O 3 and SiO 2 . Possible additives are PbO and Al 2 O 3 . A major problem with the semiconductor components in question here is the relatively low water resistance. This defect is due to the fact that the phosphorus silicate layer has a strong tendency to absorb water. The borosilicate glass according to US Pat. No. 3,752,701 has, depending on the specific embodiment, 50 to 60 percent by weight ZnO, approximately 25% B 2 O 2 and between 6 and 13% SiO 2 .

Es ist Aufgabe der Erfindung, ein Halbleiterbauelement der eingangs genannten Art anzugeben, bei dem die Glasschicht eine relativ niedrige Erweichungstemperatur aufweist und dabei die Glasschicht eine im Vergleich zum Stand der Tech­ nik verbesserte Wasserbeständigkeit besitzt. It is an object of the invention to provide a semiconductor device Specify the type mentioned, in which the glass layer has a relatively low softening temperature and the glass layer is one compared to the state of the art nik has improved water resistance.  

Diese Aufgabe wird durch die im Patentanspruch angegebene Erfindung gelöst. Danach sieht die Erfindung spezielle An­ teile an ZnO, B2O3 und SiO2 vor.This object is achieved by the invention specified in the patent claim. The invention then provides for special parts of ZnO, B 2 O 3 and SiO 2 .

Durch die erfindungsgemäße Maßnahme wird erreicht, daß das Halbleiterbauelement sehr wiederstandsfähig gegenüber Was­ ser ist, eine hohe elektrische Stabilität aufweist und die dielektrische Schicht zwischen der Verdrahtungsschicht we­ gen ihrer Glätte eine Unterbrechung der Verdrahtung verhin­ dert.The measure according to the invention ensures that Semiconductor device very resistant to what is high electrical stability and the dielectric layer between the wiring layer we prevent the wiring from being interrupted due to its smoothness different.

Im Folgenden wird ein Ausführungsbeispiel der Erfindung an­ hand der Zeichnung näher erläutert. Es zeigenAn exemplary embodiment of the invention is described below hand of the drawing explained in more detail. Show it

Fig. 1a bis 1f schematische Querschnittsansichten der auf­ einanderfolgenden Schritte bei der Herstellung des Halbleiterbauelements gemäß der Erfindung. FIG. 1a to 1f are schematic cross sectional views of the successive steps in the manufacture of the semiconductor device according to the invention.

Die Hauptoberfläche eines p-leitenden Siliciumsubstrats 1 wird thermisch auf eine übliche Weise oxidiert, um darauf einen Siliciumoxidfilm als Feldoxidschicht 2 mit einer Dicke von etwa 1 µm zu erzeugen. Der Silicium­ oxidfilm wird durch Ätzen teilweise entfernt, um gemäß Darstellung in Fig. 1a ein Fenster zu öffnen.The main surface of a p-type silicon substrate 1 is thermally oxidized in a conventional manner to produce a silicon oxide film thereon as a field oxide layer 2 with a thickness of about 1 μm. The silicon oxide film is partially removed by etching in order to open a window as shown in FIG. 1a.

Das Substrat wird dann bei einer hohen Temperatur und in oxidierender Atmosphäre erhitzt, um in dem Fenster einen Siliciumoxidfilm 3 mit einer Dicke von etwa 0,1 µm zu erzeugen, der später als Gateisolierfilm dienen soll.The substrate is then heated at a high temperature and in an oxidizing atmosphere in order to produce a silicon oxide film 3 with a thickness of approximately 0.1 μm in the window, which will later serve as a gate insulating film.

Eine polykristalline Siliciumschicht mit einer Dicke von etwa 0,3 µm wird dann mittels CVD auf die Substratober­ fläche aufgebracht. Mittels einer üblichen Photoätz­ methode wird dann gemäß Fig. 1c dieser polykristalline Siliciumfilm zur Ausbildung einer Gateelektrode 4 und eines Gateoxidfilms 3′ geformt. Ein die Leitfähigkeit bestimmender Fremstoff wie Phosphor (P) oder Arsen (As) wird der Substratoberfläche mittels Ionenimplantation zugesetzt, wie durch 5 in Fig. 1c gezeigt. Dabei werden Zonen mit einer Tiefe von 0,3 µm zur Bildung von Source 6 und Drain 7 erzeugt. Die polykristalline Silicium­ elektrode und die dicke Feldoxidschicht 2 dienen als eine Art Maske. Ionen werden auch in das polykristalline Siliciumgate implantiert. Wenn die Anordnung bei 900°C in einer Stickstoffatmosphäre für etwa 10 Minuten erhitzt wird, werden das polykristalline Siliciumgate sowie die Source- und Drainzonen aktiviert und eine leitende Gate­ elektrode gebildet.A polycrystalline silicon layer with a thickness of approximately 0.3 μm is then applied to the substrate surface by means of CVD. 1c, this polycrystalline silicon film is then formed to form a gate electrode 4 and a gate oxide film 3 ' according to FIG. 1c. A foreign substance that determines the conductivity, such as phosphorus (P) or arsenic (As), is added to the substrate surface by means of ion implantation, as shown by 5 in FIG. 1c. Zones with a depth of 0.3 μm are created to form source 6 and drain 7 . The polycrystalline silicon electrode and the thick field oxide layer 2 serve as a kind of mask. Ions are also implanted in the polycrystalline silicon gate. If the device is heated at 900 ° C in a nitrogen atmosphere for about 10 minutes, the polycrystalline silicon gate and the source and drain zones are activated and a conductive gate electrode is formed.

Auf der Substratoberfläche wird dann gemäß Darstellung in Fig. 1d mittels CVD eine Schicht 8 aus ZnO-SiO2-B2O3- Glas mit einer Dicke von etwa 0,5 µm hergestellt. Zum Zwecke dieser Herstellung mittels CVD wird ein Mischgas gegen das auf etwa 400°C erhitzte Substrat geblasen. Das Mischgas setzt sich zusammen aus Sauerstoff und einem Gas, das durch Vergasung von flüssigen Materialien in einem Verdampfer wie Zn(C2H5)2, Si(OC2H5)4 und B(OC2H5)3 beim Einblasen von Stickstiff in den Verdampfer ergibt. Die Zusammensetzung des Mischgases wird so ge­ steuert, daß das Glas etwa 10% ZnO, etwa 30% B2O3 und etwa 60% SiO2 enthält.A layer 8 of ZnO-SiO 2 -B 2 O 3 glass with a thickness of approximately 0.5 μm is then produced on the substrate surface as shown in FIG. 1d by means of CVD. For the purpose of this production by means of CVD, a mixed gas is blown against the substrate heated to approximately 400 ° C. The mixed gas is composed of oxygen and a gas that is produced by gasifying liquid materials in an evaporator such as Zn (C 2 H 5 ) 2 , Si (OC 2 H 5 ) 4 and B (OC 2 H 5 ) 3 when blowing in Stick stiff in the evaporator results. The composition of the mixed gas is controlled so that the glass contains about 10% ZnO, about 30% B 2 O 3 and about 60% SiO 2 .

Es werden dann in den Bereichen, die die Source, die Drain und das Gate bilden, auf herkömmliche Photoätz­ weise Kontaktlöcher erzeugt und das Substrat auf eine Temperatur von etwa 600 bis 700°C erhitzt. Das ZnO-SiO2- B2O3-Glas wird erweicht und gemäß Darstellung in Fig. 1e die sehr unebene Substratoberfläche geglättet. Gleich­ zeitig wird die Dichte des Glases erhöht.Contact holes are then produced in the regions which form the source, the drain and the gate using conventional photo etching and the substrate is heated to a temperature of about 600 to 700 ° C. The ZnO-SiO 2 - B 2 O 3 glass is softened and, as shown in FIG. 1e, the very uneven substrate surface is smoothed. At the same time, the density of the glass is increased.

Dann wird durch Verdampfen auf der Substratoberfläche ein Aluminiumfilm mit einer Dicke von etwa 1 µm aufge­ bracht und mittels Photoätzens gemäß Fig. 1f eine Source­ elektrode 9, eine Gateelektrode 10 und eine Drainelektro­ de 11 ausgebildet, woraufhin das Halbleiterelement fertig ist.Then, an aluminum film with a thickness of about 1 μm is applied by evaporation to the substrate surface and a source electrode 9 , a gate electrode 10 and a drain electrode 11 are formed by means of photoetching according to FIG. 1f, whereupon the semiconductor element is finished.

Obwohl im vorangehenden Beispiel ZnO-SiO2-B2O3-Glas auf dem SiO2-Film und der Gateelektrode aufgebracht wurde, ist es alternativ möglich, einen Mehrschichtaufbau, der sich aus Phosphorglas und ZnO-Glas zusammensetzt, aufzubringen. Dabei ist es weiter möglich, PbO-Glas, etwa PbO-B2O3- SiO2 auf ZnO-SiO2-B2O3-Glas auszubilden.Although ZnO-SiO 2 -B 2 O 3 glass was applied to the SiO 2 film and the gate electrode in the previous example, it is alternatively possible to apply a multilayer structure which is composed of phosphor glass and ZnO glass. It is also possible to form PbO glass, for example PbO-B 2 O 3 - SiO 2 on ZnO-SiO 2 -B 2 O 3 glass.

Claims (2)

Halbleiterbauelement, umfassend
  • - eine Feldoxidschicht (2) aus Siliciumoxid mit einem darin geöffneten Fenster auf einem Siliciumsubstrat (1),
  • - eine Gateelektrode (4) aus polykristallinem Silici­ um, die auf einem in dem Fenster gebildeten Gateisolierfilm (3) auf dem Substrat (1) ausgebildet ist,
  • - eine Source- und eine Drainzone (6, 7), die in dem Siliciumsubstrat (1) zwischen der Feldoxidschicht (2) und der Gateelektrode (4) gebildet sind,
  • - eine Glasschicht (8), die auf der Feldoxidschicht (2), auf der Source- und der Drainzone (6, 7) und auf der Gateelektrode (4) angeordnet ist, und welche Kontaktlöcher in mindestens einem Teil der den Source- und Drainzonen (6, 7) entsprechenden Bereichen aufweist, und
  • - eine Verdrahtungsschicht (9, 10, 11) auf der Glas­ schicht (8) zur Kontaktierung der Source- und der Drainzone (6, 7),
Semiconductor component, comprising
  • a field oxide layer ( 2 ) made of silicon oxide with a window opened therein on a silicon substrate ( 1 ),
  • a gate electrode ( 4 ) made of polycrystalline silicon, which is formed on a gate insulating film ( 3 ) formed in the window on the substrate ( 1 ),
  • a source and a drain zone ( 6, 7 ) which are formed in the silicon substrate ( 1 ) between the field oxide layer ( 2 ) and the gate electrode ( 4 ),
  • - A glass layer ( 8 ), which is arranged on the field oxide layer ( 2 ), on the source and drain zones ( 6, 7 ) and on the gate electrode ( 4 ), and which contact holes in at least part of the source and drain zones ( 6, 7 ) has corresponding areas, and
  • - A wiring layer ( 9, 10, 11 ) on the glass layer ( 8 ) for contacting the source and drain zones ( 6, 7 ),
dadurch gekennzeichnet, daß die Glas­ schicht (8) aus ZnO, SiO2 und B2O3 besteht und etwa 10% ZnO, etwa 30% B2O3 und etwa 60% SiO2 enthält. characterized in that the glass layer ( 8 ) consists of ZnO, SiO 2 and B 2 O 3 and contains about 10% ZnO, about 30% B 2 O 3 and about 60% SiO 2 .
DE19813132645 1980-08-21 1981-08-18 SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING MULTILAYER WIRING IN SUCH A Granted DE3132645A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11502780A JPS5739554A (en) 1980-08-21 1980-08-21 Multilayer wiring method
JP55115026A JPS5739539A (en) 1980-08-21 1980-08-21 Semiconductor device

Publications (2)

Publication Number Publication Date
DE3132645A1 DE3132645A1 (en) 1982-06-09
DE3132645C2 true DE3132645C2 (en) 1991-01-10

Family

ID=26453643

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813132645 Granted DE3132645A1 (en) 1980-08-21 1981-08-18 SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING MULTILAYER WIRING IN SUCH A

Country Status (4)

Country Link
DE (1) DE3132645A1 (en)
FR (1) FR2489042B1 (en)
GB (1) GB2082838B (en)
NL (1) NL188775C (en)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL109459C (en) * 1960-01-26
US3511703A (en) * 1963-09-20 1970-05-12 Motorola Inc Method for depositing mixed oxide films containing aluminum oxide
GB1114556A (en) * 1965-11-26 1968-05-22 Corning Glass Works Ceramic article and method of making it
US3475210A (en) * 1966-05-06 1969-10-28 Fairchild Camera Instr Co Laminated passivating structure
FR2024124A1 (en) * 1968-11-25 1970-08-28 Ibm
US3752701A (en) * 1970-07-27 1973-08-14 Gen Instrument Corp Glass for coating semiconductors, and semiconductor coated therewith
US3887733A (en) * 1974-04-24 1975-06-03 Motorola Inc Doped oxide reflow process
JPS51144183A (en) * 1975-06-06 1976-12-10 Hitachi Ltd Semiconductor element containing surface protection film
DE2606029C3 (en) * 1976-02-14 1980-03-06 Jenaer Glaswerk Schott & Gen., 6500 Mainz Composite passivation glass based on PbO - B2 O3 - (SiO2 - Al2 O3) with a thermal expansion coefficient (20-300 degrees C) of up to 75 times 10 7 / degrees C for silicon semiconductor components with
DE2611059A1 (en) * 1976-03-16 1977-09-29 Siemens Ag ENCLOSURE SEMI-CONDUCTOR COMPONENT WITH DOUBLE HEAT SINK
JPS583380B2 (en) * 1977-03-04 1983-01-21 株式会社日立製作所 Semiconductor device and its manufacturing method
JPS5425178A (en) * 1977-07-27 1979-02-24 Fujitsu Ltd Manufacture for semiconductor device

Also Published As

Publication number Publication date
FR2489042B1 (en) 1986-09-26
NL188775C (en) 1992-09-16
FR2489042A1 (en) 1982-02-26
NL188775B (en) 1992-04-16
GB2082838B (en) 1984-07-11
DE3132645A1 (en) 1982-06-09
NL8103007A (en) 1982-03-16
GB2082838A (en) 1982-03-10

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