DE3113334C2 - - Google Patents
Info
- Publication number
- DE3113334C2 DE3113334C2 DE19813113334 DE3113334A DE3113334C2 DE 3113334 C2 DE3113334 C2 DE 3113334C2 DE 19813113334 DE19813113334 DE 19813113334 DE 3113334 A DE3113334 A DE 3113334A DE 3113334 C2 DE3113334 C2 DE 3113334C2
- Authority
- DE
- Germany
- Prior art keywords
- etched
- resin
- layer
- printed circuit
- circuit boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000002313 adhesive film Substances 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims description 3
- 238000005096 rolling process Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 239000012876 carrier material Substances 0.000 claims description 2
- 238000007731 hot pressing Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 5
- 238000003475 lamination Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000002311 subsequent effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
Die Erfindung betrifft ein Verfahren zur Herstellung von Mehr lagenleiterplatten durch Heißverpressen mehrerer durch Klebefo lien, sogenannte Prepregs, voneinander isolierter geätzter In nenlagen.The invention relates to a method for producing more layer printed circuit boards by hot pressing several by adhesive film lines, so-called prepregs, etched In isolated from each other locations.
Bei der Herstellung von Mehrlagenleiterplatten können nach Ab schluß des Laminierprozesses Luftblasen im aktiven Rasterfeld verbleiben, die durch den Harzfluß des Prepregs nicht in die Randbereiche des Nutzens transportiert werden konnten. Beim Bohrprozeß können diese Hohlräume angebohrt und beim nachfol genden Durchkontaktierungsprozeß mit einer leitenden Cu- Schicht belegt werden, was zu Isolationsfehlern führen kann.In the production of multilayer printed circuit boards according to Ab End of the lamination process Air bubbles in the active grid remain, which are not due to the resin flow of the prepreg in the Edge areas of the utility could be transported. At the These cavities can be drilled and subsequently via process with a conductive copper Layer can be occupied, which can lead to insulation errors.
Mehrlagenleiterplatten mit Isolationsfehlern sind Ausschuß. Der Isolationsfehleranteil bei Mehrlagenleiterplatten kann 5-10% betragen.Multi-layer circuit boards with insulation faults are rejected. The Insulation fault percentage in multi-layer PCBs can be 5-10% be.
Aus der Zeitschrift "Industrie Elektrik + Elektronik", Jahr gang 1970, Nr. 22, Seiten 562 bis 566, ist ein Verfahren nach dem Oberbegriff bekannt.From the magazine "Industrie Elektrik + Elektronik", year gang 1970, No. 22, pages 562 to 566, is a process according to known to the generic term.
Aus der DE-OS 19 42 843 ist außerdem ein Verfahren und eine
Vorrichtung zur Herstellung einer vielschichtigen gedruckten
Schaltungsplatteneinheit bekannt, wobei die Laminierung unter
gleichzeitiger Anwendung von Druck und Vakuum bei Mehrschicht
leiterplatten erfolgt. Trotz der Anwendung des Vakuums sind
aber Restluftblaseneinschlüsse nicht gänzlich vermeidbar.
From DE-OS 19 42 843 a method and an apparatus for producing a multi-layer printed circuit board unit is also known, the lamination taking place under simultaneous use of pressure and vacuum in multi-layer circuit boards. Despite the application of the vacuum, the inclusion of residual air bubbles cannot be avoided entirely.
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung von Mehrlagenleiterplatten anzugeben, bei dem der Anteil der durch Isolationsfehler hervorgerufenen Unbrauchbar keit der Leiterplatten verringert wird. The object of the present invention is to provide a method for Manufacture of multilayer printed circuit boards to specify, in which the Share of uselessness caused by insulation faults circuit board is reduced.
Zur Lösung dieser Aufgabe wird gemäß der Erfindung der art verfahren, daß die geätzten Innenlagen vor dem Ver pressen mit einer niederviskosen Lösung des gleichen oder eines verträglichen Harzes, aus dem das Trägermaterial der Innenlage besteht, durch Tauchen, Sprühen, Gießen, Rollen oder der gleichen, beschichtet und somit die freigeätzten Bereiche zwischen dem Kupferleiterbild mit Harz gefüllt werden. To solve this problem, according to the invention Art process that the etched inner layers before Ver press with a low-viscosity solution of the same or a compatible resin from which the carrier material of the Inner layer exists, by dipping, spraying, pouring, rolling or the same, coated and thus the etched free Areas between the copper pattern are filled with resin.
Durch diese Maßnahmen wird die Folgewirkung bei Luft einschlüssen nach dem Bohren zwischen der Kupferleiter schicht und der Klebefolie (Prepregschicht) durch die isolierend wirkende Lackschicht erheblich gemindert.These measures will have a consequential effect on air after drilling between the copper conductors layer and the adhesive film (prepreg layer) through the insulating varnish layer significantly reduced.
Anhand der Figur wird die Erfindung näher erläutert.The invention is explained in more detail with reference to the figure.
Die Figur zeigt einen stark vergrößerten Ausschnitt aus einer Leiterplatte. Neben dem am Metall bestehenden Potentialgitter 1, das sich auf der Grundplatte 2 be findet, sind Bohrungen 3 und Freiätzungen 5 erkennbar. Zwischen den Bohrungen und dem Potentialgitter befinden sich Blasen 4. Diese Hohlräume werden nach der Durch kontaktierung der Bohrung mit leitendem Material aus gefüllt, wodurch Kontaktbrücken zwischen den Bohrungs wänden und dem Potentialgitter entstehen können. Auch wenn keine direkten Brücken entstehen, so wird der Isola tionsgrad zwischen Bohrung und Potentialgitter durch die Verkürzung des Abstandes erheblich verringert. Der Luftblaseneinfluß läßt sich in der Praxis kaum vermei den, da das Laminieren von einzelnen Kernen zu einem Laminat ohne Lufteinschlüsse praktisch nicht realisierbar ist.The figure shows a greatly enlarged section of a printed circuit board. In addition to the existing on the metal potential grid 1 , which is on the base plate 2 be, holes 3 and 5 free etchings are visible. There are bubbles 4 between the holes and the potential grid. These cavities are filled with conductive material after contacting the bore, which can result in contact bridges between the bore walls and the potential grid. Even if there are no direct bridges, the degree of insulation between the hole and the potential grid is considerably reduced by shortening the distance. The influence of air bubbles can hardly be avoided in practice, since the lamination of individual cores to form a laminate without air pockets is practically impossible.
Zur Verringerung des schädlichen Einflusses derartiger Hohlräume werden die geätzten Kerne nach dem Prüfen je nach Halbzeugart, z. B. Epoxid oder Polymid, mit einer niederviskosen Lösung dieser Harze beschichtet. Die Be schichtung kann mittels Tauchen, Sprühen, Gießen, Rollen usw. erfolgen. Das niederviskose Harz fließt auch in enge Freiätzungsgräben und vergräbt dabei Luft. Das Relief des geätzten Kupferleiterbildes ist mit Harz gefüllt. Die beschichteten Kerne werden dann wie bisher mit Klebe folien verpreßt. Bleiben jetzt Lufteinschlüsse im Raster feld stehen, ist die Folgewirkung gemindert, da zwischen Kupferleiterbild und Prepregschicht die aufgetragene Lack schicht isolierend wirkt.To reduce the harmful impact of such After checking, the etched cores will each have cavities by type of semi-finished product, e.g. B. epoxy or polymide, with a low-viscosity solution coated with these resins. The Be Layering can be done by dipping, spraying, pouring, rolling, etc. respectively. The low-viscosity resin also flows into narrow ones Free etching trenches and buries air. The relief of the etched copper conductor pattern is filled with resin. The coated cores are then glued as before foils pressed. Air pockets now remain in the grid stand field, the subsequent effect is reduced, since between Copper conductor pattern and prepreg layer the applied varnish layer has an insulating effect.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19813113334 DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19813113334 DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3113334A1 DE3113334A1 (en) | 1982-10-28 |
DE3113334C2 true DE3113334C2 (en) | 1989-03-23 |
Family
ID=6129163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19813113334 Granted DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE3113334A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2362037A (en) * | 2000-05-03 | 2001-11-07 | Bancha Ongkosit | Printed circuit board manufacture |
DE10126002A1 (en) * | 2000-06-24 | 2002-01-31 | Rotra Leiterplatten Produktion | Multilayered circuit board composite body used in the production of planar transformers and coils comprises two circuit boards joined by a composite foil |
JP3903701B2 (en) * | 2000-08-17 | 2007-04-11 | 松下電器産業株式会社 | Multilayer circuit board and manufacturing method thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3681171A (en) * | 1968-08-23 | 1972-08-01 | Hitachi Ltd | Apparatus for producing a multilayer printed circuit plate assembly |
-
1981
- 1981-04-02 DE DE19813113334 patent/DE3113334A1/en active Granted
Also Published As
Publication number | Publication date |
---|---|
DE3113334A1 (en) | 1982-10-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |