DE3113334A1 - Method for producing multilayer printed-circuit boards - Google Patents
Method for producing multilayer printed-circuit boardsInfo
- Publication number
- DE3113334A1 DE3113334A1 DE19813113334 DE3113334A DE3113334A1 DE 3113334 A1 DE3113334 A1 DE 3113334A1 DE 19813113334 DE19813113334 DE 19813113334 DE 3113334 A DE3113334 A DE 3113334A DE 3113334 A1 DE3113334 A1 DE 3113334A1
- Authority
- DE
- Germany
- Prior art keywords
- circuit boards
- multilayer printed
- inner layers
- insulation
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000007598 dipping method Methods 0.000 claims description 2
- 239000011888 foil Substances 0.000 claims description 2
- 238000007731 hot pressing Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000005096 rolling process Methods 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 8
- 239000002313 adhesive film Substances 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- 230000006835 compression Effects 0.000 abstract 3
- 238000007906 compression Methods 0.000 abstract 3
- 238000010348 incorporation Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005553 drilling Methods 0.000 description 2
- 239000004922 lacquer Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Verfahren zur Herstellung von Nehrlagenleiterolatten.Process for the production of multilayer ladder boards.
Die Erfindung betrifft ein Verfahren zur Herstellung von Mehrlagenleiterplatten durch Heißverpressung mehrerer durch Klebefolien voneinander isolierter Innenlagen.The invention relates to a method for producing multilayer printed circuit boards by hot pressing several inner layers isolated from one another by adhesive foils.
Bei der Herstellung von Mehrlagenleiterplatten kennen nach Abschluß des Laminierprozesses Luftblasen im aktiven Rasterfeld verbleiben, die durch den Harzfluß des Prepregs nicht in die Randbereiche des Nutzens transportiert werden konnten. Beim Bohrprozess können diese Hohlräume angebohrt und beim nachfolgenden Durchkontakti erungsprozess mit einer leitenden Cu-Schicht belegt werden, was zu Isolationsfehlern fUhren kann.Know after graduation in the manufacture of multilayer printed circuit boards of the lamination process air bubbles remain in the active grid, which are caused by the Resin flow of the prepreg cannot be transported into the edge areas of the panel could. These cavities can be drilled during the drilling process and during the subsequent Through-hole plating process can be covered with a conductive Cu layer, which leads to Can lead to insulation faults.
Mehrlagenleiterplatten mit Isolationsfehlern sind Ausschuss. Der Isolationsfehleranteil bei Mehrlagenleiterplatten kann 5-10 % betragen.Multi-layer circuit boards with insulation defects are rejected. The insulation fault fraction in the case of multi-layer circuit boards, it can be 5-10%.
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung von Mehrlagenleiterplatten anzugeben, bei dem der Anteil der durch Isolationsfehler hervorgerufenen Unbrauchbarkeit der Leiterplatten verringert wird.The object of the present invention is to provide a method for production of multilayer printed circuit boards, for which the proportion of insulation faults caused uselessness of the circuit boards is reduced.
Zur Lösung dieser Aufgabe wird gemäß der Erfindung derart verfahren, daß die geätzten Innenlagen vor dem Verpressen mit einer niederviskosen Lösung des gleichen oder eines verträglichen Harzes, aus dem die Trägerplatte besteht, durch Tauche Sprühen, Gießen, Rollen oder dergleichen, beschichtet werden.To solve this problem, the method according to the invention is as follows: that the etched inner layers with a low-viscosity solution of the prior to pressing the same or a compatible resin from which the carrier plate is made by Dip spray, pour, roll or the like to be coated.
Durch diese Maßnahmen wird die Folgewirkung bei Lufteinschlüssen nach dem Bohren zwischen der Kupferleiterschicht und der Klebefolie (Prepregschicht) durch die isolierend wirkende Lackschicht erheblich gemindert.With these measures, the consequences of air inclusions are reduced drilling between the copper conductor layer and the adhesive film (prepreg layer) considerably reduced by the insulating lacquer layer.
Anhand der Figur wird die Erfindung näher erläutert.The invention is explained in more detail with the aid of the figure.
Die Figur zeigt einen stark vergrößerten Ausschnitt aus einer Leiterplatte. Neben dem am Metall bestehenden Potentialgitter 1, das sich auf der Grundplatte 2 befindet, sind Bohrungen 3 und Freiätzungen 5 erkennbar.The figure shows a greatly enlarged section from a circuit board. In addition to the potential grid 1 on the metal, which is located on the base plate 2 is located, holes 3 and 5 etchings can be seen.
Zwischen den Bohrungen und dem Potentialgitter befinden sich Blasen 4. Diese Hohlräume werden nach der Durchkontaktierung der Bohrung mit leitendem Material ausgefüllt, wodurch KontakthrUcken zwischen den Bohrungswänden und der Potentialgitter entstehen können. Auch wenn keine direkten'Brücken entstehen, so wird der Isolationsgrad zwischen Bohrung und Potentialgitter durch die Verkürzung des Abstandes erheblich verringert. Der Luftblaseneinfluss läßt sich in der Praxis kaum vermeiden, das das minieren von einzelnen Kernen zu einem Laminat ohne Lufteinschlüsse praktisch nicht realisierbar ist.There are bubbles between the holes and the potential grid 4. These cavities become conductive after the hole has been plated through Material filled, creating contact backs between the bore walls and the Potential grid can arise. Even if there are no direct bridges, so the degree of isolation between the hole and the potential grid is due to the shortening the distance is reduced significantly. The influence of air bubbles can be reduced in practice You can hardly avoid the mining of individual cores to form a laminate without air inclusions is practically not feasible.
Zur Verringerung des schädlichen Einflusses derartiger Hohlräume werden die geätzten Kerne nach dem Prüfen Je nach Halbzeugart, z. B. Epoxid oder Polymid, mit einer niederviskosen Lösung dieser Harze beschichtet. Die Beschichtung kann mittels Tauchen, SprUhen, Gießen, Rollen usw.To reduce the harmful influence of such cavities the etched cores after testing. B. epoxy or polymide, coated with a low viscosity solution of these resins. The coating can by means of dipping, spraying, pouring, rolling, etc.
erfolgen. Das niederviskose Harz fließt auch in enge Freiätzungsgräben und verdrängt dabei Luft. Das Relief des geätzten Kupferleiterbildes ist-mit Harz gefüllt. Die beschichteten Kerne werden dann wie bisher mit Klebefolien verpreßt. Bleiben Jetzt Lufteinschlüsse im Rasterfeld stehen, ist die Folgewirkung gemindert, da zwischen Kupferleiterbild und Prepregschicht die aufgetragene Lackschicht isolierend wirkt.take place. The low-viscosity resin also flows into narrow relief trenches and displaces air in the process. The relief of the etched copper pattern is-with resin filled. The coated cores are then pressed with adhesive films as before. If air inclusions now remain in the grid, the consequential effect is reduced, because the applied lacquer layer is insulating between the copper conductor pattern and the prepreg layer works.
1 Figur 1 Patentanspruch Leerseite1 Figure 1 claim Blank page
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19813113334 DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19813113334 DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3113334A1 true DE3113334A1 (en) | 1982-10-28 |
| DE3113334C2 DE3113334C2 (en) | 1989-03-23 |
Family
ID=6129163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19813113334 Granted DE3113334A1 (en) | 1981-04-02 | 1981-04-02 | Method for producing multilayer printed-circuit boards |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE3113334A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001084896A1 (en) * | 2000-05-03 | 2001-11-08 | Timms, Kevin, Frederick, Kuang | Printed circuit boards |
| EP1168901A2 (en) * | 2000-06-24 | 2002-01-02 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
| EP1180921A2 (en) * | 2000-08-17 | 2002-02-20 | Matsushita Electric Industrial Co., Ltd. | Multi-layer circuit board and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1942843A1 (en) * | 1968-08-23 | 1970-10-15 | Hitachi Ltd | Method and apparatus for making a multilayer printed circuit board assembly |
-
1981
- 1981-04-02 DE DE19813113334 patent/DE3113334A1/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1942843A1 (en) * | 1968-08-23 | 1970-10-15 | Hitachi Ltd | Method and apparatus for making a multilayer printed circuit board assembly |
Non-Patent Citations (1)
| Title |
|---|
| Franz, A., Multilayer-Technik der Mehrlagen- bindung, Industrie-Elektrik + Elektronik, 15. Jg., 1970, Nr. 22, S. 562-566 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001084896A1 (en) * | 2000-05-03 | 2001-11-08 | Timms, Kevin, Frederick, Kuang | Printed circuit boards |
| EP1168901A2 (en) * | 2000-06-24 | 2002-01-02 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
| EP1168901A3 (en) * | 2000-06-24 | 2003-03-26 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
| EP1180921A2 (en) * | 2000-08-17 | 2002-02-20 | Matsushita Electric Industrial Co., Ltd. | Multi-layer circuit board and method of manufacturing the same |
| EP1180921A3 (en) * | 2000-08-17 | 2005-12-07 | Matsushita Electric Industrial Co., Ltd. | Multi-layer circuit board and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3113334C2 (en) | 1989-03-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |