DE3021485A1 - Carrier frequency supervision for communications system - in which time delayed zero cross-over points are assessed by logic system - Google Patents

Abstract

The checking system is applied to a communications channel using a frequency modulated carrier oscillation. The system operates on the carrier zero crossing points. These are used to generate a series of impulses, which are differentially time delayed in an impulse delay unit (1). Some of the outputs of this unit are applied to a pulse converter (2), and all are applied to a logic circuit (3). The pulse converter feeds the circuit with a number count which may be in the form of a logic high or low. The logic output is applied to a counter (4) whose output condition changes from one state to another depending upon the logic input. The change in state, for example from a high to a low, indicates loss of carrier wave. The supervision does not add greatly to the components required for the data transmission system.

Description

Method and circuit arrangement for carrier frequency

Monitoring in a Communication System The invention relates to a method and a circuit arrangement for carrier frequency monitoring in one ' Message transmission system in which the characteristic states of a digital signal a phase-jump-free, frequency-modulated carrier oscillation is assigned and in which this band-limited, frequency-modulated carrier signal over a transmission link is fed to a demodulator, which depends on the frequency of the carrier oscillation Outputs DC voltage signals as demodulated signals.

For demodulating an FSK signal (frequency shift keying signal) there has been proposed a demodulator using an incremental method will. The demodulator decides on the basis of the zero crossings of the received FSK signal, whether the signal frequency is above or below the center frequency.

For the use case screen text, for example, the identification states a binary digital signal is assigned the characteristic frequencies 1300 or 2100 Hz, see above that the center frequency is 1700 Hz. Used for the transmission rate, for example 1200 bit / s is selected, this is relatively high compared to the characteristic frequencies, so that an averaging over several zero crossings is necessary in order to avoid a small To achieve distortion and immunity to interference in the noise. In the case of the proposed incremental process, the pulse series at the output of the digital differentiator fed to a delay section. The delayed and the undelayed pulse series, whose logical 1 values represent the zero-crossing distances are in each case fed to a converter. The distance value, a multi-bit signal representing a numerical value at the output of the converter is a measure of the distance between the instantaneous received signal frequency to the center frequency of the characteristic frequencies.

The distance values at the output of the converter each represent the time between the associated zero crossings of the received FSK signal. In the present The case is in the converter for a signal frequency above a certain maximum assigned the smallest binary word and for characteristic frequencies below a certain At least the corresponding word. This area corresponds to the resolution of the Converter divided. The center frequency is e.g. due to the transition of the most significant Bits of the distance value, for example, logical 1 value after logical 0 value. The delay time in the delay section is a multiple of the period duration of the internal clock. In a subtracter connected to the converter, the Difference between the delayed and undelayed distance values is formed. That The output signal of the subtracter is fed to a second accumulator in which during each clock period of the internal clock the mean value after the incremental Procedure is recalculated. This process is understood to mean that the correct sum value in the second accumulator results when the difference from the the signal newly read into the delay section and the delay section leaving signal to the content of the second accumulator from the previous clock period is added. This allows for an absolute addition of all in the delay section signals located in the second accumulator can be dispensed with. In a.following The comparator is the output signal of the accumulator with that of the center frequency corresponding value compared. To avoid that during the operation of the demodulator the correspondence between the content of the delay section and the second accumulator is disturbed, i.e. that the mean value at the output of the second Accumulator by a random and fixed difference from the actual content of the delay section is different, the distance values of the second converter are stored in a first accumulator summed up with each step of the internal clock. After a time interval has elapsed, which corresponds, for example, to the delay time of the delay section, an Correction in such a way that the sum value of the first accumulator in the second accumulator is taken over. The time intervals between the times of the respective takeover can be chosen as long as you like. They contain at least the delay time after its expiry, i.e. at the beginning of a new interval, the transfer takes place For this purpose, a control circuit is provided which essentially contains a counter, which enters after a certain number of periods of the / clock Control signal generated with which the total value is accepted. With the circuitry A multi-stage shift register is implemented for the delay section intended.

The components of the converters are one or more priority encoders, a logic combination circuit and a memory circuit. With a priority encoder is the distance of e.g. Logical ~ 1 characteristic states of the impulse series, which are instantaneously appears at a number of outputs of the shift register, detectable. Of the the zero crossing intervals of the received signal frequencies characterizing digital Value, the so-called distance value, is turned off in the case of several priority encoders their output signals formed with the aid of the logic combination circuit. as The transfer command for the distance value into the memory circuit is, for example, the logic 1 identification state used at the output of a subsequent stage of the slew register. Kick during disturbances during operation, i.e. the demodulated FSK signal is noisy, for example or a random signal, it is a reporting signal for the data terminal necessary.

The object of the invention is therefore, for a demodulator, the initially described type a method and a circuit arrangement for carrier frequency monitoring to be provided, which in addition to the circuit complexity for realizing the demodulator requires little additional circuitry and in which essentially the existing components of the demodulator can also be used.

This object is achieved according to the invention in that a the Zero crossings of the carrier wave corresponding pulse series delayed differently appears at the corresponding outputs of a multi-stage delay section and fed to both a converter and a logic combination circuit will that a number of simultaneously at the outputs of the delay section occurring pulses in the converter a numerical value representing digital multi-bit signal is assigned that the transition from one characteristic state to the other of a certain, additional output signal of the converter triggers a counting signal, -which about the logic circuit is fed to a counter that the carry signal of the counter is applied to the logic circuit and that at the transition decided one of the output signals of the counter from one to the other characteristic state whether the carrier vibration is present or not.

By the method according to the invention for carrier frequency monitoring the operating state of the transmission link can be checked in a particularly simple manner monitor and thus clearly determine the cause of the malfunction in the event of a malfunction. When linking suitably selected signals, which are executed in Demodulator already exist, the effort for the logic combination circuit to a minimum and a message signal from the monitoring of the carrier frequency to win.

In detail, it is proposed that the number of stages of the delay section the number of stages in a series of shift registers and the associated delay time corresponds to a certain period of time of an internal clock. The output signal of 1 stages of a second shift register becomes the 1 inputs of a priority encoder fed in the converter.

With the output signal of the n-th stage or an (n + o) -th stage of a third shift register become the reset input or the set input of a first bistable multivibrator of the logic circuit is controlled. Corresponding causes an impulse to appear at the output of a before the 1-stage sluggish register arranged stage of a first shift register of the delay section that Setting a second bistable multivibrator of the logic combination circuit. These bistable multivibrator is with the output signal at the first output of the l-stage Shift register reset.

This has the advantage that when using the (n-m) th Stage or the (n + o) -th stage of the first or third shift register the area the distance values are shifted towards the frequencies actually occurring during operation will. This range of frequency spacings to the center frequency can e.g. Center frequency. It is set according to the resolution of the priority encoder used divided. In the present circuit arrangement, they are different delayed output signals, e.g. of the second shift register, are fed to the converter and with the takeover command of a stage of the shift register following the n-th stage will the formed distance value in a memory circuit of the Distance converter and appears at its output. By using an output signal of a stage of the shift register following the n-th stage as a takeover command, the range of the distance values is shifted towards the center frequency.

The first range (i.e. distance values formed from the output signals of the second shift register) is smaller than the area covered by the Selection of any stage before the second shift register and one freely after the second shift register selectable stage arises.

A circuit arrangement for performing the method according to the Invention can be designed such that the output signal of the additional Output of the converter a first input of a first NAND gate dcr logical Logic circuit is supplied. At the second output of the NAND gate, the inverting output of the second bistable multivibrator applied. The output signal this NAND gate is connected to the first input of an AND gate of the logic circuit created. The output signal at the inv'erting is sent to the second input of the AND gate The output of the first bistable multivibrator is supplied. The output of an (n + p) th Stage of the third shift register is connected to the first input of a second NAND gate created. The internal clock is fed to the second input of this NAND gate. The output of the second NAND gate is sent to the second input. of an OR gate created. The inverted carry signal is sent to the first input of the OR gate fed to the highest level of the counter. The clock input of the counter is connected to the Output signal of the OR gate applied.

Depending on the signal at the up / down counter input of the counter the impulses of the output signal of the OR gate is counted and increase or decrease the count.

The circuit arrangement according to the invention are for the logical Logic circuit a small number of the simplest gate circuits required, so that the effort for it can be kept low.

Furthermore, there is an integration of the demodulator a cheap circuit arrangement.

By using the inverted carry signal of the counter exhibits this 'impact behavior'. Normally the counter counts after switching on of the demodulator upwards until the logic 1 characteristic state at the most significant output of the counter appears. This signal indicates that the carrier wave is present is. If the count continues, the counter reaches the stop. The carry signal at the overflow output of the counter then assumes the logic-O characteristic state. Because of this 'Stop behavior' and by the hysteresis of the counter, i.e. the threshold of the characteristic state change at the most significant output, the carrier oscillation when it is exceeded or undershot is recognized as present or not, is at a corresponding distance to Stop, this prevents the carrier frequency monitoring from responding to short glitches appeals to.

The invention is illustrated below with reference to that shown in the drawing preferred embodiment explained in more detail.

1 shows a block diagram for a possible structure of the circuit arrangement for carrier frequency monitoring according to the invention.

2 shows a possible implementation of the logic combination circuit according to the invention.

In FIG. 1, 1 appears at the outputs of a delay section the pulse series is delayed differently.

The (n-m) -th output, the (n-l) -th output, the n-th output, the (n + o) -th Output and the (n + p) -th output are each connected to the corresponding inputs of a logic combination circuit 3 connected. Furthermore, the (n-l) th to n-th outputs of the delay section 1 the respective inputs of a converter 2 supplied. The converter 2 forms the corresponding for a first area Distance values.

An additional output of the converter 2 is connected to an input of the logic combination circuit 3 connected. This output takes, for example, the logic 1 identification status then on if at all inputs of converter 2 no logic 1 state is different delayed pulse series is present. The output signals of the logic combination circuit 3 are fed to a counter 4.

The carry signal of the counter 4 is an input of the logical Logic circuit 3 supplied.

As Fig.2 shows, the delay section 1 is in a series of Shift registers 5, 6, 7 divided.

The output signal at the (n-m) -th output of the first shift register 5 is fed to the set input of a bistable multivibrator 10. The output signal at the (n-l) -th output of the second shift register 6 is both with an input a priority encoder 8 as well as with the reset input of the second bistable Flip-flop 10 connected. The output of the nth stage of the second shift register 6 is both at an input of the priority encoder 8 and at the reset input a first bistable trigger stage 9. The setting input of the bistable multivibrator 9, the output signal at the (n + o) -th output of the third shift register 7 is fed. By using the (n-m) th or (n + o) th stage of the delay section 1 becomes the second area around the Center frequency selected. One first NAND gate 11 becomes the additional output of converter 2, i.

of the priority encoder 8, and the inverting output of the second bistable flip-flop 10 supplied.

The output signal of the first NAND gate 11 is at the input of a AND gate 13. Another input of AND gate 13 is the inverting The output of the first bistable multivibrator 9 is supplied.

The output signal of the AND gate 13 is the control input for the forward or down counting of the counter 4 is supplied. The (n + p) th output of the third shift register 7 is fed to a first input of a second NAND gate 12. Thereby are the first and second areas are clearly defined with regard to their position relative to one another. The internal clock T is present at a further input of the second NAND gate 12. The output of the second NAND gate 12 becomes a second input of a OR gate 14 supplied. The overflow output of the counter 4 is via an inverter connected to the first input of the OR gate 14. The output of the OR gate 14 is applied to the counter 4 as a clock signal. This wiring of the counter 4 it is achieved that the counter is within the range defined by the steps (n-m) or

(n + p) specified area counts up and when the carry signal passes of the counter 4 from one to the other characteristic state at the highest count stop. Then there is a signal with the logic 1 identification state at the clock input of the counter 4 on and the pulses at the output of the second NAND gate 12 are not counted. For frequencies outside this range, the counter counts down until the value Logical-O is reached. By using the most significant output of the counter 4, a simple yes / no decision can be made from a change in the identification status the existing carrier oscillation are hit.

Claims (7)

Method and circuit arrangement for carrier frequency monitoring in a communication system in which the characteristic states of a digital signal a frequency-modulated carrier wave that is free of phase shifts is assigned and at / this band-limited, frequency-modulated carrier signal over a transmission link is fed to a demodulator, which depends on the frequency of the carrier oscillation Emits direct voltage signals as demodulated signals, characterized in that that a pulse series corresponding to the zero crossings of the carrier wave is different delayed at the corresponding outputs of a multi-stage delay section (1) appears and both a converter (2) and a logic combination circuit (3) that a series of is fed simultaneously to the outputs of the delay section (1) occurring pulses in the converter (2) a numerical value representing digital Multi-bit signal is assigned that the transition from one characteristic state to the other a specific, additional output signal of the converter (2) a counting signal triggers, which is fed to a counter (4) via the logic circuit (3) is that the carry signal of the counter (4) to the logic circuit (3) is applied and that when one of the output signals of the counter (4) changes from one in the other characteristic state it is decided whether the carrier oscillation is present is or. not. 2. The method according to claim 1, characterized in that the number the stages of the delay section (1) the number of stages of a series of shift registers (5, 6, 7) and the associated delay time of a certain period of time internal clock corresponds to the output signal of a 1-stage second shift register (6) in each case fed to the 1 inputs of a priority encoder (8) in the converter (2) and that the output signal of the n-th stage at the reset input and the output signal an (n + o) -th stage of a third shift register (7) at the set input of a first bistable flip-flop (9) of the logic circuit (3) is present. 3. The method according to claim 1, characterized in that the appearance of pulses of the pulse series at the output of a before the 1-stage shift register (6) arranged stage (n-m) of a first shift register (5) of the delay section (1) and at the first output (n-l) of the 1-stage shift register (6) the setting or the resetting of a second bistable multivibrator (10) of the logic combination circuit (3) causes. 4. The method according to claim 1, characterized in that the characteristic state change at the most significant output (k) of the counter (4) for monitoring the carrier oscillation is used. 5. Circuit arrangement for performing the method according to a of claims 1 to 6, characterized in that the output signal of the additional Output of the converter (2) a first input of a first NAND gate (11) of the logic combination circuit (3) is supplied and that the second input of the NAND gate (11) of the inverted rende output of the second bistable Tilting stage (10) is applied. 6. Circuit arrangement according to claim 1, 2 and 5, characterized in that that the output signal of the first NAND gate (11) at a first input of a AND gate (13) of the logic circuit (3) is applied and that the second input of the AND gate (13) the output signal of the inverting output the first bistable flip-flop (9) is supplied. 7. Circuit arrangement according to claim 1, 2 and 6, characterized in that that the output signal of an (n + p) -th stage of the third shift register (7) the first input of a second NAND gate (12) of the logic combination circuit (3) that the second input of the second NAND gate (12) is the internal clock (T) is fed that its output signal to the second input of an OR gate (14) the logic combination circuit (3) is connected that the first input of the OR gate (14) fed the inverted carry signal of the counter (4) and that with the output signal of the OR gate (14) the clock input of the counter (4) is applied and depending on the output signal of the AND gate (13) of the counter (4) counts up or down.