DE2812653C3 - Circuit arrangement for matching the amplitude of an alternating signal voltage to a reference voltage - Google Patents

Description

4 <-, The invention relates to a circuit arrangement for matching the amplitude of an, in particular low-frequency, alternating signal voltage to a Reference voltage using a control loop which, when there is a difference between the reference

', o voltage and signal alternating voltage are a control variable for changing the amplitude of the signal alternating voltage.

A circuit of this type is known from DE-AS 22 53 799, which describes an AC voltage regulator,

η in which the peak values of an alternating voltage are recorded in a memory. A sample-and-hold circuit generates stair-step voltages that represent the actual value of this control circuit. Since 'with this circuit arrangement only

μ is based on the peak values, it cannot be used cause particularly fast amplitude control because a new sampling vertebral only with the next one

Maximum is available. In phase locked loops for frequency control depends

h-, the control speed mainly from the frequency ?. at which the phase comparison takes place. If, apart from a certain residual control error, a total of m phase shifts

if the same are necessary, the result is a comparison frequency-dependent settling time te = '! ■ [

From this equation it can be seen that, especially with low comparison frequencies fv, very long waiting times are required until the transient process has ended Mixing in the low frequency position (preferably for sine signals) gained. It is also possible to generate the low frequency signal synthetically by appropriately controlling a digital-to-analog converter.

All of these known methods fail utterly when an analog signal generated in the low frequency range is effectively connected to a crystal oscillator shall be. This case occurs e.g. B. then on when that Signal from a function generator only optional (optional) is to be frequency synchronized.

Another problem is that not only the Frequency, but also the form of an alternating signal voltage to the form of a reference voltage should be adjusted as quickly as possible, for example a triangular signal alternating voltage shows a rise that is too flat compared to the reference voltage or has a drop in the flank area. There is also the problem of finding a corresponding one as quickly as possible To gain correction variable for the change in the edge rise of the signal alternating voltage.

The present invention, which relates to a circuit arrangement of the type mentioned above relates, the task is to show a way on which the deviation of the signal alternating voltage can be recognized by the reference signal within a very short time, so that the manipulated variable is accordingly quickly available. According to the invention, this is achieved in that within the Rising and / or falling edge of the alternating signal voltage at different points in time, voltage levels the reference voltage are generated that by means of at least one comparator by a comparison the voltage levels of the reference voltage with those occurring at the times mentioned Signal alternating voltage values comparison pulses are formed and thus already in the edge range (Edge scanning) of the signal alternating voltage a comparison to the edge range of the reference voltage is carried out and that the control voltage is also already in the edge area from the comparison pulses derived for the amplitude change of the signal alternating voltage used for the adjustment will.

While z. B. in phase locked loop !! the frequency or If the phase deviation of the signal alternating voltage from the frequency standard is usually only recognized by the time offset of the voltage zero crossings, the invention assumes that in the case of monotonic functions (triangle, sawtooth, sine, etc.) the previous voltage curve (ie the rising and / or falling edge) is the carrier the frequency information is. The same applies when it comes to the adaptation of the waveform of the signal alternating voltage to the waveform of the reference voltage. Through the ₍ invention, the desired information is obtained through "edge scanning" and fed to the control loop as a manipulated variable. The control speed is significantly increased and the settling time in the event of disturbances or frequency changes is greatly reduced.

The edge scanner according to the invention is an arrangement in which the signal alternating voltage of a certain waveform and amplitude with a series in height evenly or according to a certain Function (e.g. sine) of arranged reference voltages compared and if the voltage is equal, a pulse is emitted in each case.

in The time intervals between these comparison pulses are dependent on the instantaneous frequency, linearity, etc. of the signal alternating voltage and can be used for Control purposes are used. This can advantageously be achieved in that the comparison pulses se with an equal uniformity derived from an oscillator, in particular a quartz oscillator Pulse series are compared.

The invention is practically suitable for all types of signal alternating voltages; it's just a

jo to the course of the respective signal alternating voltage to generate an adapted reference signal. It is there advantageous if the reference signal has a step-shaped profile because such signal sequences are particularly useful can be produced in a simple manner and

j-, are good for voltage comparisons.

For monotonically increasing and / or decreasing functions as signal alternating voltages (e.g. Triangular or sawtooth voltages) exists according to a particularly advantageous embodiment of

Invention the possibility of generating the reference voltage by means of a control counter which counts upwards on the rising edge and downwards if there is a falling edge (triangular voltage)
Developments of the invention are in the sub-

f, Proverbs reproduced.

The invention and its developments are explained in more detail below with reference to drawings. It shows
FIG. I in a block diagram the structure of an exemplary embodiment of the invention,

2 shows in a time diagram the generation of comparison pulses in the case of a triangular voltage,

3 shows the generation of Comparison pulses for non-linear signals.

r. In the embodiment according to FIG. 1, the preferably low-frequency alternating signal voltage USi generated in a signal generator SG and assumed here as a triangular signal is fed to the control circuit shown below

-, o first to the minus (-inverting) input of a first comparator KO 1 and via a circuit SV to the voltage offset to the plus (-non-inverting) input of a second comparator KO 2. The voltage offset in the circuit SV should be the value

Γι + U \ I tiaben. A control counter STZ is provided to generate the reference voltage UR assumed here in the form of a staircase.

Assume that the amplitude range to be processed is a total of 50 linear steps

, η are divided sill, 51 counting pulses from the taxpayer STZ are required for a rising and a falling edge. The additional stage enables a voltage shift of the reference voltage UR compared to US and thus an exact comparison in

, -, peak value range of the alternating voltage. Using a binary count jrs is z. B. a six-digit (6 bit) Provide counter. Since, however, the count values from count value 52 to count value 64 are no longer in this case

are required, a decoding circuit DCS is connected to the output of the control counter STZ , which no longer allows larger count values than the value 51. Furthermore, the decoding circuit DCS has the effect that the respective count value is reset to zero when the device is switched on. The circuitry peculiarity of the control counter STZ to take an additional step in the "old" direction by changing the counting direction (FIG . 2) means that the two comparators KOX and KO 2 are now offset by two voltage levels instead of one , the counting capacity is increased to N = 52 (n = 0 ... 51) and the decoding in the decoding circuit DCS for "forbidden" areas may only start from 52 onwards. The number of comparison pulses / period T remains unchanged at 100.

The initially digital count values of the control counter STZ (or at the output of a code converter CWS) are fed to a digital analog converter DA W , which the analog stepped reference voltage UR according to FIG. 2 generated. This step-shaped voltage is fed to the pulse input of the comparator KO X and the minus input of the comparator KO1.

If more complicated voltage curves, ie non-linear, z. If, for example, sinusoidal reference voltages with a discontinuous curve are to be generated, an additional circuit must be provided which serves as a code converter CWS . This circuit can, together with DA Win, in a known manner, the amplitude values of the linear staircase curve (z. B. UR in Fig. 2) in the upper and lower part of the rising and falling edge z. B. reduce it so that a non-linear course (z. B. sinusoidal) is created. It is possible either to encrypt the digital control accordingly (example in FIG. 1) or to shift the weighting of the linear digital control to the digital-to-analog converter DAW.

The output signals of the first comparator KO X go to the forward input of the control counter STZ, those of the second comparator KO 2 to the backward input. At the output of an AND gate UU. at which the output signals of the Deiaen comparators are logically combined, a phase comparison circuit PH is provided, the reference voltage of which is supplied by a stabilized, preferably quartz oscillator QO . The present at the output of the phase comparison circuit PH, and the deviation of the AC signal voltage USi of the reference voltage UR representing voltage is smoothed in a Tiefüaß TP and a control voltage UK for readjustment of the signal generator SC and therefore the AC signal voltage USL used for by a control circuit FFP (B.. In the form of a flip-flop), rectangular pulse trains UVR are generated, the rising and falling edges of which mark the beginning of the rising and falling edges of the signal alternating voltage USi and thus allow the counting direction of the control counter STZ to be determined (upward counting on the rising edge of USi, downward counting on the trailing edge). Instead of the control circuit FFP , the beginning of the rising and falling edge of the alternating signal voltage USi can also be determined by a differentiating circuit DS indicated by dashed lines and fed to the control counter STZ.

To further explain the mode of operation of the circuit according to FIG. 1 is shown on FIG. 2 referred to. There the stepped reference voltage UR with two signal AC voltages US l and US2 is shown. The signal alternating voltage US corresponds to the triangular signal coming from the signal generator SG , which is sent to the minus input de; ϊ Comparator KO 1 arrives. It can be seen that on the green of the presetting by the reference voltage UR arr comparator KO X, the alternating signal voltage US X nui has the same voltage values as the reference voltage in the rising edge at certain points

in UR. Accordingly, N comparison pulses arise at the output of the comparator KOX, which are shown in Fig. Ί with the rising edge of the voltage USX and denoted by NV (forward pulses)! are. The in the circuit SV of Fig. 1 to the

H voltage offset + UVX compared to the original alternating signal voltage Us X raised second alternating signal voltage US2 leads in its rising edge to no response of the comparator KO 2 because there is no match between the span

jo ning values of the signal alternating voltage US 2 and the reference voltage UR occurs. On the other hand, in the area of the falling edge, the reference voltage UR is reached once on every stepped line by the signal alternating voltage US2 and thus provides a series of Λ

r, output pulses (comparison pulses) at the comparator KO2, which are shown below the falling edge and designated with NR (reverse pulses). In the area of waste, as already mentioned, there is no longer a pulse train at the output of the comparator KOX, se

in that by the circuit according to F i g. 1 per pulse period 1, a total of 2 N comparison pulses are generated. Since the comparators KO X and KO2 do not match in the event of a mismatch between the reference voltage UR and the respective signal alternating voltage USX or L / S2

ji output logical one as output signal, the output of the AND gate UG emits a continuous series of comparison pulses, which are composed of the stringing together of the forward pulses NV and the reverse pulses NR and which are referred to here as 2 AZ / Ci comparison pulses).

The output of the comparator KO X is, as already mentioned, with the forward input of the taxpayer! ύ / ζ verDunden, while the output of the comparator KO 2 to the reverse input of this counter

ji is led. The occurrence of forward pulses A / V at the output of the comparator KO X causes a forward adjustment of the control counter STZ and thus an adjustment of the reference voltage UR to the next higher value. With this presetting, the comparator KOX "waits" until the triangular voltage, which rises slowly, becomes the same voltage as the Vo "setting. As soon as the triangular voltage, which is still rising, slightly exceeds the presetting, the minus input of KO 1 will be positive The positive input and the comparator output go to logic 0. This negative transition switches the control counter STZ one step further, which means that the comparator KO 1 also switches to the next higher voltage via the digital-to-analog converter

bo is set. Now the plus input is again more positive than the minus input and the comparator output goes to logic 1. This creates a Individual comparison pulse completed and the process is repeated up to the vertex of the

b5 triangular voltage in the KOi, then with the falling edge of the triangular voltage in the comparator KO 2.

In the case of the FIG. The exemplary embodiments shown in FIG. 2 are due to the linear triangular shape

resulting time intervals of the comparison pulses equal to each other. If the time intervals are also the same as those from the quartz oscillator QO (Fig. I), the linearity and the frequency of the triangular voltage agree with the nominal value. Otherwise the signal generator SG will be readjusted.

As can be seen from FIG. 3, the time intervals between the comparison pulses are uneven with a non-linear signal weekly voltage: the steeper the signal, the more compressed the pulses are. If the alternating signal voltage is a triangle, full, the comparison pulses in the phase comparison circuit PH ( FIG. 1) are compared with an equidistant pulse series from QO. From the timing differences of these two pulse trains, the control voltage is formed UK via the low-pass filter TP, by which the signal generator SG is adjusted so that the AC signal voltage US v 1, the target curve up "uf a residual error in both the linearity / ie in the Fre ⁿ ucnz resembles.

If the nominal curve of the signal alternating voltage deviates from the triangle (e.g. sine), this is e.g. B. preprogrammed by different step heights of the reference voltage UR. As a result, the time intervals between the comparison pulses (NV and NR) are again equal to one another and can be fed to the phase comparison circuit PH and thus to the control loop.

In the case of a sawtooth waveform of the alternating signal voltage USX, there is no monotonic drop in the area of the trailing edge of the alternating signal voltage US 1 . For this reason, a second comparator KO 2 , which responds to the trailing edge, is not required and the control counter STZ only has to move in one direction, e.g. B. forward, can count.

With a phase comparison with an N-step reference voltage UR / V times more phase comparisons for frequency symmetry and linearity correction of the triangular voltage (signal alternating voltage USi) are possible within a single rising edge than without such an edge scanner. This increases the control speed and greatly reduced settling times are achieved

In order to increase the accuracy of the steps of the reference voltage UR, which are generated one after the other in synchronism with the triangular voltage, it is expedient to select a digital-to-analog converter DAW with a higher resolution. For example, with a (6-bit) control counter 57Z, the digital-to-analog converter DAW can be designed with 10 bits. The accuracy of a DAW is specified as ± LSB (LSB = least significant bit) and is 2 "= 16 times greater with a 10-bit digital component than with a coarse 6-bit digital-to-analog converter.

From Fig. 2 it can be seen that the reference voltage UR is above the triangle voltage (signal alternating voltage LiSl) on the rising edge and below it on the falling edge, in order to reduce the monotonic change in the Triangular voltage to achieve an approximation and finally equality of the two voltages. Instead of the two parallel signal voltages as shown in FIG. 2, the presetting of the comparators with the reference voltage staircase curve can also be achieved by a voltage jump from USi to US2 and vice versa at the point of inflection. The omission of a second comparator is, however, increased

ίο switching costs bought.

The size of the voltage offset + UVi should correspond to the height of two t / Ä steps (Fig. 2). The stepped curve (reference voltage UR) must also be half a ί / Λ step compared to the peaks values of USi and US 2 may be offset in order to enable reliable comparisons in these regions as well.

In the case of linear functions of the signal alternating voltage US J, such as triangle and sawtooth, the reference voltage levels of UR are N evenly spaced arranged from each other: UR = - US + ^ - η, π = 0 ... / ν "; LAS = peak value of the signal alternating voltage.

In the case of non-linear functions, such as B. Sinus, are the Uneven distances and the reference voltage

Distribution adapted to the functions: z. B. UR = US ■

Sin ψη, ψη '

0 ... N.

The N reference voltage levels of UR for the edge scanner can also be a voltage divider

jo removed and N comparators fed if they are not as in Fig. 1 can be generated one after the other. The comparators would emit N comparison pulses one after the other, which, logically combined, could be fed to the control loop. at

Signal alternating voltages that come about with the help of two or more signal generators SG (e.g. in the case of a triangle, the two edges are generated separately), a separate control loop must be closed for each generator. Generally must

namely, each generator can be individually corrected differently (in the triangle example, the flanks different steepnesses), so that the characteristic values of the composite / VF signal as The whole is right. In practice, however, it is sufficient if instead of two or more self-employed Control loops only parts of one control loop are switched over synchronously with the generators. So z. B. with a symmetrical triangle between the charging and the discharging current generator

so switched and in parallel only the associated integration elements of the low-pass filter TP. In the case of an asymmetrical triangle, on the other hand, the comparison frequency, i.e. the division factor of the frequency divider chain between the quartz oscillator QO and Phase comparison circuit PH, be switched, otherwise the control would aim for a symmetrical triangle.

For this purpose 3 sheets of drawings

Claims (1)

Patent address: 1. Circuit arrangement for matching the amplitude of an, in particular low-frequency, alternating signal voltage to a reference voltage using a control loop which, when there is a difference between the reference voltage and the alternating signal voltage, provides a control variable for the change in the amplitude of the alternating signal voltage, characterized in that within the rise and / or uder the falling edge of the alternating signal voltage (USi) voltage levels of the reference voltage (UR) are generated at different times that by means of at least one comparator (e.g. KO 1) by comparing the voltage levels of the reference voltage (UR) with those occurring at the times mentioned Signal alternating voltage values (from LiSl) comparison pulses (e.g. forward pulses NV, backward pulses NR) are generated and a comparison to the tendril area of the reference voltage (UR) is carried out in the flank area (flank scanning) of the signal alternating voltage (US 1) d that also in the edge area from the comparison pulses (e.g. B. forward pulses NV, backward pulses NR) the control voltage (UK) for the adjustment of the amplitude change of the signal alternating voltage is derived. 2. Circuit arrangement according to claim 1, characterized in that the reference voltage (UR) has a step-shaped profile 3. A circuit arrangement according to claim 2, characterized in that a control counter (STZ) is provided to Erzeajung a step-shaped voltage curve with a depending on the time dreietksfö: -aig running reference voltage (UR) , which at the rising edge of the reference voltage (UR) upwards and counts down on the falling edge 4. Circuit arrangement according to claim 2, characterized in that a control counter (STZ) is provided for generating a step-shaped reference voltage (UR) with sawtooth-shaped signal alternating voltages (US) , which counts up on the rising edge of the reference voltage (UR) and on the falling edge is reset to zero. 5. A circuit arrangement according to claim 1, characterized in that the comparison pulses (z. B. forward pulses NV, reverse pulses NR) are compared with a uniform pulse series derived from an oscillator, in particular a quartz oscillator (QO), in a phase comparison circuit (PH) Output, especially after filtering in a low-pass filter (TP), the control voltage (UK) is removed and fed to an adjustable signal generator (SG) for the signal alternating voltage (US). 6. A circuit arrangement according to claim 1, characterized in that a second alternating signal voltage (US2) is formed from the actual alternating signal voltage (US 1) by a voltage reduction by a certain direct voltage value and that these alternating signal voltages (USi, US 2) each have a comparator (KO 1 , KO 2), the second input of which has the reference voltage (UR) applied to it, in such a way that the positive input in one comparator (AfO 1) and the negative input of the second comparator (KO 2) is fed with the reference voltage (UR), 7. Circuit arrangement according to Claim 5 and 6, characterized in that the outputs of the comparators (KOi, KO2) are fed to a logic operation, in particular an AND gate (UG) , to the output of which the phase comparison circuit (PH) is connected ίο 8, circuit arrangement according to claim Z to 5, characterized in that the comparison pulses (forward pulses NV, reverse pulses NK) are fed to the forward or reverse input of the control counter (.S7ZJ. 9. Circuit arrangement according to claim 3, 4 and 8, characterized in that the control counter (STZ) is provided with a decoding circuit (DCS) which only allows count values up to a certain size 10. Circuit arrangement according to claim 3, 4, 8 and 9, characterized in that the control counter (STZ) is followed by a code converter (CWS) for generating non-linear (z. B. sinusoidal) reference voltages (UR) 11. Circuit arrangement according to claim 3, 4, 8 to 10, characterized in that by a Control circuit (FFP) square-wave pulse trains (UVR) are generated, which start the rise or. Show falling edge of the alternating signal voltage (US i) , and that these square-wave pulse sequences jo (UVR) as control signals influence the counting direction of the control counter (STZ) . 12. Circuit arrangement according to claim 3,4,8 to 10, characterized in that a differentiating circuit (DS) is provided which at the beginning of the ) 5 rising or falling edge of the signal change voltage (US 1) generates control signals that are fed to the control counter (STZ) and determine the counting direction there.