DE2631916C3 - Differential amplifier made of MOS field effect transistors built on a semiconductor chip - Google Patents

Description

a) a second current source transistor (L _x ') constructed like the first current source transistor (L)),

b) a third amplifier transistor (W) constructed like the first amplifier transistor (Mt ) and

c) a third load resistor (W) constructed like the first load resistor (Ni),

and characterized by the following electrical connections:

d) control input of the second current source transistor (Lt ') to the output of the third amplifier transistor (Mi'),

e) Gates of the third amplifier transistor to ground and

f) Output of the third amplifier transistor (M \ ') with the control input of the first current source transistor (L \).

2. Differential amplifier according to claim 1, characterized by an amplifier (K) having a gain factor Jt between the output of the third amplifier transistor (Mi ') and the control input of the second current source transistor (Li') (F ig. 2,3).

3. Differential amplifier according to claim 1 or 2, characterized in that the first current source transistor (Li) and the similarly constructed second current source transistor (Li ') are formed from MOS transistors which can be controlled by the control bias applied to their gates (Up ₀ !) are.

4. Differential amplifier according to one of claims 1-3, characterized in that the first and third load resistance (/ Vi, Ni ') are MOS transistors which work in the ohmic range.

5. Differential amplifier according to claim 4, characterized by a series connection of the second current source transistor (Li ') with the third amplifier transistor (Mi') and with the third load resistor (Ni ') between the first and second DC power supply line (Ai, A ₂ ), wherein the Gate of the third amplifier transistor (M /) on Ground and its output are connected to the gate of the second current source transistor (Li '), and wherein the control bias (Up ₀ ) at the output of the third amplifier transistor (Mi') is applied to the gate of the first current source transistor (Li)

6. Differential amplifier according to claim 4, characterized by a series connection of the second Current source transistor (Li '), which is parallel to the third amplifier transistor (Mi ') is connected, with the third load resistor (A //) between the first and second DC power supply line (Au A2), the common output of the second current source transistor (Li') and the third amplifier transistor (Mi ') is connected to the gate of the second current source transistor (Li'), and wherein the control bias voltage (Up ₀ ) at the output of the second current source transistor (Li ') to the gate of the first current source transistor

2 »(Lr) of the differential amplifier is applied isL

7. Differential amplifier according to one of claims 1-6, characterized in that the gates and sinks of the first and third load resistors (Ni, Ni) are at the same potential and connected to the first DC power supply line (Ai) are connected.

8. Differential amplifier according to one of claims 1-7, characterized in that it works with common-mode negative feedback and between the

J »first and second DC power supply lines (Ai, A ₂ ) are connected to the drains (Si, S ₂ ) of the first and second MOS amplifier transistors (Mi, M ₂ ) via the first and second load resistors (Nu Ni) the first DC power supply line (Ai)

r> are connected and that the inputs of an adder are connected to the drains (Si, S ₂ ) of the amplifier transistors (Mi, M ₂ ), a current source transistor (Ms) and the output of the adder between the common sources of the Amplifier transistors (Mi, M ₂ ) and the second DC power _{supply line (A 2} ) are connected in series (FIG. 6).

9. differential amplifier according to claim 8, characterized in that first and second load resistors

4 ^r > stand (Ni, / V ₂ ) are MOS transistors operated in the ohmic range, of which the following are connected: the gates and sinks galvanically to the first direct current supply line (Ai) and the sources to the corresponding sinks (Si, S ₂ ) of the first and

V) second amplifier transistor (Mi, M ₂ ).

10. Differential amplifier according to claim 8 or 9, characterized in that the adder has two parallel-connected MOS adding transistors (M ,,, Mt) , of which are connected: the gates

t> to the sinks (Si, S ₂ ) of the amplifier transistors (Mi, M ₂ ), the sinks to the source of the current source transistor (M ₅ ) and the sources galvanically to the second DC power supply line (A ₂ ).

The invention relates to a differential amplifier built on a semiconductor chip with MOS field effect transistors with compensation of the voltage fluctuations at the output of the amplifier in common mode operation according to the preamble of claim 1.

Differential amplifiers of this type are common. In practice, however, it is not possible to determine the quality or

Quality of each individual component of the so formed MOS integrated circuit to consider, given the dimensions of the integrated circuit are very small and these are mass-produced. One Differential amplifiers are fed to two input voltages, the difference of which is to be amplified. These The difference is represented by two amplified voltages at the two outputs of the differential amplifier

Technologically conditioned parameter fluctuations can lead to the amplifier transistors work outside of their normal work area, d. h, outside the linear part of the control characteristic. This creates an undesirable imbalance in the gain of the differential amplifier; i.e. that Output voltage fluctuations occur in common mode.

The task is to create a compensation arrangement to avoid such an asymmetry in the gain of the differential amplifier mentioned above to specify.

The object is achieved by the characterizing features of claim 1

The invention is further developed by the features of the subclaims

While with differential amplifiers whose current sources have a bipolar transistor, the two is assigned to bipolar transistors, the bias of which is controllable (see IBM Technical Disclosure Bulletin, Vol. 6 (August 1963) No. 3, pp. 70/7 !; Electronics technician, 3d. 11 (1972) H. 5, pp. 221-228) are the gain factors in the case of MOS transistors determined by geometric parameters and depend in contrast to bipolar transistors only slightly affect the current in the working area.

In the invention it is achieved that the amplifier transistors in the favorable part of the control characteristic can work, d. In other words, the operating point is on the one hand in the linear part of the control characteristic of each amplifying transistor, with offset voltages in addition are avoidable. In order to achieve this and a centering on a so-called "rest point" of the To achieve the control characteristic of the amplifier, the requirement is met that the sum of the output potentials is zero or constant at both amplifier transistors.

That is, the compensation or control bias is constantly adapted to the supply current source for the two amplifier transistors arranged in parallel, wherein the supply current source is generally also formed by a MOS transistor whose gate the control bias is applied.

It is essential in the invention that a simulation of at least part of the differential amplifier is used, whereby components are used that correspond to the components of the to be compensated Differential amplifier are as equal as possible, so that technologically-related parameter fluctuations of the Components of the differential amplifier to be compensated for the fluctuations in the correspond to similar components of the compensation arrangement or simulation. This creates a Change of the control bias of the supply current source of the differential amplifier and an automatic Neueinstellunjj the working point of the amplifier components depending on the technological parameter fluctuations achieved in such a way that, as desired, the sum of the output voltages is zero or one predetermined constant value is the value of the impedance of the current source transistor which is controllable is determined by a control bias voltage applied to a control input of the supply current source · ", With the flowing current on two between the supply current source and a DC voltage source Amplifier transistors connected in parallel divides The two currents flow through the amplifier transistors in two, preferably also by MOS transistor

K) ren formed load resistances, their gates and sinks at the same negative voltage of DC voltage source lie, each between the amplifier transistors and the DC voltage source are arranged. The gates of the amplifier transistors

is of the differential amplifier are connected to signal sources, whose tensions are to be increased. The components of the compensation arrangement (replica) are chosen in such a way that their dependence on the technological parameter fluctuations

- '' gen described by the same regularity can be.

The compensation arrangement is therefore identical to the assigned one with regard to the most important components Differential amplifier, with the compensation

> ^r i arrangement works statically and the gate of the at least one amplifier transistor is grounded. The structure ensures that the control bias is controlled by various technological parameters in such a way that it in turn compensates

jo are such that the MOS amplifier transistors of the Differential amplifier form a constant output voltage sum. In an advantageous embodiment the invention is the compensation arrangement (replica) together with a bilateral

»I or differential amplifier with negative feedback in common mode is used. This differential amplifier has two DC voltages (e.g. - V and + V) which supply the amplifier with current, and also two MOS amplifier transistors, each of which has its gates connected to a signal source

■ are connected to the voltages to be amplified hand over. Amplified voltages are generated at the drains of these amplifier transistors; the Sinks are each connected to a load resistor to the positive DC voltage. This load

<T) resistors are MOS transistors that are ohmic Work area. The differential amplifier also has a current source transistor, the Gate is connected to the control bias of the compensation arrangement or simulation,

w as well as an adder whose inputs each have one Sink the amplifier transistors are connected. The current source transistor and the adder are in series connected between the common sources of the MOS amplifier transistors and one

Yt supply line of the DC voltage source. An advantageous embodiment of the adder is a parallel connection of two MOS transistors, the gates of which are each connected to a drain of the amplifier transistors.

bii The invention will now be explained in more detail with reference to the drawing explained. It shows

F i g. 1 shows the circuit diagram of a conventional differential amplifier to which the compensation arrangement according to the invention is applied

b ¹ ) F i g. 2 shows the basic circuit of a first exemplary embodiment of the simulation according to the invention, the structure of which corresponds to the differential amplifier according to FIG. 1 corresponds, FIG. 3 shows a second exemplary embodiment of the replica

Training according to the invention with only one branch of the differential amplifier according to Fi g. 1,

4 and 5 other embodiments without the amplifier between the output of an amplifier transistor and the gate of a Stromquellentransi- ^r> stors the model according to F i g. 3, where F i g. 5 shows a preferred embodiment,

F i g. 6 a differential amplifier that works together with the replica is preferred,

7 shows an equivalent circuit of the preferred differential amplifier according to FIG. 6th

F i g. Figure 1 shows a differential amplifier of conventional construction to which the invention can be applied, as shown below. The amplifier has a current source represented by a first MOS transistor L \ , the source (source) of transistor L \ being connected to a DC voltage + V and the drain (drain) to the sources of two amplifier transistors M \ and M ₂ . A control bias voltage U _1x , / , which determines the operating point of the amplifier transistors M \ and Mi , is applied to the gate of the first transistor L \ feeding the amplifier transistors M \ and Mi. The amplifier transistors Mi, Mi are connected to a direct voltage - ^ via load resistors N \ and Ni. The load resistances ι ·> de N \, Ni are according to FIG. 1 formed by MOS transistors that work in the ohmic range, and whose drains and gates are at the same potential - V. The two input voltages, the difference between which is to be formed, are applied to inputs £ Ί κι and Ei , which are connected to the gates of the amplifier transistors M \ and Mi. Output voltages Vs \ and Vs _{2 are} generated at outputs S \ and S _2.

F i g. 2 shows a schematic circuit of erfindungsge- i ^r> Maessen compensation arrangement. This arrangement has the same components as the statically operated differential amplifier according to FIG. 1, the gates of a third and a fourth amplifier transistor ΜΊ and M'2 being connected to ground. The outputs Si and S _{2 of} the -w amplifier transistors M \, M ' ₂ are connected to an adder Σ which calculates the sum Vs, + Vs _2. This sum signal is fed into an amplifier K , the output of which is connected to the gate of a second current source transistor L \ , -r> where the in the first current source transistor L \ according to F i g. 1 fed in control bias Up ₀ I is applied to the gate of the transistor L \ . This arrangement is used to control or regulate the control bias Up ₀ / depending on technological ^r > o räräffictcrSCuWaniCüngcn ucf VcrSCiiicucncn 1 Γαΐϊ5ΐ3ΐΟ- ren M, N, L to ensure the constancy of the voltage sum at the output of the D'fferenz amplifier. To regulate the voltage Up ₀ I , a reference voltage is required, which is represented in FIG. 2 by the negative "voltage - V ". The technological parameters such as the threshold voltages of the MOS transistors M, and M ₂ (A / 'i and M' ₂ \ the channel width of the MOS transistors and the geometric channel lengths of the MOS transistors fluctuate in the differential amplifier (Fig. 1 ) in the same way as in the simulation (FIG. 2), which also applies to possible fluctuations in the voltage + V. More precisely, the transistor N ', in the arrangement according to FIG. 2 as well as in FIG. 4 and 5 represent a (third) load resistor operated in the ohmic range *>"> , the geometry ratio Z / L being less than one, with: Z = width of the charge carrier channel between sink and Source, and L = geometric length of the MOS transistor channel. Like transistor N _1, this transistor ΝΊ is particularly sensitive to fluctuations ΔΖηηά AL in the channel width and length; it makes it possible to adjust the voltage Up ₀ / as a function of these fluctuations in order to compensate for the concurrent fluctuations in the transistor Ni.

The third amplifier transistor M \ is a MOS transistor, the gate of which is at ground (ie at the reference voltage zero V), and which allows the fluctuations of the DC voltage + ^ to compensate for the control bias voltage. The second current wave transistor L ', finally, the channel width Z of which is important, is very sensitive to the threshold voltage V ₅ , which often fluctuates depending on the technology used. The second current source transistor L'i compensates for the fluctuations in the threshold voltage by readjusting the control bias voltage Upoi in accordance with these fluctuations in the threshold voltage Vs. It has been experimentally proven that the use of these three transistors in one of the four cases shown in FIG. 2, 3, 4 and 5 allow the fluctuations of the parameters + V, Vs, Z and L to be compensated.

The replica according to FIG. 2 is not optimal, since the relatively large number of transistors increases the number of causes of errors as well as the space requirement. Because of the interaction of the various components and because of the presence of the amplifier K , the arrangement also has a slow transient response. F i g. 3 shows an arrangement which has only a single branch of the differential amplifier, ie the components M ' and N'u which are as similar as possible to the transistors Mi (and Mi) and N' (and N ₂ ) of the differential amplifier. The component L \ is derived from Li, taking into account that the current through L \ is only half as large as the current through Li.

The embodiment according to FIG. 3 of the arrangement according to the invention dispenses with the two transistors M ₂ and N'i, whose technological fluctuations in parameters run in the same sense as those of the transistors ΜΊ and N \ , so that the two transistors M ' ₂ and N'2 are redundant. The sink of the amplifier transistor M \ is connected via the amplifier K to the gate of the transistor L'i, which is fed into the gate of the transistor L _{1 of} the differential amplifier according to F i g. 1 fed polarization voltage Up ,,, generated

F i g. 4 shows an arrangement without a differential amplifier K, the Phasep.bedingur.ger. between the output of the third amplifier transistor M \ and the gate of the second current source transistor L'i are met by the structure. The geometry of the transistors L'i, M \ and N \ is identical to the geometry of the transistors according to FIG. 3. The arrangement according to FIG. 4 works satisfactorily, although the circuit is not optimal, since the gate of the second current source transistor L'i is at high potential, as a result of which the sink-source voltage of the third amplifier transistor ΜΊ is low and this operates in the ohmic range instead of in the amplifier range.

An even better implementation, which is preferably used in the invention, is shown in FIG. 5, in which the transistors L \ and M \ are connected in parallel and are in series with the transistor N \ . The two DC voltages + V and - V are connected to the series circuit. That lies in this arrangement

Gaiter of the third amplifier transistor M \ always grounded, and the gate of the second current source transistor L \ is coupled to the common output, that is connected to the drains of the transistors L \ and M \. In this circuit the transistor M '\ works in amplifier mode, so that the circuit according to F i g. 5 delivers excellent results and generates an output control bias Up ₀ / which is suitable for regulating technological parameter fluctuations.

F i g. 6 shows a differential amplifier with common-mode negative feedback, which is preferably used together with the compensation arrangement according to the invention. The differential amplifier has two MOS transistors M \ and M ₂ , the gates E \ and £ 2 of which are controlled by voltages or signals Ve \ and Ve ₂ , which are emitted by signal sources (not shown), these voltages being referred to ground are. The sinks Si and 52 of these transistors JW ₁ , M ₂ generate amplified voltages Vii and Vs ₂ , which are fed into the gates of transistors M _b and Mi , which work as adding amplifier transistors of an adder Σ , and their sinks to generate common-mode negative feedback are connected to the source of a current source transistor / W ₅ . The voltages applied to the transistors M _b and M ₇ connected in parallel influence the voltage applied between the gate and source of the current source _{transistor M 5} and thus the current of the current source. The sources of the transistors Mt and M ₇ are connected to a DC voltage line A ₂ ,

whose potential is + V. The gate of the current source transistor Λ / 5 is polarized or biased by connecting a terminal P to a compensation arrangement (simulation) (not shown) which supplies the control bias Up ₀ I. The sink of the current source transistor Ais feeds the sources of the amplifier transistors M 1 and M ₂ . The load resistors JVi and N ₂ work in the ohmic range, the gates and the sinks of these load resistors JV ₁ and N ₂ formed by transistors being galvanically connected to a direct current supply line A \ which is at the potential - V.

In order to limit the changes caused by technological parameter fluctuations as much as possible, the transistor pairs Ai ₁ , Ai ₂ and JV ₁ , JV ₂ and Mt, M _{7 are} made up of transistors that are as similar as possible to one another.

FIG. 7 shows an electrical equivalent circuit diagram of FIG. The amplifier transistors M ₁ and Ai ₂ are represented by amplifier A (with gain A) , the adding transistors M _b and M ₇ by an adder Σ, an amplifier K with a gain factor K being assigned to this adder. Voltages e, ed \ and ed ₂ are offset voltages of amplifiers A and K.

The mathematical derivation of the results generated by the differential amplifier according to Fig. 1 and 2 obtained is as follows:

The output potentials Vs ₁ and Vs _{2 are} calculated using the following equations:

Vs ₁ = A [Ve ₁ + ed, - K (Vs ₁ + Vs ₂ - e) ~ \ , Kv ₂ = A [Ve ₂ + ed ₂ - K (Vs ₁ + Vs ₂ - e ·)].

After a simple algebraic transformation we get:

Vs ₁ = 4 (Ve ₁ - Ve ₂ ) + | _Wl - eä ₂ ) + \

= - 4 C't - ^ve J ⁺ 4 ^M · ~ ^{edi) +} 4 [ Ve ₁ + Ve ₂ + ed, + ed ₂ + 2Ke
1 + 2AK

According to the equations, the differential offset voltage (error voltage) of the voltage difference Vei - Ve ₂ at the input is given by ed \ ~ edi . For this reason it is advantageous to work differentially (the difference between the voltages being smaller than each offset voltage itself) and to ensure that the amplifiers A (represented by the amplifier transistors A '/ ₁ and M ₂ ) are as similar as possible. If the amplifiers are identical, ed \ = edi applies and the differential offset voltage is zero.

The non-differential offset voltage V _o rr at the system input is calculated as follows:

K " = ed, -ed ₂ +

1 -ρ 2. A λ

The equation shows that the influence of the technological parameter fluctuations (ed \, edi and e) as well as the value of the input parameters Ve \ and Ve ₂ have only a slight influence on the offset voltage V _o n if the factor (\ + 2AK), the so-called common mode rejection, is great. The common-mode oftset voltage

κι e (asymmetry of the common clock gain) of the amplifier, the offset voltage of the adder transistors M _b and JW ₇ multiplied by the factor K, shows the interest in a reduction of K, the product AK being constant. This way you can with

«Common-mode negative feedback can be implemented very easily with a minimal number of components

'the, in particular a fast negative feedback can be achieved.
Through the transistor pair JWe and M ₇ is also a

bo series resistor introduced, which _{reduces the output resistance of the current source formed by the transistors JW 5} , Mt and M ₇ by reducing the slope of the current-voltage characteristic.

In addition 3 Bhilt drawings

Claims (1)

Patent address: 1. A differential amplifier built on a semiconductor chip made of MOS field effect transistors with compensation of the voltage fluctuations at the output of the amplifier in common mode operation, with a first current source transistor arranged between a first and a second direct current supply line, the impedance of which can be controlled by a high voltage, which supplies a direct current that is divided between the first and second field effect transistor and flows through a first and second load resistor which is arranged between the first and second field effect transistor and the first DC power supply line, the gates of the field effect transistors being connected to signal sources whose signals are to be amplified, characterized by a differential amplifier circuit constructed on a separate semiconductor chip and arranged between the first and second direct current supply lines (Au A2) , or half of a differential amplifier, which at least contains: