DE2560559C2 - - Google Patents

Description

The invention relates to a data exchange device with the Features of the preamble of claim 1.

The term "data exchange device" thus includes a system from one or more data input and output devices as well as usable portable data carriers.

A generic data exchange device is from DE-OS 22 20 721 known. The data card described there has one Memory, whose connections are directly connected to the contact connections connected to the card. Accordingly, there are none lock upstream of the memory.

Also, no detector is described in DE-OS 22 20 721 which is able to determine whether a currently addressed Space in the storage of the portable disk is free or not.

DE-AS 11 14 049 describes measures for protecting core memories known in the main memory of a computer. Because every bit is stored as a remanent state in a ferrite core, the storage is destroyed when reading out. It is a matter of Mainframe computer with a central processor, a ferrite core memory and associated circuitry to clear the memory. A portable data carrier with a semiconductor memory is not provided there.  

The problem solved in this publication lies in the organization a core memory through computer programs. It works a method by which a memory can be controlled automatically is that the data doesn't get mixed up. It is possible to rewrite a storage space already described, and it is forbidden under certain circumstances to have one to describe free space.

They are already usable as credit cards, bank cards and the like Information cards known (US-PS 37 02 464), the each a memory consisting of solid-state elements included, in which the respective application Data are stored. Such a memory can, for example, from semiconductor elements or from bistable Switching elements can be constructed. By introducing one such information card, which is a disk array represents, in a correspondingly designed recording of a Data input / output device, it is possible Information in the data memory of such a data carrier arrangement  to enroll or information from to read such a data store. Since none Security measures regarding access to the data store the respective information card or data carrier arrangement are therefore abusive Application of such a disk arrangement very simple way possible. So in particular in a very simple way the memory content of the intended data storage can be changed.

A data exchange system is also known (FR-PS 20 44 691), in which the individual data carrier arrangements also easily access to in allow them contained data storage, in particular are formed by shift registers. It is enough it, the respective disk arrangement over their Coupling device, with which it with the data entry / Data output device is connectable to supply clock pulses. In the event that from such a disk arrangement Data should be read out, it suffices, besides the supply of the mentioned clock pulses on the mentioned Coupling point to connect a separate memory, in which the content of the data memory is then, as it were of the respective data carrier arrangement is. But this is also this well-known data exchange system very easily misused, d. that is the content of data storage in an unauthorized manner changeable in the respectively provided data carrier arrangements is or can be read out.

A memory protection device is already known (DE-AS 14 99 687) for the protection of information in certain memory areas of a data processing system against unauthorized access by unauthorized Intended to serve users. This facility is intended to Store assigned storage units for controlling the Have access operations to the memories. At  Memory access operations are designed to protect stored Information in this known arrangement only depending on the identity of the accessing user on the type of access and on certain geometric Storage area limits are expanded. With that but already simple even with this known device Abuse opportunities exist. Abusive Use of the known arrangement needs namely only given a fake user identity to get access to memory areas to which no access should be made. this means but that in this known arrangement abusive Access to the intended memory is not excluded are there for such accesses with the usual Control signals is managed.

After all, it is already an arrangement for data backup in the working memory of an electronic calculator known (DE-AS 12 47 707), in which a comparison device It is provided that when a program runs occurring in succession in a memory address register Data by comparison with in a second register provided data on the affiliation checked the memory area that is currently running Program is assigned, and which emits a signal which the control of the relevant memory cell then blocks, if it does not belong to the currently running program is. In this way, parts of the memory are supposed to secured against destruction by incorrectly programmed addresses will. The designation of those memory cells not to be controlled during the execution of a program are done by programming. This means, that through a change in this programming those Storage areas are excluded from protection able to protect themselves. But that's also an abusive application of this known arrangement not avoided as in this case too access to Memory areas that are to be protected against access,  is possible with the usual control signals.

The invention has for its object in a generic Data exchange device security against fraudulent To increase manipulations.

The achievement of this object is in the claim 1 marked.

Advantageous embodiments of the invention are in the subclaims described.

In a data exchange device according to the invention programmable read only memory (PROM) is used, in particular erasable PROM (EPROM or EEPROM).

The generic term "data exchange device" means that Data from the portable data carrier into the data entry and Output device can be read out or written into the memory from the same are. This data transfer does not have to be necessary done simultaneously. During certain operating times of the portable data carrier can only write data in its memory and during other operating conditions only data can be read from the memory of the data carrier.  

The invention is illustrated below with the aid of drawings for example explained in more detail.

Fig. 1 shows the general structure of a data exchange system according to the invention for processing payment transactions with a bank.

FIG. 2 shows in detail a portable data carrier that can be used in the data exchange system according to FIG. 1.

FIG. 3 shows in detail a netting mechanism that can be used in the data exchange system according to FIG. 1.

FIG. 4 shows a further possible embodiment of a data carrier arrangement which can be used in connection with the data exchange system according to FIG. 1.

FIG. 5 shows a still further embodiment of a data carrier arrangement which can be used in connection with the data exchange system according to FIG. 1.

FIG. 6 shows a possible implementation of a memory control inhibit circuit for a data carrier arrangement.

FIG. 7 shows a basic circuit diagram of a data delivery / data recording device which can be operated in conjunction with a data carrier arrangement according to FIG. 5.

FIG. 8 shows an addressing circuit of the arrangement shown in FIG. 7.

Fig. 9 shows a circuit diagram of a data storage circuit for storing m * n 1-bit words in a data memory adapted to store m words each with n bits.

FIG. 10 shows a symbolic representation of the data storage circuit shown in FIG. 9.

FIG. 11 shows a possible form of realization of a clock circuit for the data storage circuit shown in FIG. 9.

FIG. 12 shows a further possibility of realizing a data carrier arrangement which serves a data memory for storing m · n 1-bit words.

FIG. 13 shows a still further possibility of realizing a data carrier arrangement with a data memory corresponding to the type shown in FIG. 9.

FIG. 14 shows yet another embodiment of a data carrier arrangement in which the writing into prohibited coded memory sections of the provided data memory is prevented.

All embodiments of the described below Data exchange device according to the invention are in particular for Applications in banking and accounting provided. For this reason and to make reading easier, will explain how it works and how it works Effects largely on the banks and management a bank account uses its own terminology. However, the embodiments may be different Used for purposes and used everywhere there where necessary, especially confidential data and irreversible way of storing.

The electronic circuits of all described below Embodiments are because of their use inaccessible in banking in a portable, hereinafter also referred to as a data carrier arrangement Object, in particular in the form of a flat rectangular Card is formed, arranged. you are incorporated into this object in an inaccessible manner, d. H. it is not possible to connect to the electronic Get circuits without destroying them. This Result can be achieved in particular that these circuits in the form of logic microcircuits (integrated circuits) executed and in an opaque Plastic are embedded, however other mechanical solutions are also conceivable.  

In all figures, the disk arrangement (the card) concern is the wrapping which the circuit parts, which are electrically or optically inaccessible from the outside, limited, represented by a dashed line.

The coupling means are the only elements that unite electrical or optical access to the inside of the Allow electronic components contained in the card.

In order to make the description of the electronic circuits as simple as possible, the supply circuits have not been shown. However, the supply connections that are to be set up between the data carrier arrangement and the data input / output device are indicated by the characters VP, VG , ground (characters which each identify the write voltage source, the general supply source of the logic circuits and the zero line).

Finally, it should be noted that in these embodiments used monolithic read-only memory of various types, especially programmable or can be reprogrammable. Such stores do not require energy for that Storage of information. In contrast, requires writing information in general a considerable achievement (several Watt). Therefore, the manufacturers guarantee an extreme long storage times on the order of several Decades in the event of reprogrammable Storage. Stores of this type are:

INTEL 1702 and National Semiconductor 5203. This memory can be extinguished by ultraviolet rays or by x-rays. HARRIS 7620, Monolithic Memory 6340, TEXAS INSTRUMENTS 74 S 387, INTERSIL 5604. These cannot be deleted Stores are in the backup or Link breakdown type executed.

Memories with capacities of 4096 bits are different Manufacturers, especially in  Area of the MOS memory (erasable). The modern ones Process for connecting integrated Circuits enable the at low cost Production of a memory block with 16 kbits or 32 kbits (4 or 8 plates) on one surface of several 10 mm², including the special ones Circuits of the subject of the present invention, such that this block in a map with the dimensions 2 × 60 × 80 mm³ can be included.

These monolithic semiconductor memories have Compared to other storage devices, such as magnetic "cassettes", elastic washers, etc., significant advantages. they are more reliable and their dimensions are smaller. They do not require mechanical movements for that Reading and writing are insensitive to magnetic Fields and difficult to falsify and to damage (the fraudster must have complicated electronic Use means to determine the state of the semiconductor memory to change). These semiconductor memories are therefore in Particularly suitable as a data memory compared to other memories to be used in the invention. This is true especially for the applications of the systems for banks to.

The different embodiments of the data storage  the invention differ significantly from each other by building the portable disk assembly. Not more than once (on the occasion of each embodiment) the description of the with the portable data carrier arrangement connected transmission device to repeat we only described them twice:

In detailed form in connection with FIGS. 1, 3, in general and concise form in connection with FIGS. 7, 8.

However, it will be apparent to those skilled in the art that each of the portable disk assemblies shown in the figures are connected to a transmission device may be all or part of the properties of the described transmission devices having.

The data exchange system shown in FIG. 1 has two different parts which are connected in operation by a transition which is symbolically represented by a dash-dotted line.

In the left part of Fig. 1, a portable data carrier arrangement is shown, preferably in the form of a ring, a card, a pendant, a pin (z. B. carried out in an integrated design).

On the right-hand side of FIG. 1, a data input / data output device, preferably a banknote dispenser or a cash register, is shown for direct use at a point of sale. In the latter case, the business process described below is not associated with the issuance of banknotes, but rather with the entry of information into the merchant's cash register, which later enables the merchant to receive a counterpart in paper money or book money from the bank of the holder of the data carrier arrangement .

For the sake of clarity, this description continue to issue banknotes assumed what is otherwise regarding the electronic Building up the use of a cash register entirely is equivalent.

The circuits of the ring as a portable data carrier arrangement here contain an identification memory 40 , a target memory 51 and a credit memory 50 as a data memory. The system allows the following operations during its use:
Identification of the holder of the data carrier arrangement (portable data carrier) a process which either enables or prevents the further process;
possibly reading a credit line and transferring this credit line into the credit memory of the data carrier arrangement;
Issue of a requested cash amount, if and only if the account balance of the holder of the data carrier permits this;
Registration of the entirety of the processes for the purpose of booking and / or for later review on a data carrier, such as a semiconductor memory.

The operations to be performed by the media owner are as follows:
Possible entry of an approved credit line via the reader 114 ,
Enter the confidential identification number using the keyboard 31 ,
possible entry of a target sum using the keyboard 63 ,
these three operations can be performed in different chronological order,
Introducing a projecting part of the data carrier arrangement (of the ring) to a corresponding location provided in the housing of the data input / output device.

At the moment when the holder of the data carrier arrangement effects the last operation that is his responsibility, ie the introduction of the data carrier arrangement into the data input / data output device, all of the operations listed above are carried out very quickly. Almost instantly, the system will have completed this operation, allowing one of the following possible outcomes depending on the choice of disk arrangement owner and his account balance:
Simple checking of the account balance by numerical display of the balance by means of a display organ 69 ,
Checking the account balance after entering a credit as a result of an entered "credit approval", which is taken up, deleted or eliminated in a manner not shown, after the credit has been written into the credit memory of the data carrier arrangement,
Checking the account balance after entering a credit balance and issuing cash, the new account balance after these two operations being necessarily positive or zero,
Checking the account balance after issuing cash; As in the previous case, cash is only issued if the balance of the new balance is positive or zero.

The various functional sequences of the system that serve as an overview for the following description are the following:
Feeding the data carrier arrangement,
Commissioning of the general control of the various elements of the system by triggering a multiplexer,
Operation of one of three memories ( FIG. 2),
Operation of one of two series balancing units (marked with AS / S ) ( Fig. 3),
Reading previous credit balances,
Registration of the new credit balance,
Reading previous target values,
Registration of the new target status.

The banknote dispenser has a power generator 150 that feeds a winding 151 . When the data carrier arrangement is inserted into the output device and thus into the data input / data output device, the winding 151, as the primary winding of a transmitter, is coupled to a secondary winding 105 , which is part of the circuitry of the data carrier arrangement. This winding supplies a DC voltage via a rectifier circuit, consisting of a diode 106 and a non-capacitive electronic filter 107 , which is intended for the various supply circuits of the data carrier arrangement. If necessary, the electromagnetic coupling is replaced by a coupling, the elements 150 and 151 being replaced by a light source and the winding 105 by a photocell. The coupling of the data carrier arrangement and the data input / data output device is effected in a simple manner in that a projecting part of the data carrier arrangement is introduced into a corresponding location provided in the housing of the data input / data output device. This introduction causes a contact 27 to be closed by a mechanical impact, which is part of a general supply device, not shown, for the circuit of the banknote dispenser. At the same time, a timer 28 is triggered, as a result of which a 1 signal is emitted to a first input of an OR gate 41 . This 1 signal is maintained for so long that the identification of the owner of the data carrier arrangement can be effected. It should be noted that the second input of the OR gate 41 , which is connected to the output of a flip-flop 42 , carries a 0 signal, due to the corresponding setting of the flip-flop 42 , which occurs when a 1 signal occurs is set at its clearing input CL via the OR gate 86 . If this identification attempt succeeds (it becomes clear from the following under what conditions this happens and what this entails), the supply connection is maintained until the end of operation of the banknote dispenser, on the basis of a 1 signal at the second input of the OR gate 41 .

In contrast, the absence of this signal, which indicates that the user has used an incorrect identification number, suppresses the supply connection by the occurrence of 0 signals at the two inputs of the OR gate 41 , the 1 signal coming back in from the first input a 0 signal is transferred while the 1 signal has not been set at the second input. This means that the banknote dispenser cannot be used. The design of the timer 28 can be left to the person skilled in the art.

It should be noted that the entire described here Arrangement is wired in positive logic.  

Commissioning of the general control

If a 1 signal occurs at one of the two inputs of the OR gate 41 , this signal is fed via this OR gate to an AND gate 34 and also to a monostable multivibrator 35 which can be triggered upon the occurrence of a rising signal or pulse edge. The monostable multivibrator 35 , in the stable state of which signals 1 and 0 appear at its two outputs, delivers a pulse of complementary value (1 pulse at the output identified by 0 and 0 pulse at the output identified by 1 ) during the occurrence of one rising pulse leading edge at its input. During the duration of the pulse emitted by the monostable multivibrator 35 , the output denoted by 1 outputs a 0 pulse to the second input of the AND gate 34 , which thus remains blocked, ie remains blocked. The other output 0 of the monostable multivibrator 35 delivers a positive 1 pulse to an input of a counter 36 reset to zero, which counter controls the demultiplexer 38 . At the end of the pulse emitted by the monostable multivibrator 35 , the stable 1 signal appears again at the output of this multivibrator labeled 1 , whereby the AND gate 34 is opened, that is to say can be transmitted. This AND gate now allows a first pulse supplied by the clock generator 33 to pass. This pulse transmitted to the counter 36 brings the demultiplexer 38 into its first position, the T line 160 being connected to the starting position 0 . The pulse just mentioned is also fed to the input of a monostable multivibrator 37 which can be triggered on a falling signal or pulse edge and which works like the monostable multivibrator 35 , but with the difference that it only receives a pulse at its input when a falling pulse leading edge occurs delivers at output 0 . This pulse occurring at the output 0 of the multivibrator 37 is transmitted from the demultiplexer 38 to its output 0 . After the occurrence of this pulse, this part of the arrangement remains unchanged until the next pulse emitted by the clock generator 33 occurs . The cycle then repeats itself in the same way as before, the counter 36 causing the demultiplexer 38 to pass from output 0 to output 1 ; the next pulse emitted by the clock generator 33 is then given with a delay and after shaping by the monostable multivibrator 37 from output 1 (if the RG line 161 of the demultiplexer 38 leads again with a 0 signal). This operating cycle is thus carried out in succession for the ten output states of the demultiplexer 38 , the last eight in succession each giving a positive pulse to one and the same clock line 162 via the OR gate 39 . It should be noted that the signal state at the output 9 of the demultiplexer 38 is immediately followed by the signal state described above, which occurs at the output 0 . This part of the arrangement controls the system throughout its operation.

In addition to supplying the circuits of the data carrier arrangement the transfer of information between the data carrier arrangement and the data input / output device in the same way by optical Coupling between a light emitting diode and a photodiode.

Reading the confidential identification number

If a positive pulse occurs at the output 0 of the monostable multivibrator 35 , a 1 signal is fed via the OR gate 60 and the optical coupling 45 to a memory input of the data carrier arrangement, as a result of which its credit memory 50 and its target memory 51 are correct on their first memory page Get state to trigger a later read operation (here, the memory page is understood to mean a total of several parallel memory locations of the respective memory, each memory page or memory location specifying a blocked state or an open state, depending on whether it has been written to or not , in an irreversible way). The signal mentioned also resets the series balancing units 32 and 49 and the counter 47 to the counting position 0 . The memory 40 is fixed on its first memory page by a constant 1 signal at its (zero) memory input (this signal is symbolized by a plus sign in FIG. 1); because the memory contains only a single page, which is principally and previously described for the life of the data carrier arrangement and which contains the confidential identification number of the holder, registered at the moment the account is opened. It should be noted that the confidential code (not shown) is designed such that it represents both the holder of the data carrier arrangement and his bank.

The memory or data memory 5 of the data carrier arrangement ( FIG. 2) is permanently in the read position by a 0 signal at its read / write input E / L , which means the closing of the contacts 3 and the ineffectiveness of the memory control blocking circuit or of the locking element 2 causes. The 8-bit counter 1 (address counter), followed by the blocking circuit or the locking element 2 , is used to address the memory 5 (a single address is used here, which is that of the first memory page). For the credit memory and the target memory, the transition from one to the other memory page takes place at the beginning of each clock cycle by a pulse at the RG input 161 ; this pulse, which is delayed by the monostable multivibrator 88 , causes the address counter 1 to continue counting. The first pulse, which appears on the conductor RG , resets the 4-bit counter 6 , which controls the output multiplexer 4 ; it has the address counter 1 counted one step after it has been delayed by the monostable multivibrator 88 . In accordance with the occurrence of the clock pulses, the values of the different bits are recognized on the selected memory side of the memory 5 , which are present at the output under consideration from the bit with the highest weight to the bit with the lowest weight and which are in series via the coupling 104 to the Naldierwerk 32 are transmitted, which indicates a number x by counting in binary and parallel form, which is fed to the input of a comparator 30 . The other inputs of the comparator 30 are already supplied with a number y in the same form, which has been encoded in a manner not shown from the identification number which was previously entered by the owner of the data carrier arrangement on the decimal keyboard 31 . If x and y are the same, the comparator 30 outputs a signal 1 via the AND gate 85 to the set input of the flip-flop 42 , which thereby toggles and outputs a signal 1 from its output to the one input of the OR gate 41 . This ensures that the clock control 33 is maintained after the timer 28 has stopped. The presence of the AND gate 85 obliges the holder of the data carrier arrangement to enter his confidential code within a prescribed period, corresponding to the time when the timer 28 is active .

Operation of the identification balancing unit 32 ( FIG. 3)

In the present case, the device 32 is operated only as an addition device. It is held in the positive counting position by a continuous signal 1 at its counting / subtracting C / D input, symbolized in FIG. 1 by a plus sign. It essentially has a 16-bit counter / subtractor 11 (of which only the 8 bits of low value are used here), to which, in the presence of a positive information bit at the input of the AND gate 10 from the memory 40, that from the clock generator 15 are delivered via the AND gate 14 impulses. The zero reset signal originating from the conductor 161 blocks the AND gate 14 via the OR gate 16 and the flip-flop 13 and resets the 4-bit counter 12 to zero, which sets the multiplexer 9 into its ineffective zero position. The first clock pulse leads the multiplexer 9 out of a position, whereby it is converted into its input state by the counter 12 . The first clock pulse also flips the flip-flop 13 , whereby the blocking of the AND gate 14 is released, which allows the pulses of the clock 15 to pass; clock 15 is 300 times faster than clock 33 . Before the occurrence of the second clock pulse, 128 pulses of the clock 15 have possibly been introduced into the 16-bit counter / subtractor 11 via the AND gate 10 . At the end of the 128th pulse, the frequency divider 20 outputs a signal 1 to the input 1 of the multiplexer 9 , as a result of which the AND gate 14 is blocked by the flip-flop 13 via the OR gate 16 . The system remains unchanged until the occurrence of the second clock pulse, which puts the multiplexer 9 in its input state 2 . The previous cycle is now repeated. The following information occurring at the AND gate 10 corresponds to the read value of the bit which follows in rank immediately after the bit with the greatest weight (2nd bit of the first memory page of the memory 40 ). The confidential identification number is thus read, translated into a pulse number according to its value, written into the unit 11 in a stable binary form and transmitted parallel to the input x of the comparator 30 (compare: FIG. 1). The shift register 17 with serial input and parallel output ( FIG. 3), followed by the locking element 18 and the OR element 19 , signals the end of an empty memory page by emitting a signal 1 , ie a memory page on which all bits contain the information 0, so nothing has been registered. This arrangement for the acquisition of zero, marked with DZ , is not used here; rather, it will be in the netting mechanism 49 , as will be described below.

Reading the previous credit status (see Fig. 1)

When a signal 1 appears at the output of the comparator 30 , it is transmitted via the AND gate 85 (the timer 28 has not yet been stopped), which is connected to the set input PR of the flip-flop 42 . This flip-flop now outputs a signal 1 from its output instead of a signal 0 , which maintains the operation of the general clock generator 33 until the end of the operation of the entire arrangement. This signal 1 is fed to the one input of the AND gate 87 , whereby this AND gate is transferable until the end of the operation of the arrangement; the units 50, 51, 49, 47 and consequently 46 and 48 are already reset to 0 , as described above. At the beginning of the cycle the data carrier arrangement to be introduced, the information contained in credit memory 50 in the Saldierwerk 49 via the output S of the memory 50 and the coupling 119 according to the identification of the owner, according to a method of reading the confidential identification number first during the Corresponds to the clock cycle. The transition from a memory page of the memory 50 to a subsequent memory page takes place in the memory 50 by means of a pulse at the beginning of the clock cycle via the RG line 161 , specifically via the coupling 44 . The sum of the values of all previous credit levels that have been introduced into the credit memory in a manner described below appears in a stable form at the output of the series balancing unit 49 in binary form. It is made visible by means of the display device 69 after a transcoding, not shown, which is familiar to the person skilled in the art. The same remark for an inverse transformation applies to the keyboards 31 and 63 in the tens system. It should be noted that during the reading operation of the credit status, the series balancer 49 is in the counting position due to a signal 1 at its input from the output 0 of the decoder 48 and the OR gate 52 . After arrival of the value contained in the last described memory page of the memory, the memory page, which is read in the following clock cycle, is an empty page, which is recognized in the series balancer 49 by a signal 1 , which at its output DZ to distinguish it from a 0 the shift register 17 is output ( FIG. 3), the eight latch circuits 18 being driven by the output T and the NOR gate 19 at the beginning of the second clock cycle. This signal 1 blocks the delivery of a clock pulse RG 161 from the output of the AND gate 82 , specifically via the multivibrator which can be triggered on rising signal or pulse edges ( FIG. 1) in such a way that the addressing of the memory 50 is maintained and the writing of a new credits or credit balances possibly required by the owner of the data carrier arrangement are made possible on the blank page.

Registration of the new credit balance

The same zero detection signal 1 that passes through the OR gate 108 causes the counter 47 to advance in its counter position, and puts the multiplexer 46 in its input position 1 and the decoder 48 in its output position 1 , which the balancing mechanism 49 does holds a signal 1 at the other input of the OR gate 52 in a positive count position. The same signal 1 reaches the write / read input of the credit memory 50 via the coupling 57 , as a result of which the memory in question is brought into the write position as a result of ineffective locking elements 2 , opening of the read contacts 3 with the transferable AND element 7 . The input of the information in serial form into the page provided for registration is now effected via the multiplexer 113 ( FIG. 1), on the one hand in the direction of the credit memory via the coupling 120 and on the other hand in the direction of the series balancing unit 49 via the multiplexer 46 , the Multiplexer 113 is controlled by counter 115 , which in turn is controlled by general clock 33 . The value of the credit sum is therefore written on the first empty memory page of the credit memory 50 and added to the sum which was previously indicated by the display element 69 via the 16-bit counter / subtractor of the series balancing unit 49 . The end of the written memory page is detected by the AND gate 59 , the two inputs of which at the moment each carry a signal 1 , the first input being connected to the output 1 of the decoder 48 , while the second input is at the output of the highest weight of the Counter 115 is connected via the monostable multivibrator 140 which can be triggered on falling signal or pulse edges, the task of which is to detect the transition of counter 115 from state No. 7 to state No. 0. When the reading and registration of the new credit or credit balance in the memory 50 has ended, the corresponding value is deleted in a manner not shown in a credit note reader 114 by a signal transmitted to the input E via the conductor 93 . The output of the AND gate 59 , which carries a 1 signal, now controls the credit memory and the target memory back to zero via the OR gate 60 and the coupling 45 , and also allows the counter 47 to advance in its position via the OR gate 108 .

Reading the previous target levels

The new position of the counter 47 brings the multiplexer into its input state 2 (reading of the target memory 151 ), as a result of which a signal occurs at the output 2 of the decoder 48 ; the outputs 0, 1 and 3 of the decoder 48 carry 0 signals, as a result of which the series balancer 49 comes to the subtracting position as a result of a signal 0 at its input C / D. The reading of the previous target values is now effected like the reading in the credit memory 50 via the coupling 122 , the number representing the sum of these target values being subtracted from the number already written in binary form in the 16-bit counter / subtractor of the series balancing unit 49 , ie from the number previously displayed by the display organ 69 . The first empty memory page of the target memory is detected by a signal 1 at the output DZ of the series balancing unit 49 by means of the AND gate 109 . It should be noted that at the moment this information appears, the outputs of the series balancer 49 are in a stable, numerically binary state, according to the operation:
X = (total of previous credit levels) + (new credit level) - (total of previous target levels).

The value X is necessarily positive even if the new credit balance is zero. If the previous balance and the new credit balance are zero, then the value X is obviously also zero, which is a borderline case.

The value of the money which may be intended to be output by the system described - this value was entered by the owner of this data carrier arrangement using the decimal keyboard 63 before the data carrier arrangement was introduced into the output device - in its binary form Y with X by the binary comparator 110 compared. If a signal 1 occurs at the output 3 of the decoder 48 , which occurs during the last reversal of the counter 47 , caused by a signal 1 at the output of the element 109 by the element 108 , the comparison of X and Y leads to the output of a signal 1 from the single output of comparator 110 if, and only if X is greater than Y. At that moment, the counter 115 which controls the successive input states of the multiplexer 116 is reset to zero as soon as the counter 47 has been determined in its last state. The arrangement is now in the writing position for entering a new target level.

Registration of a new target status

The multiplexer 46 , which is in its input position 3 , is connected to the target memory 51 via the coupling 124 in order to write a new target status, the value of which is simultaneously subtracted by the series balancer 49 and displayed in the display element 69 in the same manner as before. It should be noted that the monostable multivibrator 81 for the target memory 51 plays the same role that it plays for the credit memory 50 , ie the entry in the memory is carried out on the first empty memory page and not on the subsequent one, which is also an empty memory page is. On the other hand, from the output 3 of the decoder 48 , which carries a signal 1 , the setpoint memory 51 is brought into the write position, during this last phase of the operation of the arrangement via the coupling 123 , and at the end of this phase a general stop signal by flipping the flip Flops 42 is caused. As a result, a signal 1 occurs at the erase input of this flip-flop via the OR gate 86 , as a result of the corresponding output from the AND gate 111 , which in turn is made transferable by a positive pulse at its input, which is from the zero output of the monostable multivibrator 140 , which acts in the same way as at the end of the writing of the new credit or credit balance in the memory 50 . The process of issuing the banknotes (not shown) takes place during the same time that the new desired status is being written into the desired memory 51 , the amount of which has previously been entered in decimal form by the owner of the data carrier arrangement using the keyboard 63 and has been tested as previously described.

The coupling with the aid of a transformer for supplying the data carrier arrangement from the data input / data output device has been chosen and is shown in FIG. 1 in such a way that this ensures galvanic isolation. The secondary winding 105 of the transformer, which is formed by the windings 15 and 105 during the interaction of the data carrier arrangement with the data input / output device, is followed by a filter 107 , which provides a regulated DC supply voltage at its output, the filter being non-capacitive due to the reduction , because the capacity required for a classic filter cannot be made small enough in relation to the other electronic elements. This supply coupling could also be realized by an optical coupling between a light source, which is contained in the data input / data output device, and a photocell in the portable data carrier arrangement, whereby the desired galvanic isolation is ensured in order to avoid any short circuit which would destroy the could cause storage contained in the disk array. The same applies to the other optical couplings which have been selected for the transmission of the information between the data input / data output device and the data carrier arrangement. The three memories, whose functions have been described, are basically of the same design. When implemented in an integrated circuit, they have the property of being described irreversibly and sequentially if desired (except for certain types of memory, which can be deleted by non-random means, but by appropriate handling). These memories, the capacity of which is approximately 1000 times larger per unit area than that of the magnetic memories generally used for this purpose, have the advantage over the latter that the reading and enrollment are easier and more adaptable, owing to the fact that that they do not require the proximity of the reader. They are addressed electronically, with complicated, expensive and unreliable electromechanical devices being replaced by simple conductors, the number of which can also be reduced by the known multiplex method. Non-volatile memories are preferably used among these memories in an integrated circuit.

The display element 69 is used for simple visualization by means of luminous digits, but it can also be replaced by a printing unit, this printing unit having parallel branches at its inputs in order to give the holder of the data carrier arrangement the possibility of reading a document from the data input / data output device to read or retain read operations performed during the operation described above.

The method applied to a bill dispenser can also be applied directly at a point of sale be, whereby the holder of a disk arrangement in the Able to make his purchases without the purchase amount due is settled in cash or check but only by  that the data carrier arrangement of the buyer is charged with the purchase price becomes.

FIG. 4 shows an embodiment of a detector for determining an unprogrammed memory section in the event that the detector is contained in the data carrier arrangement 400 designed as a card. This embodiment shows a memory or data memory 201 , the address supply of which is controlled by a blocking circuit or a locking element 205 . The AND gate 202 forms the detector of an empty address; it drives a memory 204 which controls the write element 203 and the locking element 205 .

FIG. 5 shows another embodiment of the detector for an occupied memory section for the case in which the detector is contained in a card 400 as a data carrier arrangement.

The data memory 209 , configured for m words with n bits (e.g. 256 words with 8 bits), is externally routed through the conductor bundle 207 (8 in the selected example) via the blocking circuit or the locking element 210 (8 blocking or Locking units) addressed (see FIG. 6, in which a special embodiment of a locking element is shown, E, S, C denoting the input, the output and the charge control input, respectively). In the empty state, all memory points of the data memory carry a 1 signal. This can be an integrated circuit of type 1702 (Intel), 5203 or 5204 (National Semiconductor) or 7620 (e.g. Harris semiconductor).

A bundle of conductors 220 (here 8 conductors) leads away from the output of the data memory and is directed outwards.

The control input 211 , when carrying a signal 1 , enables the execution of write operations which are triggered by increasing the supply voltage of the data memory and by the supply of a write bit.

When a voltage is applied, the flip-flop RS , which is formed by the elements 217 and 215 , is automatically adjusted so that a signal 1 on the conductor due to the presence of the capacitor 213 which is connected to the positive terminal of the supply source 216 occurs. The same capacitor effects a control of the locking element 210 and the blocking of the writing element 212 for a brief moment via the OR gate 218 .

If the address indicated by the conductor 207 at this moment is an empty address (eight output conductors 220 carry a signal 1 ), then the presence of a signal 1 at the output of the AND gate 214 with its eight inputs forces the flip-flop RS to end pulse sent from the capacitor 213 to output a 0 signal.

With regard to the undervoltage of the portable data carrier arrangement, this has the consequence that the locking element 210 is locked or locked and the element 212 becomes transmissible, which allows the address to be written into the relevant address via the conductor 219 .

This state is stable until the next overvoltage, ie any change of address is impossible from now on, since the pulse emitted by capacitor 213 occurs only once.

If the address displayed when the voltage is applied is already occupied (occurrence of a single zero on the conductor 222 ), the occurrence of a signal 0 at the output of the AND gate 214 has no effect on the flip-flop RS , which is therefore found in the Allows state 1 to be set via capacitor 213 . The occurrence of a signal 1 at the output of the OR gate 218 therefore prohibits writing. Addressing is now possible, whereby reading of all occupied addresses of the data memory is permitted.

The first empty address causes the flip-flop RS to go to state 0, which allows writing and the addressing is prohibited until the next voltage drop.

If the user is writing in or with two consecutive Addresses, it is for him necessary to suspend the voltage of the assembly to stride, and then to a new one Applying the voltage.

The arrangement so formed can easily be in shape an integrated monolithic circuit and on a support, e.g. A card (e.g. 5 × 8 cm²) can be fixed with 20 connections:

• 8 address managers
• 8 information output managers
• 3 supply conductors (general supply of the peripheral circuits VG , supply of the memory VM , ground)
• 1 write command leader

When executed in a non-monolithic form, the Arrangement of six separate housings integrated Circuits and a capacitor exist in one printed circuit are connected, which the necessary Provides connections and serves as a mechanical support.  

The supply of the portable data carrier arrangement is effected by the conductors 208, 220 and 221 .

The data input / output device capable of exchanging data with such a card is shown in brief form in Fig. 7, which will now be described. The supply is effected by the VG 240 and ground 238 conductors and by the VM 208 conductor during the write phase.

The received data, forwarded via conductor 224 to processing element 244 , is optionally compared with respect to its addresses (transmitted via line 252 , which is connected to line 222 ) with possible external data which is transmitted via conductor 248 , the result of the processing carried out triggering write operations by the write element 246 (conductors 254, 256, 226 ), registration operations 250 , display operations 251 and / or output operations 253 as well as checking or verification operations 258 .

The writing element 246 serves to coordinate the various processes required for writing:
Increase the voltage VM (special supply source for the programmable memory 209 ) to the level VP , signal 1 on the electrical conductor 226 , disconnection of the conductor 224 , then supply of a corresponding signal which is to be written.

The addressing element 242 advantageously has a binary counter modulo n = 257, which is able to address the memory with its successive addresses and thus write with the first empty available address thanks to the NAND gate 260 , the AND Member 262 with three inputs 262 and the clock generator 265 ( FIG. 8).

NAND gate 260 is used to indicate to processing element 244 that the currently activated address is an empty address. This NAND gate 260 could be omitted if the counter 257 were automatically reset to zero when voltage was applied to the device.

In the case of a 16 kbit memory (1365 memory pages of 12 bits each) a total of 27 connection points are required for the circuit, which could be inadmissible. To reduce the number of connections, one can create a multiplication of the input and the output and / or use a basic memory which is arranged for words with one bit, as described further below in connection with FIG. 9, in which a A memory grid is shown which is set up for mn words with one bit and which is formed from a primary memory which is set up for m words with n bits, where n is the format of the desired word. This grid contains the various multiplication circuits as well as write circuits which allow the storage of a selected bit (one of the eight bits of one of the 256 "pages") by simply controlling the connection of a single write input.

The writing of such a programmable memory is generally accomplished in several steps. A An example of a cycle is the following:

• 1. addressing a selected word,
• 2. separation of the output stages of the memory,
• 3. Increase in the supply voltage of the memory the right value
• 4. Connection with a predetermined voltage of the bits intended for writing (replacing the initial state by a state 0).

This definition often corresponds to a memory output with a so-called "open collector".

All of these operations must be taken into account very often different time constants.  

Fig. 9: Memory 302 (e.g., of the 7620 Harris type) is connected to resistors 338 to 345 and eight NAND power elements 304 to 311 , which may be formed by transistors with open collectors. An input of each of the eight NAND gates is connected to point D of the memory (controlling the separation of the output stages). The supply input of the memory, to which each of the resistors is connected, is connected to the output 352 of an electronic switch, which consists of transistors 334 and 336 and the inverter 347 . If a signal 0 is present on conductor 350 , transistor 336 is blocked, while inverter 347 activates transistor 334 ; this creates a connection between point 352 and the general supply VG . In contrast, when a signal 1 is present, point 352 is connected to the write supply VG .

The clock device 326 and the elements 348 and 303 ensure the correct chronological order of the successive commands which correspond to the write operation.

The latch circuit or latch 332 is used to hold the address by a signal 0 (determined by the inverter 328 ) at its or its latch input 356 during a write operation.

11 address weights are required when a 256 x 8 bit memory is used as 2048 x 1 bit memory, the eight higher weights addressing the actual memory ("memory pages"), while the three less significant weights read 322 and write demultiplexer 320 taxes.

If the address is selected from 11 bits, a positive write command on conductor 330 locks or latches latch 332 while sequentially disconnecting the memory (conductor 360 ), increasing the supply voltage (conductor 350 ) and warming up the second input of the selected NAND gates of NAND gates 304 through 311 via conductor 362 - thereby allowing control of demultiplexer 320 - to be made.

The addressing process is the same for reading, via the multiplexer 322 which controls the output conductor 366 .

The inverters with a high input threshold 312 to 319 serve to isolate the multiplexer 322 and the NOR or exclusive OR gate 324 during the write phase.

The NOR or exclusive OR gate with eight inputs 324 detects in the form of a signal 1 on the conductor 370 a completely empty memory page with eight bits.

The storage arrangement under consideration can be illustrated schematically in the manner shown in FIG. 10. It has 17 access connections:

• 11 address lines ( A ₀- A ₁₀)
• 3 supply points VP-VG mass
• 2 outputs: S (bit) and AV (display of a blank page)
• 1 write control E.

An embodiment of the clock circuit 326 is shown in FIG. 11. It essentially has three flip-flops RS 373, 374 and 375 , which are successively controlled by four delay elements 376-377-378-379 . Inverter 372 issues the write command. A simple modification of the circuit would allow the memory arrangement under consideration to be equipped with any type of memory: changeable, fixedly programmable or "programmable / reprogrammable". These modifications are familiar to the person skilled in the art. FIG. 12 shows another exemplary embodiment of the blocking circuit (this is the detector for an unprogrammed memory section) in the event that the memory is set up for mn words with one bit (for example 2048 words with one bit). In this embodiment, the detector is included in card 400 .

Element 516 represents a memory arrangement which, in addition to the actual memory, includes the various circuits required for the execution of the write process. These circuits are activated by a single positive command supplied via conductor 503 .

The clock 502 sequentially controls the forwarding of the various addresses of the memory via the counter / subtractor 512 , the blocking circuit or the locking element 514 and the logic elements 504 , 506-508 . The shift register 530 converts the information successively exiting from the memory into parallel representations of 8 bits. The divider 536 divides by eight and issues a test command to the register 530 after every eight clock pulses. This command is fed through capacitor 538 and OR gate 540 to latch 523 which is connected to the output of eight gate AND gate 525 . If the output of this AND gate carries a signal 0 (occupied memory page), the addressing is continued. If the output of the locking element 523 carries a signal 1 (completely empty memory page), then the lock input of the logic element 504 interrupts the forwarding of the clock pulses, sets the counter / subtractor 512 in the subtracting position and makes the AND element 520 transferable, which in turn is the one from Clock 502 coming pulses forwarded through the OR gate 506 .

The counter / subtractor starts counting again until the eighth pulse of this sequence (detected by the divider 526 which divides by eight) by the flip-flop RS consisting of the NOR gates 522 and 524 , can tilt, whereby the AND gate 520 is blocked and the clock 502 are put out of operation.

The memory is now located at the first empty address that follows a written memory page. From now on, writing is permitted via the links 528 and 529 , which in each case transmit the write command which is supplied from the outside via the conductor 531 , and the addressing bit by bit which is transmitted externally via the conductor 533 via the links 506 and Allow 508 to be forwarded. The logic elements 508 and 510 and the inverter 518 serve to lock or lock the address and to record the state of the address counter during the write pulses.

Capacitor 542 allows a single pulse to be sent that resets all controls of the array to 0 when voltage is applied.

The RS 548-550 flip-flop is finally reset to zero by the transition of the counter / subtractor 512 to the maximum count position CM (conductor 546 ), which produces a stable signal 0 on conductor 552 , which has the consequence that the addressing Link 529 is locked.

This arrangement prevents a fraudster from returning to an occupied address by using the addressing input 533 bit by bit beyond the nominal capacity of the counter.

After the voltage has been applied, the arrangement supplies all the information it contains in the memory to the conductor 517 , then adjusts itself to the first address of the first empty memory page, specifically in the write position, controlled by the logic element 560 , the blocking input of which commands " Ascending / Descending "of the counter at the end of a sequence of eight (falling) pulses to zero.

The synchronization pulses are transmitted to the outside via the conductor 509 .

It follows that the clock 502 could also be arranged outside the arrangement. In this case, the conductor 509 would serve to synchronize the storage arrangement from the outside; it should be connected to point 544 .

This card or data carrier arrangement requires for its good connection with the Only six connection points in the vicinity.

The possible review of the writing process will end  the operation by briefly interrupting the supply, Read the new content of the memory and comparing with the old, previously grasped content and / or with the write message likewise stored causes.

The divider 554 , which divides by eight, and the flip-flop 556-558 allow the addressing pulses to be limited bit by bit in accordance with the write operation to eight. Within the framework of the same application of the voltage to the portable data carrier arrangement, only a write operation on the first empty memory page (a word of eight bits) of the memory 516 is possible.

FIG. 13 will now be described, in which another embodiment of the memory drive inhibit circuit (the detector for unprogrammed memory sections) is shown for the case in which the memory arrangement has the form described in connection with FIG. 9. In this embodiment, the detector is arranged on the card or data carrier arrangement 400 . The memory 570 used is for multi-bit words, e.g. B. 256 × 8 bits. It includes its own write and read multiplex circuits. A logic element ( FIG. 9) connected to its eight parallel outputs enables the detection of an empty memory page (signal 1 present at all inputs and consequently at its output), but the addressing is nevertheless effected by 1-bit addresses.

The first page of memory (the first eight bits) becomes mandatory be occupied (presence of at least one zero bit).

After the voltage has been applied, the blocking circuit or the locking element 578 emits a signal 0 (first occupied address), as a result of which the AND element 573 is opened via the inverter 579 and allows the pulses coming from the clock generator 574 to pass.

The counter 571 now addresses the memory (by 1-bit words), while the divider 575 , which divides by eight, signals the latches 578 via the OR gate 576 and the capacitor 577 the side changes.

At the first empty page of memory, a signal 1 from the output of the locking element will block the AND element 573 and the write element 580 will open. The addressing can now continue bit by bit from the outside via the conductor 583 and the OR gate 572 , while the write pulses are likewise passed from the outside via the conductor 581 .

The information is output via conductor 582 , while the external synchronization takes place via conductor 584 .

If the memory only has occupied pages, set the addressing continues to a certain extent during the user is informed of the state of the arrangement becomes.

The flip-flop 586-587 , which is connected to the output CM 585 of the counter 571 , permits the blocking of the write element 580 bit by bit, beyond the nominal capacity of the counter.

The capacitor 588 outputs a single pulse to the conductor R ₁, which resets all series elements of the portable data carrier arrangement to zero at the moment the voltage is applied.

A card or data carrier arrangement designed in this way can be an advantageous one Embodiment of a semiconductor register include. If you have a memory of programmable / reprogrammable Type (electrical or optical erasure) would contain it - e.g. B. with a cash register of a point of sale - a registration according to the number of their settings allow, with words of a hundred bits for example the Account number of the buyer (84 bits) and the purchase price (16 bit).

A card with e.g. B. 16 memories of 2048 bits each  therefore enable the registration of 327 purchases, what z. B. an operation of 6 days with 9 hours a day one Checkout with a purchase every 10 minutes corresponds.

If this card regularly to the bank to collect of information, for deletion and replacement with a If an empty card is brought, this card plays the card possible connection role between a collection facility the data (point of sale) and the processing facility (Bank).

In another area of use (recording of alphanumeric data), this card could be the equivalent register from approximately 90 typewriter pages (this is the case with an individual health book or one ID or an identity document).

In the following, Fig. 14 is described, in which an embodiment of the memory drive inhibiting circuit is shown, which is intended to prevent the change of the content of memory sections coded as prohibited. The blocking circuit is contained on a card 400 .

Memory 601 is arranged for words of 9 bits, e.g. B. 256 x 9 bits. In the empty state, all storage locations carry signal 1 . The bank account number that e.g. B. consists of 21 digits, ie 84 bits, is divided into eleven words with 8 bits, each word being followed by a bit B ₉ of zero. The initial write occurs from B ₁- B ₉ for each of the eleven pages of memory occupied by the account number such that the cancellation of the ninth bit only prohibits the write after it has been executed. The writing element 602 , which may have to be able to hold an increased voltage at its input 605 , controls the separation input 606 of the memory (often marked with CS, E or ME in the technical literature). This is addressed by the bundle of conductors 604 (8 conductors in the example given), while the eight input / output bits are available at point 603 . The command is given to conductor 607 .

This embodiment has the advantage of possibly making each address irreversible with eight bits of memory. However, it requires a considerable number of connection points to the outside (21 in the example shown) and a device with diodes 608 which prevents the link 602 from being made transmissible from the outside.

Claims (6)

1. Data exchange device with:

• - at least one data input and output device,
• at least one portable data carrier, which receives supply and control signals from the data input and output device only when it has been connected to it, and which contains an addressable programmable semiconductor memory which is connected to a data line, an address line, a write line and a read line are provided, which lines can be connected to the data input and output device, so that data can be read from the memory into the data input and output device or can be written into the memory from the same,

characterized in that the memory ( 201, 209; 516; 570 ) is divided into a plurality of sections, each with n bits, and in that the data carrier ( 400 ) contains the following circuits in the form of built-in components:

• - a detector ( 202, 214 ) which, in accordance with the content of a memory section just addressed via the address line ( 207; 533; 583 ), emits a blocking signal whenever at least one of the n bits of this section is written, and
• a lock ( 203, 212; 528; 580 ) which is connected to the write line ( 211; 503 ) of the memory and cooperates with the detector to prevent writing to the memory as long as the detector emits a lock signal, so that sections of the memory already described cannot be overwritten.

2. Data exchange device according to claim 1, characterized in that the data carrier ( 400 ) further includes a holding circuit ( 205; 210; 504; 573 ) which is in series with the address line and assumes a holding state when the detector does not emit a blocking signal , whereby an address entered in the memory is held as soon as it corresponds to a section not described. 3. Data exchange device according to claim 2, characterized in that the data carrier ( 400 ) further includes an initialization circuit ( 204; 213-218; 542-550; 586-588 ), which when connecting the data carrier ( 400 ) to the data input and - output device temporarily interrupts the operation of the lock so that the address can be changed and the associated memory content can be read out, as long as no unwritten section is encountered. 4. Data exchange device according to claim 2 or 3, characterized in that the detector has two logic elements ( 202, 203; 214, 212 ), of which the first logic element ( 202; 214 ) the content of the respective memory section of the semiconductor memory ( 201, 209 ) in parallel form, while the second link ( 203; 212 ) is enabled to perform a write operation if the relevant memory section of the semiconductor memory ( 201; 209 ) contains no written bits, and that between the first link ( 202; 214 ) and the second Linking element ( 203; 212 ) a memory circuit ( 204; 215, 217 ) is interposed, which allows the activation state of the first linking element ( 202; 214 ) to be recorded at least for the duration of a registration cycle ( Fig. 4, 5). 5. Data exchange device according to claim 4, characterized in that the memory circuit is formed by a flip-flop ( Fig. 5).