EP0329966B1 - Method for securing secret code data stored in a data memory, and circuitry for carrying out this method - Google Patents

Abstract

The invention relates to a method and circuitry for securing code data stored in a code data memory (1a) prior to analysis, in which the signals at the code data memory outputs provide an indication of the contents of the code data memory. According to the invention, a blocking circuit (4), controlled by a blocking logic circuit (9), is provided at the code data memory outputs, which it blocks as soon as entered control data fails to match the code data. <IMAGE>

Description

The invention relates to a method for preventing the unauthorized reading of a secret code, which consists of a number of code data and is stored in a code data memory.

Such a method and an integrated circuit for carrying out the method are known in principle from EP-OS 0 207 320.

Such an integrated circuit represents, for example, an essential element of a so-called chip card, which can be used in security and access systems, in billing or registration systems and in debit and credit systems. The integrated circuit and the data memory are accessed via external contacts on the card surface in a card reader.

In many applications, memory data are stored in a memory area referred to as code data memory on the respective cards and are used as secret code data for identification or authentication of the card user or the card. System security depends on how well this code data is protected against misuse. For this reason, very high demands are placed on the fraud security of cards and readers. Due to the security precautions corresponding to today's experience, however, a direct attempt to analyze the content of the code data memory, which usually consists of an EEPROM memory and in particular a sub-area of said data memory of the card, little chance of success. However, it is possible to draw conclusions about this memory data from the indirect influence of the code data on the code memory outputs or on the connected peripheral logic.

US Pat. No. 4,102,493 also discloses a circuit in which secret data are fed from a memory to a comparator device and compared there with control data. However, all secret data from the memory are always shown there. Although these cannot leave the entire device that contains the memory, a fraudster could determine the entire secret code by examining the line between the memory and the comparator device.

From FR-PS 23 11 360 it is known to determine an access authorization to provide a certain number of code entries by the operator and to store all inadmissible attempts in a memory provided for this purpose until the entire memory space is occupied. The unit to be protected is then put out of operation.

From EP-OS 0 127 809 a circuit arrangement is known in which data comparisons are carried out between stored code data and control data entered from outside, the address space of the memory area containing the code data being divided into several subsets, each defined by a selection logic, with several Address lines are connected to an address control unit from which an enable signal can be tapped if at least one address from each subset has been selected in the course of the comparison operation. From EP-OS 0 128 362 a circuit arrangement with memory and security logic is known, in which after comparison of an entered control word with a stored code word is written into at least one memory cell of an operation data area, the address of which depends on the comparison result. Here are access attempts registered with incorrect control data entries because, in addition to the access release, the operation data memory is only deleted after the release procedure has been successfully completed. Due to the limited size of the operation data memory, the number of permissible incorrect entries is limited.

In the circuit arrangements described above, however, the code data stored in the data memory are largely unprotected to the comparator device in which they are compared with input control data.

In particular if a comparator device is provided for comparing the code data with control data entered by the user and the code data is transmitted via a data transmission device, e.g. If a data line or a data bus are routed to this comparator device, for example a comparator, the code data could be read on this data transmission device. A data transmission device mentioned above can in particular contain the column lines of the data memory as well as the column decoder and the data bus.

An integrated circuit described in EP-OS 0 207 320 contains a non-volatile code data memory, which is in particular of the EE-PROM type and in which a secret code is stored. This code data memory is connected via a data bus to an input of a comparator circuit, the other input of which is provided for the control data to be entered. The output of the code memory or the data bus is in this case equipped with a blocking circuit which can be controlled by a logic circuit in such a way that the outputs of the memory cells, as a rule the column lines of the memory field, are blocked in the normal state with respect to the peripheral logic. The lock is only released for a short period in which the secret data in the peripheral logic is actually required for the data comparison. The possibility of performing an analysis of the code data is therefore limited to a short period of time, but is not absolutely impossible. In particular, when the lock is activated, the output lines of the code data memory to be protected are switched to a defined potential independently of the stored information.

In order to further limit the number of possible analysis attempts, the start of a code data memory access is initiated by a write operation in a counter memory which is addressed together with the relevant code word. This counter memory is only reset when the control data corresponding to the code data has been entered correctly and a control process has been completed. As a result, the size of the counter memory determines the number of incorrect access attempts. An additional identification memory identifies the cells of the data memory that make up the code data memory, so that the access block is restricted to this area only.

A circuit described in this laid-open document limits the task of code data from the code data memory onto the data bus, but analysis of all code data is only made more difficult, not prevented.

The object of the invention is to provide a method for absolutely saving secret code data stored in a data memory prior to analysis.

This object is achieved by a method according to claim 1.

Secret code data stored in a data memory, which are compared with input control data with the aid of a comparator device and which must be passed from the data memory output to the comparator device via a data transmission device, can be analyzed while they are on the data transmission device. Such an analysis can be prevented by not sending all secret code data from the data memory to the data transmission device after initiating a data comparison, but rather by activating a blocking circuit according to the invention by the first input of control data which do not match the code data further output of code data to the data transmission device prevented.

It proves to be particularly favorable if, after a correct data comparison of all code data making up a complete code has been completed, further output of code data from the memory to the data transmission device is prevented.

The code data should preferably only be output from the memory to the data transmission device after a comparison process has been registered, for example by writing a counter bit. If the registration is carried out by writing a counter bit, it can also be ensured by an upstream logic circuit that the counter bit described was previously not written to. Said registration, in particular by writing a counter bit, can be provided both for the permanent registration of all access attempts made and for the registration of incorrect access attempts. If the registration is to be carried out using an error counter, a logic circuit must be used to ensure that the error counter can only be reset after the correct data comparison has been carried out.

The security of the method can be further increased by the fact that even in the case of byte-by-byte stored code data, these are transferred serially to the data bus and compared bit by bit with the control data. As soon as the first control bit does not match the corresponding code bit, the output of the next code bit to the data transmission device is then prevented.

If an error counter is provided for counting the erroneous control data, each erroneous control data input requiring the restart of a data comparison according to the invention, it is advantageous for reasons of security if the number of comparison operations required for a comparison cycle is as large as possible compared to the maximum permissible one Number of incorrect control data entries. However, at least the number of comparison operations required for a comparison cycle should be greater than the maximum permissible number of incorrect control data entries.

The FIG shows in the form of a block diagram a particularly favorable embodiment of an integrated circuit for carrying out a fuse method according to the invention.

Here, block 1 represents a data storage device which contains at least one code data storage 1 a and can in particular contain an identification memory. Block 2 contains an enable counter, which can be used in particular as an error counter and which is activated to guide a comparison cycle, in particular by writing a free counter bit. Block 3 contains a control logic circuit which controls whether a counter bit of the release counter 2 was previously unwritten and was then written, and in this case forwards a corresponding release signal to a blocking logic circuit 9 according to the invention. Block 4 contains a blocking circuit which is intended to prevent the code data of the code data memory from being output to a data transmission device 6 and, in particular in the activated state, sets the data outputs of the code data memory or the data lines connected thereto to a fixed potential. Block 5 contains a comparator device which compares the control data entered at input 7 with the code data located on data transmission device 6 and provides the data corresponding to the comparison results at an output 8. Embodiments of the circuits contained in blocks 1, 1a, 2, 3, 4 and 5 and of the data transmission device 6 and their mode of operation are described in the published patent application of the European Patent Office EP-OS 0 207 320.

In the case of a monolithically integrable electronic circuit in which a code data memory 1 a is connected via a blocking circuit 4 and a data transmission device 6 to an input of a comparator device 5, in which these comparators device 5 has a further input 7 and an output 8 providing the comparison results, the output of further code data to the data transmission device 6 is prevented in that a blocking logic circuit 9 according to the invention activates the blocking circuit 4 due to the first negative comparison result at the output 8.

With such a circuit, the output of the code data from the code data memory 1 a to the data transmission device 6 is made possible in particular by the blocking logic circuit 9 after the write of a previously free enable counter bit by switching off the blocking circuit 4.

It proves to be particularly favorable if the blocking logic circuit 9 contains a switch-off logic circuit 10 which, after the comparison of correct control data with the code data of a complete code, causes the blocking circuit 4 to be activated. Because the signal at the output 8a of this switch-off logic circuit 10 is dependent on complete correct control data input, it can also be provided for resetting an error counter and, in addition to the signal at the output 8 of the comparator device 5, as an enable signal for the entire safety circuit. The switch-off logic circuit 10 preferably contains a counter which is reset when the blocking circuit 4 or the release counter 2 is activated, which counts by one for each correct data comparison of the comparator device 5 and which activates the blocking circuit after comparing the last code bit.

The function of a circuit according to the invention is described below with reference to the particularly favorable exemplary embodiment shown in the FIG.

The control logic circuit 3 monitors whether a counter bit of the release counter 2, which was not previously written, is written to. An output of this control logic circuit 3 is connected to the set input of an RS flip-flop 12, which is in the blocking logic circuit 9 is included. After a counter bit has been correctly written into the release counter 2, this flip-flop 12 is set. The inverted output QN of this flip-flop 12 is connected to the control input of the blocking circuit 4 and deactivates the blocking circuit when the flip-flop is set. The blocking circuit 4 contains, in particular, a switch T for each data line, which switches this data line to a fixed potential when the blocking circuit 4 is activated. Another embodiment of the blocking circuit 4 according to the invention is implemented in such a way that the column decoder of the code data memory 1 a is switched on for all columns when the blocking circuit 4 is activated. As a result, all outputs of the code data memory 1 a are in parallel and an association between the information of the code data to be protected and the information on the data transmission device 6 is not possible. If the blocking circuit 4 is deactivated, code data from the code data memory 1 a can be transmitted bit by bit or byte via the data transmission device 6 to a first input of the comparator device 5. The comparator device 5, which can in particular consist of a known type of comparator, compares the code data present at its first input with the corresponding control data entered at its second input 7 and preferably outputs the comparison results serially at its output 8.

If the code data is identical to the control data, preferably comparing bit by bit, then the blocking logic circuit 9 triggered by the output 8 of the comparator device 5 only causes the blocking circuit 4 to be blocked when the corresponding data comparison is the last data comparison of a comparison cycle, that is to say when the last correct data comparison the entire code has been compared with correct control data. This is achieved, for example, in that for each comparison result of a correct data comparison, a counter circuit 10 counts one unit further, that this counter circuit 10 is reset at the beginning of a comparison cycle, which is partly due to a reset of the counter circuit 10 can be achieved with the activating control signal of the blocking circuit 4 and that the counter circuit 10 outputs a signal at its output 8a when the counter reading, which corresponds to the total number of comparison operations corresponding to the code, which causes the blocking circuit 4 to be activated. According to the invention, an address counter provided in the integrated circuit can also serve as counter circuit 10. The multiple use of such a counter leads to a chip area saving.

This signal at the output 8a of the counter circuit 10 can also be provided as a reset signal of an enable counter 2 operated as an error counter and as an enable signal of the code security circuit. This release signal can release any function to be protected and can also enable, for example, the release of a CPU contained in a microprocessor, in particular the release of the program decoder or the data decoder.

If the code data differ from the corresponding control data, the first comparison operation of the comparator device 5 with different data already causes the blocking circuit 4 to be activated.

The activation of the blocking circuit 4 by the output signal of the switch-off logic circuit 10 and by the output signal of the comparator device 5 in the presence of a negative data comparison can in particular be achieved according to the invention in that the output 8 of the comparator device 5 is connected to an input of a logic gate 11 and the output 8a of the switch-off logic circuit 10 is connected to the other input of this logic gate 11 and that the output signal of this logic gate 11 is provided to act on the reset input of the flip-flop 12 contained in the blocking logic circuit 9.

If the blocking circuit 4 is to be activated when there is a high signal at the output 8 of the comparator device 5 and at the output 8a of the switch-off logic circuit 10, an OR gate, for example, fulfills the function of the logic gate 11.

Claims (5)

1. Method for preventing the unauthorized reading of a complete secret code which comprises a number of code data and is stored in a code data memory (1a), in which the code data memory (1a) is connected via an inhibit circuit (4) by means of a data transmission device (6) to a first input of a comparison device (5), the second input of which receives check data, and in which one output of the comparison device (5) drives the inhibit circuit (4) via an inhibit logic circuit (9), having the following method steps:

   a) outputting a first code bit of the complete secret code from the code data memory (1a) to the data transmission device (6),

   b) comparing the code bit with a corresponding check bit by means of the comparison device (5),

   c) if the code bit read out of the code data memory matches the check bit, a further code bit is read out of the code data memory (1a) and a further check bit is applied to the comparison device (15) and method step b) is then repeated,

   d) if the code bit read out of the code data memory (1a) does not match the check bit, the further reading out of code data is prevented by means of a signal from the comparison device (5) via the inhibit logic circuit (9) to the inhibit circuit (4).
2. Method according to Claim 1, characterized in that after a correct data comparison has been completed, a further output of code data from the code data memory to the data transmission device (6) is prevented.
3. Method according to one of Claims 1 or 2, characterized in that the output of the code data from the code data memory (1a) to the data transmission device (6) is enabled only after the writing of a counter bit.
4. Method according to one of Claims 1, 2 or 3, characterized in that the code data are transmitted serially on a data bus (6).
5. Method according to one of Claims 1, 2, 3 or 4, characterized in that an error counter (2) for counting the incorrect check data inputs is provided, in that with the aid of said error counter (2) the number of incorrect check data inputs is limited in a known manner, and in that the number of compare operations required for a compare cycle is greater than the maximum permissible number of incorrect check data inputs.

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