DE2515660A1 - METHOD AND CIRCUIT FOR GENERATING AND INDUCTIVE TRANSMISSION OF FM SIGNALS - Google Patents

Description

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PLl / Schneider-st / tex 7.4.1975

R.No. 1385

Method and circuit for generating and inductively transmitting FM signals

The invention relates to a method for generating and inductive Transmission of FM signals according to the preamble of claim 1.

The traffic broadcasting system has been in place in the Federal Republic of Germany for some time ARI (= Car Driver Broadcasting Information) introduced, with which traffic information is conveyed via the VHF transmitter will. These traffic reports provide information about road conditions and traffic obstructions and often also pointers to possible ones Detours and alternative routes.

The information of the road users via the traffic radio station is usually intended for the entire collective of users of federal motorways and trunk roads. An individual information is therefore not possible, with the exception of the so-called emergency call. Another

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PLI / Schneider-st / tex -2- 8.4.1975

R.No. 1385

Difficulty in terms of information, especially during the main travel season, the language barrier. Visitors from abroad who do not speak German must then go through the most important traffic information Announcements are taught in their mother tongue, e.g. from Norddeutscher Rundfunk in Danish and Swedish.

Another difficulty for the road user caused by the ARI system is not mastered is due to the fact that, depending on the weather conditions and the traffic density, observing the traffic signs to find the destination is considerably more difficult.

In order to avoid the mentioned disadvantages of the ARI system, a new traffic guidance system developed for motorways and expressways. With this system, a vehicle driver after naming the Information relevant to the destination, such as directions, road conditions, best speed, etc., is automatically displayed on a display panel brought to the display. :

The invention is based on the object of a method and a circuit for generating and inductively transmitting FM signals for a To develop a traffic guidance system, with a high degree of digital building blocks being used to create an integrated Enable circuit.

This task is cited in the characterizing part of claim I. Features solved.

The invention has the great advantage that due to the aperiodic Behavior of the circuit no transients occur. This is achieved by converting a digital signal

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PLl / Schneider-st / tex

8.4.1975 R. No. 1385

into another with a staircase shape, the envelope of the latter consisting of parts of a sinusoid, only using ohmic resistances will.

Another advantage of the invention is that the frequency of a digital signal is changed by an external command so that an externally controllable fast frequency shift keying is possible.

The invention also has the advantage that it is in the push-pull output stage only a single analog amplifier part is required.

In the following an embodiment will be described with reference to a drawing, in which the circuit according to the invention in a Traffic guidance system is used.

Show it

Figure 1 is a block diagram of the road device, Figure 2 is a block diagram of the vehicle device, Figure 3 is a circuit diagram of a sine wave generator.

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R.No. 1385

The new route guidance system essentially consists of in vehicles built-in vehicle devices and street-mounted devices. A vehicle unit contains the assemblies receiver 1, Transmitter 2, cycle control 3, address switch 4, display unit 5 and ferrite antenna 6. A road device that at traffic decision points How motorway exits, intersections, triangles and road crossings are set up, the road loop assembly contains 7, receiver 8, transmitter 9, cycle control 10, address memory 11 and transmission device 12 to a central traffic computer 13th

The data exchange between the road device and the vehicle device takes place Via an induction loop 7 laid in the roadway and a ferrite antenna 6 attached to the vehicle.

The input, output and storage of information takes place both in the road device as well as in the on-board device, purely digital. For transmission via the loop 7 or the ferrite antenna 6, a Binary information into a pulse duration modulation and then into converted to a frequency modulation. There are two frequencies used by a switchable frequency divider 14 from one can be obtained with a color carrier crystal stabilized oscillator 15.

Its frequency of 4.433 MHz is divided by a total of 40 and by 30,

so that the two frequencies f = 111 kHz and f = 148 kHz are obtained.

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R.No. 1385

All occurring binary information is with the help of the frequencies f and f coded as follows:

The "Low" (L) state is indicated by a signal made up of 7 periods of frequency 148 kHz and 16 periods of the frequency 111 kHz, the state "High" (H) is indicated by a signal of 22 periods of the frequency 148 kHz and 6 periods of the frequency 111 kHz are shown.

A so-called start step is generated by a signal of 30 periods the frequency 148 kHz and 6 periods of the frequency 111 kHz are shown.

For the purpose of exchanging information between road devices and on-board unit, the road unit continuously sends call steps that are identical to the start step just described.

If a vehicle equipped with an On-Board Unit is above an induction loop 7, the call steps from the vehicle device recorded and evaluated. The call steps are used to switch off the vehicle receiver 1 and at the same time switch on the vehicle transmitter 2, which in turn transmits a destination address set in the address switch 4 of the vehicle to the road device.

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R.No. 1385

The address switch 4 is a four-digit hexadecimal code working coding switch set up. Accordingly, a destination telegram is sixteen bits long. With this telegram length there are 65,536 possible destinations.

The telegram begins with a start step that sends the sender 9 des Road device off and the receiver '8 turns on. Then the sixteen bits of the target telegram are transmitted, three times in a row, two consecutive telegrams are checked for identity.

The vehicle then automatically switches to receive and in the street device on send. The road device sends a start step and an instruction telegram, the direction, speed and Contains special instructions and which consists of eight bits, also three times in a row. The data transfer is now complete.

The following is a rough outline of the block diagrams of the road device and the on-board unit. Since the electronics of the road device are predominantly that of the vehicle device the same, the same reference numbers are used for identical components in both devices.

A signal received via the induction loop 7 passes through a low-pass filter 16, an amplifier 17 and a limiter 18, the it brings it to a rectangular shape with TTL level and an AND gate 19 a counter 20 with which the two frequencies f and f are determined in a period measurement. The counting frequency is used

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PLl / Schneider-st / tex - 7 - 8 April 1975

R.No. 1385

Natural frequency of the oscillator 15, which is connected to an input of the AND element 19 is connected. A decoder 21 of the counter 20 supplies a pulse for each period. These pulses are counted in a period counter 22, and on the one hand the information "start step" is recognized in a start step recognition circuit 23, if present, and on the other hand it is recognized the information "low" and "high" obtained in a bit detection circuit 24.

Becomes a starting step that a vehicle has sent from the starting step detection circuit 23 recognized, the latter interrupts the one from the road device! sent call step clock with the aid of a call step clock circuit 25 and A reversing circuit 26 contained in the cycle controller 10. The receiver 8 of the road device remains switched on until the destination address of the vehicle has been received three times.

The destination address consisting of 16 bits is, as already mentioned, three times ^! sent by the vehicle. From the bit detection circuit 24 the signal arrives on the one hand via a bit counter 27 at an input of an AND element 28, on the other hand it is fed to a shift register serving as a 16-bit buffer 29 and to an input of an exclusive OR element. The output of the 16-bit buffer 29 is connected to a second input of the exclusive-OR element 30 and to a memory 31. The output of the exclusive-OR element 30 is connected to a flip flop 32. The outputs of the flip flop 32 and the memory 31 are connected to further inputs of the AND element 28. If the bit counter 27 has counted to sixteen and two consecutive messages contained in the signal were identical, the message content is passed on to the memory 31, and the target address contained in the telegram reaches a storage and programming unit 33 via the AND element.

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PLl / Schneider-st / tex -8- 8.4.1975

R.No. 1385

The storage and programming unit 33 is constructed so that in her the incoming destination addresses are assigned to the associated directional instructions will. After a target address has been recorded, a connection is made from the output of the AND element 28 to an input of the reversing circuit 26 the road device is switched from "Receive" to "Send".

One of the storage and programming unit 33 becomes a destination address Corresponding directional instructions including any existing one! Additional information passed on to a parallel-to-serial converter 34, so that in the memory and programming unit 33 space is created for new instructions from the central traffic computer 13 via the transmission device 12 can be received. As a transmission medium between the transmission device 12 and the central traffic computer 13 telephone lines already available on motorways can be used.

The instruction telegram received by the parallel-to-serial converter 34 has a size of eight bits and is composed as follows: two bits for a direction instruction, one additional bit. From the eight possibilities these three bits are the codes for directional instructions without additional instructions and directional instructions with the additional instructions "Goal outside", "goal reached" and "wrong direction" built up; ι two bits for a recommended speed, two bits for one Road status report, one bit not yet used.

As already mentioned, a road device transmits in "idle mode", i.e. if there is no data exchange with a vehicle, continuous call steps with intermittent reception pauses in which a vehicle is involved can answer after receiving a call step. Sending the

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R.No. 1385

Call steps as well as the sending of instruction telegrams are carried out by the cycle controller 10 is controlled. It consists essentially of the call pacing circuit 25, the reversing circuit 26, the Parallel-serial converter 34, a coding counter 35, a bit counter 36 and a telegram counter 37.

The call pacing circuit 25 ensures that during encoding of a call step the transmitter 9 of the road device remains switched on and the receiver 8 is switched on briefly after the transmission will. The telegram counter 37 causes a telegram consisting of a start step and the instruction pending on the parallel-serial converter 34 is sent three times.

The eight bits of the instruction are in parallel on the parallel-to-serial converter and are queried there serially via the bit counter 36, and they reach the coding counter in parallel as states "Low" or "High" This converts the frequency f and f into the number of periods corresponding to the states and is sent with the Frequency counted. After the number of periods f required for "low" or "high" has been reached, the coding counter 35 sends a switching signal to the Transmitter 9 associated switchable frequency divider 14, so that it is then transmitted at the frequency f.

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R.No. 1385

At the output of the switchable frequency divider 14 arise the initially mentioned frequency-modulated telegram pulses. These square waves are at one input of an AND element 38, the second input of which is connected to an output of the reversing circuit 26 is. The second output of the conversion circuit 26 has an input of the AND element 19 connected.

From the output of the AND element 38, the square waves get into a transducer 39 where they are converted into sinusoidal oscillations. The sinusoidal oscillations are amplified in a transmitter output stage 40 and transmitted via the road loop 7 to the vehicle.

The block diagram of the vehicle device will now be explained. as far as it deviates from that of the road device.

If the vehicle device receives a call step from the road device, so the signal picked up by the ferrite antenna 6 arrives via components of the vehicle receiver 1 to 1 which have already been described for the road device to the period counter 22, then in a call step recognition circuit 41. From there, a signal is sent to an input of an OR element 42 given, the output of which is connected to the reversing circuit 26. The reversing circuit 26 causes the receiver 1 and 2 to be switched off a simultaneous switching on of the transmitter 2.

As already mentioned, a destination address is set on address switch 4, the sixteen bits of which are present in parallel on the parallel-to-serial converter 34. As with the road device, the instruction telegram is now sent from On-board unit sent a target telegram, whereby the cycle control the on-board unit differs from that of the road unit only in this way.

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PLl / Schneider-st / tex - 11 - 8 April 1975

R.No. 1385

separates that a bit counter 43 is designed for sixteen bits and that the output of the telegram counter 37 directly to an input of the reversing circuit 26 is connected, so that the call pacing circuit is omitted. After sending a target telegram three times, the Telegram counter 37 that via the reversing circuit 26 of the transmitter switched off and the receiver 1 is switched on and at least for the time to transmit three telegrams so that an instruction telegram from the road device can be received.

The transmitter 2 of the vehicle device is connected to the transmitter 9 of the road device identical.

If the on-board device now receives an instruction telegram from the road device, which, as is well known, consists of eight bits and is sent three times in succession, the telegram reaches the bit recognition circuit 24, where again the information about the states "Low" and "High" is obtained.

The output of the bit detection circuit 24 is up to the AND gate 28 evaluated in the same way as in the road device, with only one bit counter 44 designed for eight bits and one 8-bit buffer 45 and a memory 46 designed for eight bits are used.

If two consecutive instruction telegrams are recognized as identical, the telegram content arrives at the output of the AND element 28 on a Display field 47 optically for display. If the instruction telegram contains, for example, the direction instruction "turn left" and the additional instruction "Fog", the left directional arrow and the text "Fog" light up on the display field 47. Via a three-tone generator 48 and a loudspeaker 49 the arrival of an instruction telegram is indicated acoustically.

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R.No. 1385

Via a connection from the output of the AND element 28 to a second After the instruction telegram has been received by means of the reversing circuit 26, the input of the OR element 42 is the receiver 1 of the on-board unit switched off.

As a rule, the instructions on the display 47 remain that long received until another data exchange takes place between the vehicle device and another road device. The display panel can but can also be deleted manually beforehand by deleting the instruction telegram in memory 46 by means of a switch 50 will.

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PLl / Schneider-st / tex - 13 -. 8.4.1975

R.No. 1385

After the block diagrams of the road device and the on-board device have been described, the following describes the circuit for generating and inductively transmitting FM signals, which are used in both the Sender 2 of the on-board unit as well as in the sender 9 of the road unit for Application.

The new transmitter essentially consists of the following assemblies: Oscillator circuit 51, first frequency doubler circuit 52, switchable frequency divider 53, second frequency doubler circuit 54, converter 55, output stage

In the oscillator circuit 51 in which the crystal oscillator 15 is connected in parallel is connected upstream of a controllable capacitor 57 and a fixed capacitor and in which the quartz oscillator 15 has a first resistor 59 connected in parallel with a first inverter 60, a third capacitor 61 and a second resistor 62 connected in parallel with a second inverter 63 are, a digital clock signal is generated with the natural frequency of the crystal oscillator 15 of 4.433 MHz.

The clock signal present at the output A of the oscillator circuit 51 is on the one hand fed to a clock output B via an inverter 64 and on the other hand to an input of a NAND gate 65. At a second entrance of the NAND gate 65 is a command signal brought in via an input C.

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PLl / Schneider-st / tex - 14 - 8.4.1975

R.No. 1385

The output of the NAND gate 65 leads to the first frequency doubler circuit 52 and is there on the one hand with an input of an inverter 66, on the other hand via a first capacitor 67 with an input of a NOR gate 68 connected. A first resistor 69 connected to ground is connected downstream of the first capacitor 67. The output of the inverter is connected to a second input of the NOR gate 68 via a second capacitor 70. The second capacitor 70 is a grounded second resistor 71 connected downstream. At the output of the NOR gate 68, which is also the output of the first frequency doubler circuit 52 forms, there is a digital clock signal of 8,866 MHz.

The digital clock signal of 8,866 MHz is sent to a counter input B of a 4-bit binary counter 72 of the type 7493 (see Siemens data book 1974/75, Volume I, Digitale Schaltungen MOS, page 178), which is the core of the Frequency divider circuit 53 forms.

It should be noted that in the 4-bit binary counter 72 the output Q. is not is connected to the counter input B, so that the 4-bit counter 72 only counts from zero to seven, i.e. eight periods of the counting frequency are registered.

Depending on whether an input D has a state L or a state H of a signal is applied, the frequency divider circuit 53 divides the clock frequency of 8.866 MHz by eight or by six. This is done in the following way: The outputs Q and Q of the 4-bit binary counter 72 are at the inputs of a NAND gate 73, the output Q at the input of an inverter 74. The outputs of the NAND gate 73 and the inverter 74 are connected to the inputs of a further NAND gate 75 connected.

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R.No. 1385

This logical link appears at the output of the NAND gate for the decimal numbers zero to two the state L, for the decimal numbers three to seven the state H. As will be shown, the 4-bit binary counter is used 72 is reset when dividing by six by the state corresponding to the decimal number six. Thus, at the output of the NAND gate 75 for the decimal numbers zero to two of the state L and for the decimal numbers three to five ddr state H on. This means, that the counting frequency of 8.866 MHz, divided by six, is present. It is fed to an input of a NAND gate 76.

At the counter output Q, which is known to have the state L from zero to three and has the state H from four to seven, the counting frequency of 8.866 MHz, divided by eight, can be tapped directly, and they is fed to an input of a NAND gate 77.

The counter outputs Q and Q are still at the inputs of a

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NAND gate 78, which is followed by an inverter 79, the output of which is connected to the first reset input R _{0 of} the 4-bit binary counter 72.

The input D of the circuit is connected to one input of a NAND gate and connected to an input of a NAND gate 82 via an inverter 81. The output of the NAND gate 75 is through an inverter 83, respectively connected to a second input of the NAND gates' 80 and 82. The outputs of the NAND gates 80 and 82 are at the inputs of a bistable Flip-flop made up of NAND gates 84 and 85. The output of the NAND gate 84 is connected to an input of the NAND gate 76 and to the second RucksteH input R "of the 4-bit binary counter 72 connected.

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R.No. 1385

The output of the NAND gate 85 is at an input of the NAND gate

After describing the circuit, the functionality of the Frequency divider circuit 53 will be explained. It is assumed that at input D and thus at an input of NAND gate 80 the state L is present. This causes a state H at the output of the NAND gate 80 regardless of the state of the other input.

The state L at input D causes a state H because of the inverter 81 at the first input of the NAND gate 82. Since the state L prevails at the output of the NAND gate from zero to two and the state H from three to seven, are because of the inverter 83 at the second inputs of the NAND gates 80 and 82 from zero to two the state H and from three to seven the state L.

It is assumed that the output of the NAND gate 85 has the state H, so that this state is also at one input of the NAND gate. The output of the second NAND gate 84 of the flip-flop then has the State L so that NAND gate 76 is disabled. In this case, the status H is at its output.

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R.No. 1385

Thus the one at the first input of the NAND gate 77 gets through eight divided counting frequency via a NAND gate 86, the inputs of which are connected to the outputs of the NAND gates 76 and 77, in the second Frequency doubler circuit 54, and it is continuously divided by eight in the frequency divider circuit 53.

The case is now considered in which the circuit input D and thus one input of the NAND gate 80 assumes the state H. Since the second input of the NAND gate 80 has the state H, the state L appears at the output, which in turn the bistable flip-flop toggles so that the state H occurs at the output of the NAND gate 84, while the output of the NAND gate 85 has the state L assumes and the NAND gate 77 blocks.

There are now both at an input of the NAND gate 76 and at the second reset input R "the states H, so that the other The signal lying at the input of the NAND gate 76 reaches the second frequency doubler circuit 54 via the NAND gate 86. By the logical Linking the 4-bit counter 72 with the NAND gate 78 and the inverter the first reset input takes R. state H if and only if both the counter output Q and the counter output Q have the status H

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owns; this is the case with the decimal number six. Since the reset inputs R and R _{2 are} internally linked by an AND element, in the present case the 4-bit binary counter 72 is reset at the decimal number six, and the counting frequency of 8.866 MHz, divided by six, enters the second frequency doubler circuit 54.

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R.No. 1385

A renewed appearance of the state L at input D causes a switchover the division ratio to eight.

The division ratio is only allowed in the frequency divider circuit 53 can be changed if it is guaranteed that the period after keying has a duration specified by the division ratio. this is always the case when the counter is in the zero position.

Since the second frequency doubler circuit 54 is identical to the first 52 does not need to be discussed in more detail. Its output is connected to the counting input Ä 'of a second 4-bit binary counter 87 in the frequency converter 55 connected.

j The two frequency doubler circuits 52, 54 are used because Four times the clock frequency of a color carrier crystal is required for the design of the present circuit.

Since the output Q. of the 4-bit binary counter 87 is connected to the second counting input B, the counter can count from zero to fifteen. The outputs Q ₁ and Q_ are connected to the inputs of a NAND gate 88, the output of which is connected via an inverter 89 to the reset inputs R_., R_ "

j is connected. This logical connection creates the 4-bit binary counter

; in the case of the binary number HLHL, which, as is well known, corresponds to the decimal number ten, i
reset.

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R.No. 1385

The outputs Q, Q, Q and Q are connected via logic gates 90 to 108, which consist of NAND and NOR gates, to resistors R. to R_ connected in parallel. The resistors R ₁ to R ₁ . are on the other hand on a connecting line 109 to the output stage 56. Between a voltage source U of 5 V in this example and the connecting line is a further resistor R i. Due to the type of wiring, the logic elements 90 to 108 act like a sequence switch, which, with the frequency of the clock signal at the counter input A, sets one of the resistors R. to R_.

switches through.

By wiring the 4-bit binary counter 87 with NOR and NAND gates, where the outputs for the lowest counter reading and for the highest counter reading at the inputs of the NOR circuit upstream of the resistor R or NAND gates, the outputs for the second lowest count and for the second highest count at the inputs of the resistor The circuit works like an up / down counter that counts from zero to four, whereby the counter position four is evaluated twice.

For example, if the resistor R. is switched through, the following applies to the voltage on the connecting line 109 U ₁ / IL, = R, / R, + R ₁ . In the next counting stage

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if R _{n is switched} through and U „/ U_ = R./R.+R _o applies. In the fifth counting stage / ZdZd /

(Counter reading four) R _{c is switched} through and U _r / IL = R_ / R, + R_ applies. In

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the sixth counting stage R is also switched through, in the seventh R, and in the tenth row

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R.No. 1385

The resistors R. to R ₁ . and R _fi are dimensioned so that the voltages U. (i = I ... 5) up to U ₁ . increase and then decrease again to U, so that a rising and falling staircase shape is created, the envelope curve of the two staircases representing half a period of a sinusoid. A step-shaped voltage is thus present at the output of the converter 55, the envelope curve representing positive half-waves of a sinusoidal oscillation. An already sine-like signal with a frequency divided down by a factor of 10 is thus obtained from a purely digital signal at the output of the second frequency doubler 54.

Because of the use of purely ohmic resistors in the resistor network of the converter 55, the circuit has an aperiodic behavior, so that no transients when keying from one frequency f to one

second f occur,
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The output signal fed via the connecting line 109 to the output stage 56 of the converter 55 is amplified in two transistors 110, 111 connected as emitter followers and then connected to a center tap of the primary winding Output transformer. The primary winding consists of two winding halves 112, 113. In this exemplary embodiment, each of the winding halves 112, 113 has twenty turns.

A parallel circle lies parallel to the two winding halves 112, 113 from a resistor 114 and a capacitor 115. The winding half 112 is via an output transistor of a power driver 116, the winding half 113 via an output transistor of a second power driver switched to ground. The two power drivers 116, 117 belong to a digital component of the type 49700 (see Siemens data book 1974/75, Volume I, Digital Circuits MOS, page 289), which consists of two AND power

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PLI / Schneider-st / t.ex - 21 - 8 April 1975

R.No. 1385

drivers 116, 117 and two NAND gates 118, 119 each with two inputs consists.

At one input each of the NAND gates 118, 119 this is at the command input C present signal that was fed to NAND gate 65. The output signal of a flip-flop 120 is at the second input of the NAND gate 119, the input of which is connected to the output of the NAND gate 88 in the converter 55. As already explained, there is 88 at the output of the NAND gate a square-wave signal with a frequency that is divided by a factor of ten compared to that of the signal present at the counter input A of the 4-bit binary counter 87 is. In one period of the frequency lying at the output of the NAND gate 88 and thus at the input of the flip-flop 120, there is exactly one half-period the step-shaped voltage fed via the connecting line 109 to the output stage 56. As a result, there are two half-periods of the staircase Voltage in one period of the square wave signal at the output of flip-flop 120.

The signal at the command input C in this exemplary embodiment has the Meaning State H = "transmitter on" and correspondingly state L = "transmitter off".

A state H is assumed, which is therefore at one input each

the NAND elements 118, 119 are present. Has the square wave at output i
; of the flip-flop 120 also has a state H, then this causes a state L at the output of the NAND element 119 and thus at the second input of the NAND element 118. This results in a state H at the output of the NAND element in the power driver 117 and the Output transistor becomes conductive. Likewise j results in a state H at the output of the NAND element 118 and thus a state L at the output of the NAND element in the power driver 116, so that its output transistor is blocked. A half-wave at the center tap between the

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PLI / Schneider-st / tex - 22 - 8.4.1975

R.No. 1385

step-shaped voltage applied to both winding halves 112, 113 thus causes a current that flows through winding half 113 against
Mass flows.

During the subsequent half-cycle the stair-shaped voltage has the square wave at the output of the flip-flop 120 has the state L, which now corresponds to the power driver 116 in an analogous manner The output transistor opens and the output transistor belonging to the power driver 117 opens locks. During this half-cycle of the stepped voltage, a current flows through the winding half 112 to ground.

With the help of the winding halves 112, 113, the control via the flip-flop 120 and the digital component of the 49700 type, the step-shaped
Voltage with an envelope of positive half waves transformed into a voltage with a sinusoidal envelope.

Due to the self-capacitance of the output transformer and the parallel connection the resistor 114 and the capacitor 115 are used to smooth the staircase-shaped Voltage reached so that a pure sine wave for transmission got.

The selected type of control of the output transformer with the flip-flop 120 and the digital module of the 49700 type also ensures that with a state L at the command input C, ie with a state
"Transmitter off" both transistors in the power drivers 116, 117 are blocked, so that losses due to currents flowing away are prevented.

In the present output stage, which works as a push-pull output stage, comes you only need one analog amplifier part.

- 23 -

609843/0981

Claims (17)

BLAUPUNKT-WERKE GMBH ",,. L ^ h" =. * .. *, "**" <*. *, *. * "PLI / Schneider-st / tex - 23 - 8 April 1975 R.No. 1385 claims 1. Method for generating and inductively transmitting FM signals in an electronic route guidance system, with an oscillator circuit, a converter and an output stage are used, characterized in that obtained with the aid of the oscillator circuit (51) Digital signals with at least two frequencies are fed to the converter (55) that in the converter (55) by means of logic modules (87 to 108) and a resistor network (R to R,) from a DC voltage a step-shaped periodic voltage is obtained in which the envelope curve of half-periods is described by a sine value function and whose frequency depends on the frequency of the supplied digital signals that the step-shaped periodic voltage is an output transformer the output stage (56) is fed and that the output transformer emits a signal which has an envelope curve, which is described by a sine function. 2. The method according to claim 1, characterized in that the output transformer given signal is given the shape of a sinusoidal curve. 3. The method according to claims 1 and 2, characterized in that the stepped periodic voltage in the transducer (55) given a shape where the envelope consists of a sinusoid. - 24 - 609843/0961 - 2 5 1 5 6 R BLAUPUNKT-WERKE GMBH »>. _ut ^ PLI / Schneider-st / tex - 24 - 8.4.1975 R.No. 1385 4. The method according to claim 1, characterized in that the step-shaped periodic voltage in the transducer (55) is given a shape consisting of a sine curve. 5. The method according to claim 1, characterized in that from one clock frequency generated in the oscillator circuit (51) in a frequency divider circuit placed between the oscillator circuit (51) and converter (55) (53) Digital signals with at least two frequencies are obtained that the frequencies have a defined division ratio and that the digital signals are fed to the converter (55). 6. The method according to claim 5, characterized in that by a external control signal in the frequency divider circuit (53) from a digital signal with an upper frequency to a digital signal with a lower frequency is keyed. 7. The method according to claim 1, characterized in that with a external command in the output stage (56) controls when a signal is emitted from the output transformer. 8. A circuit for carrying out the method, in which an oscillator circuit has a frequency divider circuit - a converter and an output stage are connected downstream, characterized in that the converter (55) contains a counter (87) which has digital components (90 to 108) with resistors connected in parallel (R. to R _1. ) are connected in such a way that - 25 - 6 0 9 % '■ 3 / η Q Π 1 25156RQ BLAUPUNKT-WERKE GMBH ,. hu:, ».;« * ***** »**. * » PLl / Schneider-st / tex - 25 - 8.4.1975 R.No. 1385 that with the help of a constant voltage applied to a resistor (R,) voltage at a first output of the converter (55) a step-shaped periodic voltage is generated whose envelope consists of positive half-sine waves and whose frequency depends on the clock frequency of the counter (87) that the step-shaped periodic voltage via a coupling amplifier circuit (110, 111) a Output transformer is supplied and that it generates a sinusoidal current by means of a control circuit and a low-pass filter (114, 115) in the output transformer. 9. A circuit according to claim 8, characterized in that the primary side of the output transformer from two winding halves (112, 113) exists, between which the step-shaped periodic voltage is applied, that between the winding halves (112, 113) and ground driver stages (116, 117) are connected, which are controlled in such a way that for the duration of a first half cycle of the step-shaped voltage a current flows through the first winding half (112) and for the During the subsequent half cycle, a current flows through the second winding half (113). 10. A circuit according to claim 9, characterized in that the driver stages (116, 117) consist of AND power drivers. 11. Circuit according to claims 9 and 10, characterized in that the driver stages (116, 117) are each preceded by a NAND gate (118, 119) is that a second output of the converter (55), which is a digital signal with a period equal to a half period of the stair-shaped voltage leads, connected to a flip-flop (120) - 26 - 609843/0961 BLAUPUNKT-WERKE GMBH 31 hudum «* ** · **» * »*, *. a » PLI / Schneider-st / tex -26- 8.4.1975 R.No. 1385 whose output is connected to one input each of the NAND gates (118, 119) is applied, while a second input of the NAND gate (119) with a Command input (C) is connected and the output of the NAND gate (119) is applied to a second input of the NAND gate (118). 12. A circuit according to claim 9, characterized in that in parallel to the winding halves (112, 113) a low-pass filter from a resistor (114) and a capacitor (115). 13. A circuit according to claim 8, characterized in that the coupling amplifier circuit consists of transistors (110, 111) connected as emitter followers. 14. A circuit according to claim 8, characterized in that the frequency divider circuit (53) a counter (72), digital components (73 to 83, 86) and a bistable flip-flop (84, 85), which in the way are switched that a control input (D) is keyed from one division ratio to another. 15. A circuit according to claim 8, characterized in that between the oscillator circuit (51) and frequency divider circuit (53) a frequency doubler (52) is switched. 16. A circuit according to claim 15, characterized in that between Frequency divider circuit (53) and converter (55) a second frequency doubler (54) is connected. - 27 - 609843/0961 BLAUPUNKT-WERKE GMBH ₁₂ PLl / Schneider-st / tex -27- 8.4.1975 R.No. 1385 17. Circuit according to claim 15 or 16, characterized in that the input of the frequency doubler (52) on the one hand via an inverter (66) and a first capacitor (70) with a first Input of a NOR element (68), on the other hand via a second capacitor (67) with a second input of the NOR element (68) is connected that the first capacitor a first resistor (71) connected to ground and the second capacitor (67) second resistor (69) connected to ground are connected downstream and that the output of the NOR element (68) is the output of the Frequency doubler (52) forms. 6 0 9 B I, 3/0 9 G 1 Blank page