DE2451729C2 - Circuit arrangement for suppressing higher-frequency interfering oscillations in an interfering sinusoidal signal oscillation train - Google Patents

Description

35

The invention relates to a circuit arrangement for suppressing higher-frequency interfering vibrations in a noisy signal oscillation train in which only the signal components are passed on, which are above and below specified threshold values. The digital output signal thus obtained is in can be processed further with a digital frequency discriminator. The predominant disturbance oscillation is here a smoking disorder into consideration.

The invention is particularly advantageous in a stationary or mobile Doppler retroreflective device the radar, laser or infrared technology can be used, preferably in a proximity or distance detonator of a grenade operating according to the Doppler method or 'packets. namely with digital signal processing for upstream connection to the digital Doppler frequency measuring device.

With modern electronic ignition systems of the explosive charge of projectiles or rockets, this is Ignition criterion mostly no longer from the intensity of the received signal, but from its frequency curve derived. By backmixing with the current transmission frequency, a useful signal is obtained, its Frequency /) v for all Doppler methods of the current one Approach speed between the detonator and the target is proportional and with FM radar method that Distance between the detonator and the target (ground).

The required frequency measuring device must be capable

a) Determine the current useful frequency in a short time and quickly follow changes in frequency.

b) to be able to process a large frequency ratio fsmaJfsmm,

c) Detect signal cancellations caused by interference phenomena without delay and

d) Avoid incorrect measurements if the useful signal / interference signal ratio is poor.

Since narrow-band processes are only limited in this regard due to their inertia (search and tracking devices) are usable, there is usually only one broadband - especially from an economic point of view working circuit arrangement in question. To control the actual frequency discriminator (e.g. frequency counting circuit, frequency or phase comparison circuit) the Nutisignal must be in a signal processing arrangement converted into a suitable digital signal.

In the known circuit arrangements used for this Zv / eC , this is done by comparing the instantaneous values of the useful signal with predetermined reference voltages, e.g. B. with the help of Schmitt triggers or voltage comparators.

From DE-OS 21 13 236 such circuit arrangements are known in which an amplifier is operated with negative feedback to determine the reduction in the inclination polarity of an input signal. Occurring higher-frequency disturbing oscillations often cause multiple evaluations of changes in the inclination polarity of an input signal, i.e. simulate a higher useful frequency, especially when the voltage values of the input signal are in the vicinity of the switch-on level V 1 or switch-off level V 2 of the circuit.

The Schmitt trigger mentioned in it also has Tietze-Cchenk, as in "Semiconductor Circuit Technology". 1971 edition, pages 415 and 416 known the disadvantage that its circuit hysteresis reduces the feedback In the .Schmitt trigger influenced in such a way that when a necessary. Reduction of the switching hysteresis reduces the feedback will deteriorate in the Schmitt trigger, which then has the consequence that it no longer works bistable.

These circuits disadvantageously require a large spacing in order to function properly between the useful signal and the interference signal, so that the higher-frequency noise components superimposed on the useful signal cannot simulate a higher usable frequency.

The invention is based on the object of creating a circuit arrangement which has a higher frequency Interfering signal oscillations in an interfering signal oscillation train suppressed, so that a multiple evaluation of the half-waves of the signal oscillation train prevented, and which delivers a digital output signal that is largely free of interference from a digital Frequency discriminator can be processed further.

The essential features of the invention are the patent claim 1, their advantageous embodiments, Developments and variants are the subclaims removable. The invention is illustrated in the following description of the drawings, in which Circuit diagrams and signal curves of advantageous circuit arrangements are shown, explained in more detail.

Fig. 1 circuit example of an analog / digital converter with monitoring circuit,

Fig. 2 voltage diagrams of the output signals

from the analog / digital converter and monitoring circuit as well as the digital output signal of the signal oscillation train,

F i g. 3 variant of the in F i g. 1 circuit example shown,

Fig. 4 voltage diagrams of the output signals of the comparator K and the D flip-flop.

F i g. 1 shows a circuit arrangement according to the invention with an analog / digital converter (R 0 to R 6, Ki, K 2, / C3), which preferably contains two voltage comparators K 1 and K 2 on the input side, which check whether an input voltage Ue ( Signal oscillation train with superimposed disturbance oscillation) exceeds a positive reference voltage + Ur or falls below a negative reference voltage - Ur . In addition, a monitoring circuit SP is provided which alternately blocks K 1 or K 2 during a half cycle of the input signal. This arrangement prevents a half of U- from being evaluated several times as a result of the superimposed noise level.

A memory should preferably be used for this purpose, in particular a D flip-flop, the data input of which has the output Q and the state of which is switched by the trailing edge of the output pulses Ua (after inversion by IC2) at the clock input Tum. Like IC2 , / C3 is an inverter amplifier.

F i g. 2 shows the voltage diagrams necessary to understand the circuit. It's from above applied downwards:

a) The input signal Ue, with the broadband noise signal corresponding to the entire evaluation band superimposed on the useful signal, as well as the reference voltages (+ Ur and - Ur), which are advantageously subjected to a hysteresis by R 5 or R 6.

b) The output signal A from K 1, which indicates the positive half-waves of the useful signal.

c) The output signal B from K 2, which indicates the negative half-waves of the useful signal.

d) The output signal Ua, the pulse sequence of which corresponds to twice the useful frequency. Occurring signal cancellations are indicated immediately by the lack of positive impulses

e) The memory signal Q for blocking the comparator K 2 (K 2 blocked if Q = 0).

g) The memory signal Q for blocking the comparator K \ (Ki blocked if Q = 0).

is conductive. Is turned 52, so the reference voltage U +, the input voltage appears at the non-inverting comparator input in place of UE now enters a positive half-wave of sufficient amplitude a, so U +> U is Ua-L About ie the feedback IC and R 5 is this shift by reducing supported by U— . If the input voltage Ue falls below the reduced threshold, U. \ changes to state 0. This process causes the memory to be switched over via the clock input T, ie S2 blocks and S 1 becomes conductive. The next negative half-wave is now discriminated in an analogous manner.

Fig. 4 shows the voltage diagrams associated with Fig. 3:

a) The input signal Ue. a noise voltage is superimposed on the useful signal. as well as the reference voltages U + and U-.

n..c A " _r ", nmc; »nnl //. Hoccar. D.il ^ nU «« lon / J »n.

corresponds to useful frequencies.

c) The memory signal Q (Q = 1 means 5 I conductive).

d) The memory signal Q (Q = 1 means 5 2 conducting).

A variant of the? Circuit according to FIG. 1 is in FIG. 3 shown. It only requires a voltage comparator, but two analog switches for switching of the input signal. The mode of operation of this version is as follows:

At the two inputs of the comparator K are - assuming 51 and 52 are blocked - the reference voltages U- and U +, which are obtained from the relatively high resistance chain Ri to R 4 and symmetrically around an artificial zero point (the one through the capacitor C. is blocked in terms of alternating voltage) are arranged. Through R 5 and R 6, the thresholds U— and U + can also be influenced by the output Ua (hysteresis). Because U-> U + , Ua = 0.

The memory SP (in accordance with FIG. 3, preferably again a D flip-flop) has the effect that its output signals Q and Q each have a switch f51 or 52)

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60 2 sheets of drawings

Claims (15)

Patent claims: 1. Circuit arrangement for suppressing higher-frequency interfering oscillations In an interference-prone sinusoidal signal oscillation train, which can be further processed largely without interference by a digital frequency discriminator, which can be connected upstream of the digital Doppler frequency measuring device in a Doppler reflectance measuring device with digital signal processing. characterized in that when using at least one analog / digital converter, the analog / digital converter (RO to R 6, KU K2, IC3) checks the instantaneous voltage of the noisy signal oscillation train to determine whether it corresponds to the zero axis of the sine wave of the signal oscillation train symmetrically lying positive and negative reference voltage values (U +, U-), ie reference voltages of the same amount but with different signs but- or below that its outputs each deliver a pulse signal if the amount of the instantaneous voltage value of the signal oscillation train is greater than the positive or negative reference voltage, and that a Monitoring circuit (SP) is provided. which controls the Analog / Digitai-Wanüler (R 0 to R 6, K 1, K 2. IC3) in such a way that after each positive or negative reference voltage exceedance of the signal oscillation train, only the next negative or positive reference voltage exceedance is recorded, so that a multiple evaluation of the half-waves of the swiusförK.igen signal oscillation train is prevented as a result of the Ctörschwingungsüberlagungsüberlagungs. 2. Circuit arrangement according to claim 1, characterized in that the analog / digital converter (R 0 to Rb.Ki.K2, IC 3) contains two comparators (Ki, K 2) on the input side, with the help of which it can be determined whether the current one Voltage of the noisy signal oscillation train to the zero axis of the sine wave of the signal oscillation train exceeds or falls below the positive and negative reference voltage (U +. U—) , and that one comparator (K 1) is sensitive to the positive amplitude values and the other comparator (K 2) is sensitive to the negative amplitude values of the signal oscillation train, or vice versa. 3. Circuit arrangement according to claim 2, characterized in that the two signal outputs of the comparators are connected to the two inputs of an output circuit (ICX) which only deliver no output signal when the same, non-zero input signals are present at their two inputs. 4. Circuit arrangement according to claim 3, characterized in that the monitoring circuit (SP) uses the output signals generated by the output circuit (ICi) as control signals. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that the input of the monitoring circuit (SP) is connected via an inverter amplifier (IC2) to the output of the circuit arrangement and that the switching input of one comparator (K 1) with one output (Q) of the monitoring circuit, the switching input of the other comparator (K 2) is connected to the other output (Q) of the monitoring circuit. 6. Circuit arrangement according to one of claims 3 to 5, characterized in that the output circuit (ICt) is designed in the form of a NAND gate 7. Circuit arrangement according to one of claims 1 and 4 to 6, characterized in that the monitoring circuit (SP) is designed to prevent multiple evaluation in the form of a D-FIip-flop that its T input to the output of the inverter amplifier (IC 2 ) is connected. that the data input D of the D flip-flop is directly connected to its emen output (Q) and the switching input of one comparator (K. 1) and the other output (Q) is connected to the switching input of the other comparator (K 2) . 8. Circuit arrangement according to one of claims 2 to 7, characterized in that by feedback (R 5, IC 3, RG) a hysteresis acts in the voltage comparison that the one comparator (K i) after falling below the amplitude of the signal oscillation train below the with a reference voltage afflicted with hysteresis (+ Ur) by which one output signal (Q = 0) of the monitoring circuit (SP) is blocked and that the other comparator (K 2) after the amplitude of the signal oscillation train has exceeded the reference voltage afflicted with hysteresis (- Ur ) is blocked by the other output signal (Q - O) of the monitoring circuit (FIG. 2). 9. Circuit arrangement according to one of claims 2 to 8, characterized in that the comparators are designed for voltage comparison in the form of two differential amplifiers. 10. Circuit arrangement according to one of claims 2 to 9, characterized in that for generating the reference voltage throw; a high-resistance source (+ Ub. Ri to R 4) is connected upstream of the inputs of the comparators. 11. Circuit arrangement according to claim 1, characterized in that the analog / digital converter contains a single voltage comparator (K) , the two signal inputs of which are supplied with the sinusoidal signal oscillation train and with the aid of which it can be determined whether the instantaneous voltage of the noisy signal oscillation train has predetermined reference voltage values (U + , U-) exceeds or falls below that a switching device with two switches (Si, S2) for alternately locking and unlocking the input channels of the voltage comparator (K) carrying the signal oscillation lines are provided in one or the same following half-wave of the sinusoidal signal oscillation line, that the positive reference voltage value (U +) is applied to one input of the voltage comparator (K) and the negative reference voltage value (U- ) is applied to the other input, that the input of the voltage comparator to which the positive reference voltage (U +) is applied can be unlocked by the one switch (52) for signal oscillation trains with positive amplitude or locked with negative amplitude,
that the input of the voltage comparator to which the negative reference voltage (U-) is applied is through the other switch (Si) for signal oscillation movement trains with negative amplitude can be unlocked or locked with positive amplitude,
that a high-resistance source (+ Ub. Ri to /? 4. C) is connected upstream of the inputs of the voltage comparator (K) to generate the reference voltage values and that the output of the voltage comparator (K) via an inverter amplifier (IC) of the monitoring circuit and its output Q are connected to the control input of a switch (S 1) assigned to it and its output Q to the control input of the other switch (S 2) assigned to it (Fig. 3). 12. Circuit arrangement according to claim 11, characterized in that the two switches are designed in the form of two analog switches (Si. S 2). 13. Circuit arrangement according to one of claims 1 to 4 and 11 to 12, characterized in that the monitoring circuit (SP) contains a memory. 14. Circuit arrangement according to claim 13, characterized in that the memory rii is designed in the form of a D flip-flop (SP) . 15. Circuit arrangement according to one of claims 11 to 14, characterized in that an inverter amplifier (IC) and a resistor (R 5) in the inverting comparator input containing feedback circuit are in series with one another and for hys'eresebildung during voltage comparison. a resistor (R 6) is located in the feedback circuit containing the non-inverting comparator input.