DE2004934B2 - MEMORY ARRANGEMENT WITH CIRCUITS FOR ERROR DETECTION AND ERROR CORRECTION - Google Patents

Description

The invention relates to a memory arrangement with settings for error detection and correction r information stored in memory Division of the memory into groups of memory modules which store data or error correction code bits, according to the preamble of claim 1.

Memory arrangements, in particular matrix memories made from ferrite cores or from integrated semiconductor circuits, are used for modern data processing systems in an automatic manufacturing process generated. Although very high demands are made on the devices for the production of these memory matrices in particular

changes are made, it is unavoidable that in a matrix memory with several million bits Storage capacity, d. H. several million individual components, faulty or damaged memory locations appear. It is also possible that after a long time Operation of such a memory different Memory cells fail. However, since a memory for a data processing system must be error-free, are For the individual memory types, various options have become known to repair the damaged areas to be determined and marked within the memory or by other non-defective memory locations to replace. In addition, it is known to detect errors within a stored word when storing and automatically by using an error correction correct correction codes to a limited extent.

In addition, in the case of matrix memories with magnetic cores, attempts have been made to replace the defective memory locations that were used in the Production of more word lines -nit memory cells provided than actually intended for the desired Storage capacity are required. If an error now occurs at a memory location in a word line, then the entire word line is made ineffective and one of the redundant lines in its place controlled. This type of compensation for defective memory cells within a matrix memory hai However, the major disadvantage that entire cell groups in the memory are redundant, which increases the price of the memory increase significantly. In addition, it is not possible with such an organic memory, individual Identify and correct defective bit positions on several word lines, as only a certain one limited number of redundant word lines Can be built in at the price of such a one Organized storage can still be kept within acceptable limits.

By the American patent specification 32 22 653 isi a circuit arrangement became known by an additional error marking bit marked " Storage locations within the memory are automatically replaced via a control network Memory call z. B. a defective SpeicherstelU is controlled, then a comparison circuit causes an alternative address, which designates a free, non-defective memory cell, to be automatically assigned is controlled. However, this additional control network is technically extremely complicated and expensive and also requires relative to compensate for errors much time.

Furthermore, the older patent (DT-Pi 15 24 788) provides a circuit arrangement for Kompensa tion of defective storage cells, which is characterized by the fact that each

Data block is assigned to an overflow block in the memory that controls and counts de As is known, memory blocks are sent by a block address that contains the respective header address

contains and a block counter, which counts the transmitted data blocks, as well as a word address counter, which determines the word cells within a block by advancing by one and a word counter, that counts the transmitted words, and that a switch is made in the presence of a defective word cell A signal is generated within a block that the word counter is switched on at this point in time prevents the word counter from reaching the nominal value after calling all word cells in a block stands and the transfer of the remaining words of one via existing, known addressing circuits Controls data block in an assigned overflow block. In addition, according to the earlier patent (DT-PS 15 24 791) another suggestion is that each word line of the main memory in a plurality Sub-word register is subdivided so that the read-only memory designed as an additional address memory has a Error identifier memory contains that the read-only memory via an error correction circuit and via Control circuits are connected to a spare memory which, like the main memory, is in sub-word registers is subdivided, which can be controlled instead of the defective sub-word register in the main memory that needs to be replaced.

The circuit complexity for the two last-mentioned circuit arrangements, which can only compensate for a defective memory cell in a memory, is extremely high in relation to the compensation possibility. In addition, it was proposed by the earlier patent (DT-PD 15 49 468) that the memory arrangement consists of m + π sub-memories as basic working memories, where m + n corresponds to the number of bits of a word which, in addition to the m information bits, also contains π bits for error detection and correction includes that each sub-memory has an address register, control circuits and a data register and that the inputs of all address registers are connected in parallel to the outputs of an address register fed by the central processing unit of the data processing system, so that the same memory location in all m + n sub-memories is addressed will.

As a result, it is possible that so many partial memories fail at the same time without interruption how errors can be corrected by the error correction circuit, however, this correction possibility made possible by a very high technical effort, which results from the assignment of a own address register, own control circuit and own data register for each Partial memory results.

The invention is based on the object of a memory arrangement with error detection and automatic To create error correction, a variable automatic by using error correction code bits Enables error correction of the memory words read with little technical effort.

The solution to the problem according to the invention consists in the characterizing part of claim 1.

The advantage of the memory arrangement according to the invention with circuits for error detection and Error correction consists in the fact that its capacity can easily be increased many times over without that a special technical effort or a change in the storage concept is required. the high flexibility of the automatic error correction system is also achieved with a very low technical effort compared to the known correction systems for memory and to the known Compensation circuits achieved for bad bits within a memory word.

The invention will now be described with reference to FIGS. 1 to 3 illustrated embodiments described in more detail.

The in F i g. The data memory shown in FIG. 1 is in two storage parts or two storage units 1 and 2 divided up. The capacity of the memory unit 1 is 8000 (8 k) memory words of 72 each in this example ίο bits, and the storage capacity of the storage unit 2 is 8000 (8 k) memory words with 22 bits each.

The memory unit 1 contains 72 memory modules, each of which can store 8 k bits. The storage unit

1 is also organized in such a way that each memory module contains 1 bit of each memory word stored in the memory unit 1. Each memory word contains 64 data bits and 8 error correction code bits to enable individual error correction. The memory unit 2 consists of 22 memory modules, each memory module in turn storing 1 bit of each word. Each word in the memory unit 2 consists of 16 data bits and 6 error correction code bits.
The two memory units 1 and are addressed

2 in byte representation. The addresses of the bytes in each word are contiguous, or in other words, they are contiguous. The memory address register 3, which is 32 bits in size, stores the address of the byte that at memory output 4 is required. Bits 16 through 28 of memory address register 3 are used to To gain access to a memory word of memory unit 1 and bits 18 to 30 are used to To gain access to a memory word of the memory part 2 Bits 16 and 17 are both zero if the Memory unit 2 is addressed. Bits 29,30 and 31

from memory address register 3 are used to select 1 of 8 bytes when the word is from the Memory unit 1 is fetched and bit 31 is used to select one of two bytes when the word is to be fetched from the memory unit 2.

The higher-order bits 0 to 15 in the memory address register 3 select either the memory unit 1 or the Storage unit 2 off. The highest combination of bits

0 to 15 in the memory address register select the memory unit 2, Not all of the possible combinations of bits 0 to 15 in the present exemplary embodiment are used, are required to select memory units 1 and 2, so that the remaining Combinations can be used with a desired increase in storage capacity.

The 72 bits of each word that came out of the memory section

1 is fetched via the input gate element 5 into the 72-bit register 6 entered. The bits stored in the register 6 are then switched to a downstream Error correction circuit 7 given, which can detect double errors and the positions in register 6 can show in which there are individual errors. When a single error occurs, the error correction circuit shows 7 shows the position of the individual error in register 6 by generating an error bit display that shows a corresponding

According to the 64 reverse circuits, each of the 64 Unikehrschaltungen 8 leaves the output of a Pass position in the register unchanged to the corresponding gate circuit 9 if there is no error. However, if there is an error in one position, then

the output signal is inverted in the corresponding position, whereby the error is corrected. The word read out remains in register 6 until another word passes input gate element 5. That

> 5

20th

Output gate element 9 gives the required byte to output 4 under control of the byte selection bits such as previously described. The check bit used for the selected byte is generated by a check generator 10 which is connected to the error correction circuit 7 in a conventional manner. If a 22-bit word comes from memory unit 2, data bits 0 to 15 are assigned to positions 0 to 15 of register 6 and the correction code bits 16 to 21 are given to the positions 64 to 69 of the register 6. Any of the not used Data bit positions 16 to 63 are set to zero and the error correction code positions 70 and 71 of the Registers 6 are set to one by the gate elements 5 at which there are no input signals. The value to which an unused position in register 6 is set is determined by the used Error correction code determined. The operation then proceeds as if the word were transferred from memory unit 1 is read, except that only bits 0 to 15 of register 6 contain meaningful data.

If a double error is detected by the error correction circuit 7, it becomes an uncorrectable one Error signal generated. This signal can cause access to the corresponding memory cell is repeated again. In order to increase the working speed, a byte can be placed on the memory output be placed before the error correction circuit 7 has completed the error detection. When a correctable error is detected, a correctable error signal can be generated which causes It is possible that the corresponding byte on the memory output is ignored and that the corrected Byte that is then transferred to the memory output is accepted.

Eight error correction code bytes can be used for each word stored in memory unit 2 be used. This requires two additional modules for the memory unit 2. Figure 2 shows one Data memory similar to that of FIG. 1, with the exception that the memory unit 2 consists of 39 modules, 32 for data storage and 7 for the error correction code bits. The storage capacity of the Speieber unit 2 is 32 k bytes of data. The mode of operation is the same as in connection with the one in FIG. 1 memory shown, with the exception that when the word in register 6 from memory unit 2 has been fetched, the register 6 contains four meaningful data bytes. Two byte selection bits 30 and 31 are required to select one of four bytes for transmission to the output.

In Fig. 3, a smaller storage unit is shown in FIG of the two bits of each word in storage units 1 and 2 are stored in the same module. the Storage unit 1 contains 36 modules, each of which stores 8 k-bits to store 4 k-words of 72 bits (64 data and 8 error correction code bits), d. H. it is a data storage capacity of 32 k-bytes available. The memory unit 2 consists of 20 identical modules to store 4 k words of 40 bits (32 data and 8 error correction code bits). This corresponds to a data byte capacity of 16 k. the Operation of the memory according to FIG. 3 is the same as the operation of the memories shown in FIGS. 1 and 2 with the exception that in this example the output is two bytes and bits 30 and 31 or bit 31 can be used to put the required two bytes on the output. A double error correction must be made if the memory with a defective or removed module should continue to work.

Increased storage capacity can be achieved by adding an additional storage unit or several additional storage units corresponding to storage unit 1 in FIGS. 1 and 3 used will. Small increases in memory can be achieved by a unit such as B. the Storage unit 2, the capacity of which is a binary fraction of the capacity of storage unit 1. Has z. B. the Storage unit 1 has a storage capacity of 64 k bytes, then the storage unit 2 should have a storage capacity of 8 k, 16 k or 32 k bytes. Bits 0 to 15 in memory address register 3 are used to select the partial memory unit.

For this purpose 3 sheets of drawings

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Claims (8)

Patent claims: 1.Memory arrangement with circuits for error detection and error correction of the information stored in the memory by dividing the memory into groups of memory modules which store data or error correction code bits, which the error correction circuit has at the memory output, which if necessary contains erroneous bits that are in an output register, corrected, characterized in that the memory is divided into a first part (1) for storing words from / πι data bits and n \ error correction code bits and a second part (2) for storing words from the data bits and / J ₂ error correction bits, wherein m \ larger / 712 and n \ larger / 72, and a common memory address register (3) is assigned to the two memory elements (1 and 2). 2. Memory arrangement according to claim 1, characterized in that the memory is made up of a plurality of modules, each module having one bit from each word in one of the parts of memory saves. 3. Memory arrangement according to claim 1, characterized in that the memory has a number Memory modules, each module containing two bits of each of the words in one of the parts of Includes memory. 4. Memory arrangement according to claims 1 to 3, characterized in that the with the Error correction circuit (7) connected output register (6) of the memory with an inverting circuit (8) for displaying the error position or the Inversion of the incorrect position or positions is connected. 5. A memory arrangement according to claim 4, characterized in that when a word is entered with / 772 + / J ₂ bit positions from the memory part (2) into the output register (6) input gate elements (5) are arranged, which in every unused bit position of the output register ( 6) enters a predetermined bit, which is dependent on the error correction code, for carrying out the error correction. 6. Memory arrangement according to claims 1 to 5, characterized in that the most significant bits in the memory address register (3) for Control of access to a memory word are used and the lower-digit bits are the byte or the Control bytes of the read word that is to be transferred to the output. 7. Memory arrangement according to claims 1 to 6, characterized in that the memory contains a number of memory positions in which words of / Π2 data bits and / 72 error correction code bits are stored and in which the value of m is different in each position 8. Memory arrangement according to one of claims 1 to 7, characterized in that / 772 is a binary fraction of m \