DE1254703B - Memory for determining a connection path via a switching matrix in telecommunications, in particular in telephone switching systems - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

H04m

H04q

German class: 21 a3 - 38

Number: 1254 703

File number: St 23596 VIII a / 21 a3

Filing date: March 31, 1965

Opening day: November 23, 1967

The invention relates to a memory for determining a connection path via a switching matrix in Telecommunications, in particular in telephone exchange systems.

It is known, the occupancy status of sections of a switching network in the cells of a memory to be held in order not to first determine the occupancy status in the switching matrix when a connection is established to have to. In a centrally controlled switching system, you can control the switching network required signals at the same time to adapt the memory content to the respective occupancy status of the switching matrix can also be used.

It is also known and very useful in terms of avoiding a second control circuit, the To divide up memory and to arrange the cells so that the addresses of the memory cells match the addresses of the sections of the route in the coupling matrix match. Are the memory cells in a multi-dimensional coordinate system arranged, then corresponds to z. B. a coordinate direction of the division of the switching matrix into several switching stages, another coordinate direction of the division into parallel switching matrices and another coordinate direction corresponds to e.g. B. the various outputs of each matrix.

It is also known to form groups and bundles in the switching network by forming corresponding Storage cell groups with lower or higher coordinates to take into account.

These known memory arrangements set a regular structure of the switching matrix and the Memory and are firmly bound to this structure.

All known memories, the cells of which can be addressed in any way, can be used for storage of the occupancy status of the switching network; those are particularly suitable for storage in which the addresses of the memory cells match the addresses of the sections of the route in the switching matrix. But with all known storage systems, a considerable amount of tax is required to search for a route to query only those cells for their content in the memory, their assigned path sections in the switching matrix can be interconnected to form a connection path. In practice, the control circuit must have another Contains an image of the possible connection paths in order to provide the required information about interconnectivity to be able to process the sections of the way.

It is the object of the invention to simplify the mentioned further image in the control circuit and So the effort in the switching matrix and memory for determining a connection path Via a switching network in telecommunications, in particular in telephone switching systems

Applicant:

Standard Elektrik Lorenz Aktiengesellschaft, Stuttgart-Zuffenhausen, Hellmuth-Hirth-Str. 42

Named as inventor:

Dipl.-Ing. Georg Becker, Gerungen; Peter Wöhr, Stuttgart-Feuerbach

to reduce the memory common control circuit.

ao The memory according to the invention solves this problem in that the connectivity of two sections of the path from an assignment between the identification of a section of the route and the memory address for the Occupancy status of the other part of the route follows, and that a switchable route through the whole Coupling matrix runs in the memory via a chain of memory cells, in each case between the identification of the one and the memory address of the following two adjacent chain links one such assignment is fulfilled. This assignment can be done at any time by a saved program without Intervention in the wiring can be changed, or can be made by a wired allocator.

It is most expedient if in the entire store with two interconnectable sections of the path the same assignment is fulfilled, because then you only need one when searching for a route in the memory Allocator. This allocator supplies the addresses of the the occupancy status of the cells storing the following sections of the route. When establishing a connection So the same mapper is used multiple times, namely once for each section of the route.

Either the intermediate lines between the coupling blocks or these Switching contacts connecting intermediate lines are considered. Both ways are only two States capable, so that in each case one bit per section is sufficient to save the occupancy status.

The memory and the allocation circuit can be approximately rectangular with magnetic cores in a known manner Hysteresis loop can be built.

709 689/70

Claims (1)

3 4 In the following, the invention is based on a leading part of the way, there is a fixed assignment, The embodiment shown in the drawings. 2 and F i g. 3 explained. The valid assignment shown in the example is: F i g. 1 shows a block diagram of the interacting circuit parts; 5 ^Χ ^ Λ ^-1 F i g. 2 shows a simple example of a coupling y = E + 2> m _x + (N-1) · a _t .
field; F i g. 3 shows the address distribution in memory for where means the switching matrix according to FIG. 2.. The four blocks in FIG. 1 represent the switching network io ^{E =} memory address for the occupancy status KN, the memory SP, the controller ST and that of ^{the first} 3 outputs of the first coupling allocator Z or the stored program. ! t ' ^z " t ¹ ~~. Via the lines Ll, Ll the address of a »= number of the coupling stage m of a memory output to be queried for its occupancy state is searched for _W1 rd, z. B. the coupling cell has the memory Sp and the characteristics of the 15th _Λ fute C the number ζ = 3.
Path piece fed to the allocator Z. The query - ¹ ^ ¹ = number of the coupling stage in which the last result is determined via line L3 of the control ST and * "» «output was e.g. communicated to the assigner Z. If the section is free, Jr output B 32 In the coupling stage B with, the allocator Z determines the memory addresses for ^the number il = 2.
the occupancy status of the further sections ao ^m f _r ⁼ ^ _T ^{nzahI of} the outputs of the coupling stage X. and gives this information over the line L4 to the ^N = number of the last determined free control. It is also sufficient if the allocator output, within its coupling block, only contains the memory address for the occupancy status ^z ; ^B · ff * J «output B 32 number JV = 2nd of the first further path segment determined. ° * = ^{number of de} \ outputs a switching block Is this directional piece is, the controller 35 checks ^de, _ ^r coupling stage ι the next possible J '= absolute memory address for the occupancy memory cells whose addresses are e.g. B. have consecutive ^{status of} the first continuing route numbers. The assignment of a connection piece. route is via the line L5 in the switching network KN This assignment can be made with known access and made in the memory SP . 30 folders or a saved program. The switching matrix according to FIG. 2 has four lead coupling stages. As in Fig. 1, the allocator receives A, B, C and D. The coupling stage A has four coupling Z each via the line L2 the required in- blocksev41, A2, A3 and A4 with four inputs each, information about the output that has just been checked, z. B. Inputs A31 to ^ 434, and three outputs each, This section of the route is considered free via line L3 Eg outputs Ä 31 to O '33. Each output of a 35 is reported, so the allocator gives the Coupling block leads to another coupling block memory address y for the occupancy status of the the coupling stage B. The three coupling blocks Bl, Bl first further path section to the control and 53 thus each have four inputs and each have ST. three outputs, e.g. outputs B '31 to B' 33. Each Let, for example, output B '32 des Output of a coupling block of the coupling stage B leads 40 coupling blocks 53 have been determined. The occupancy to another coupling block Cl, Cl or C3 the state of this part of the path is with the absolute Coupling stage C. Finally, each of the two memory addresses 35 (see FIG. 3) is stored. There are Outputs of a coupling block of coupling stage C, the following variables are known: to one of the two coupling blocks Dl, D 2 in the e · _ ι _Λ ■ _ ι · 1 _ ->_i-> _o Coupling stage D. These coupling blocks each have two 45 £ - l &, ζ - J, ζ -1 - 2, W ₁ - 12, m _% - 9, Outputs D'11, D'11 or D'21, D'22. JV = 2, a _t = 2. In the present example, _{the assigner determines the address as the route segments}
the intermediate lines considered, the m of the drawing the same reference numerals as the inputs or y = 16 + 12 + 9 + (2 - 1) · 2 = 39.
carry the outputs of the coupling blocks, as there is a 50 is reversible unambiguous assignment. This is the memory address for the occupancy In Fig. 3 is the division of the memory and the status of the first further section of the route C 21, Address distribution in the memory for the switching matrix as can be seen from FIG. 2 and F i g. 3 according to FIG. 2 specified. Each storage cell SZ can easily convince. If this stretch of the road is occupied, If there is binary information about the occupancy 55, the addresses of the following outputs can do this condition of the section of the route assigned to it. Each coupling block by simple address modification Memory cell has an absolute memory address ASA, (addition of 1) can be determined.
with which it is called and then on its content can be queried. In the presentation of the claims:
F i g. 3 is also a symbolic address SA an- 60 given that the identification of the inputs or 1st memory for centrally controlled switching the exits and thus also the sections of the route, in whose memory cells the occupancy speaks. The cell content 0 means e.g. B. that the state of the sections of the switching network is the section of the path assigned to the memory cell is free, which is stored, characterized in that Cell content 1 means z. B. that the memory cell 65 that the connectivity of two pieces of path assigned part of the route is occupied. an association between the marking Between the identification of a section and a section and the memory address (ASA) the memory address of one (e.g. the first) further for the occupancy status of the other section of the route i 254 follows, and that a switchable path through the entire switching matrix in the memory via a Chain of memory cells runs, in each case between the identification of the one and the Memory address of the following two adjacent chain links such an assignment is fulfilled. 2. Memory according to claim 1, characterized in that in the entire memory at two interconnectable sections of the road the same assignment is fulfilled. 3. Memory according to claim 1 and 2, characterized in that the assignment to be fulfilled for the entire memory is hardwired in one allocator and that this allocator after Feeding in the identifiers of a section of the route, the addresses of the occupancy status of the next Cells storing sections of the path. 4. Memory according to claim 1 and 2, characterized in that the assignment to be fulfilled is made by a stored program that can be used at any time without interfering with the wiring is changeable. 5. Memory according to claim 1 to 3, characterized in that the occupancy state to be stored of a section of the route is the occupancy status of an intermediate line. 6. Memory according to claim 1 to 3, characterized in that the occupancy state to be stored of a distance is the switch position of a switch contact. 7. Memory according to claim 1 to 3, characterized in that the memory and the allocator are constructed with magnetic cores of approximately rectangular hysteresis loops. 1 sheet of drawings 709 689/70 11.67 © Bundesdruckerei Berlin