DE1250659B - Microprogram-controlled data processing system - Google Patents

Abstract

1,061,361. Editing data. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 11, 1965 [April 6, 1964], No. 5906/65. Heading G4A. In an electronic data processing system, data characters to be edited are transferred selectively and successively under partial control of a bi-stable device from a first (" source ") storage field to a second (" pattern ") storage field initially containing control and data characters (e.g. decimal point), whereby at the conclusion of an editing operation the second field contains selected characters from the first field selectively interspersed with data characters of the second field. Bytes each have 8 bits and comprise two binary-coded decimal digits or one such and a sign (" packed " format), or one such digit plus 4 zone bits (" unpacked " format). Provision is made for interchanging the two halves of a byte in a register to simplify test on a half, testing being done generally by subtracting a constant from the number and seeing if the result is zero. The bi-stable device referred to above is a " significance trigger " which is 0 if the next " source " character is presumed non-significant and 1 if significant. The trigger is set to 1 if the " source " character is non-zero, or when a " significance start " control character is detected in the " pattern " field, and set to 0 when a " field separation " control character is detected. The characters of the " pattern " field are accessed from memory in turn. Those not control characters are retained in the " pattern " field if the "significance trigger " is at 1 but replaced by fill characters if at .0. " Field separation " control characters are replaced by fill characters. Detection of a " significance start " control character or a " digit select " control character results in the accessing of the. corresponding " source " character. If this is non-zero or if the "significance trigger " is at 1, it replaces the control character in the "pattern " field after being " unpacked " by insertion of zone bits 1111. Otherwise the control character is replaced by a fill character. The editing operation is initiated by an instruction word containing an OP code specifying either normal, editing as above or the latter plus the additional feature of storing the address in the "pattern " field of the highest significant character in the "source" field when this is detected through switching of the " significance trigger ". This facilitates later insertion of e.g. a currency symbol. The editing instruction word also specifies the number of bytes in the " pattern " field and the addresses of the highest order bytes of the " source " and " pattern " fields. These addresses are each specified by specifying a number and a register, the contents of the register being added to the number to get the address. Detection of a sign character in the " source " field sets to 1 a trigger to indicate that a sign is present, and if the sign is negative sets a further trigger to 1 to indicate this. This will cause the " significance trigger " to be set to 1. The second sign trigger and another trigger set to 1 in the presence of a non-zero " source " digit can be used to control subsequent (unspecified) operations. Reference has been directed by the Comptroller to Specification 954,801.

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

G06f

German class: 42 m3 - 9/16

Number: 1250 659

File number: J 27773 IX c / 42 m3

Filing date: March 25, 1965

Opened on: September 21, 1967

The invention relates to a microprogram-controlled data processing system with a macroinstruction containing main memory with assigned decoders and registers as well as with a Read-only memory containing micro instruction sequences and controlled by the output registers of the main memory, the macro operations with the individual via decoder and an assigned register Units of the data processing system controls.

Electronic data processing systems operate under the control of a program of macro instructions. A macro instruction defines a macro operation such as B. Add, subtract or Compare using part of the instruction called the opcode. Any macro command can be broken down into microinstructions, many of which have different macroinstructions in common are. It has been found that in multipurpose data processing systems it is more expedient to to provide a control circuit for micro-operations and for executing a macro-operation carry out the micro-operations necessary for this.

Each micro-operation is under the control of a micro-instruction which, when decoded, the necessary switching and gate signals for the data processing system to carry out the micro-operation provides. The set of microinstructions that are necessary to run a macro operation is called a microprogram. Micro instructions are in a memory with fast Access saved.

Up to now it has been customary for the macro instruction to select only the first instruction of a microprogram. The address of the subsequent microinstruction in memory was either completely replaced by the previous one Microinstruction or partly by the previous microinstruction and partly by Machine conditions determined.

In the publication by Mc Crack en. Weiss, Lee: "Programming Business Computers", pp. 171 to 174, John Wiley & Sons, Inc. New York, describes how certain information in the main program can influence the control of the sequence of subroutines. The addresses contained in the main program indicate the first command of a subprogram or the subprogram in general. The main program does not contain consecutive addresses of commands of a subprogram. The next command in a subroutine is microgram-controlled by the previous command
Data processing system

Applicant:

International Business Machines Corporation, Armonk, N.Y. (V. St. A.)

Representative:

Dipl.-Ing. H. E. Böhmer, patent attorney, Boeblingen, Sindelfinger Str. 49

Named as inventor:

Gene Myron Amdhahl, Saratoga, Calif .; Jacob Raymond Johnson,

Peter Calingaert,

Richard Paul Case, Poughkeepsie, N. Y .; Elaine Marie Boehm, Wappingers Falls, N.Y .; William Porter Hemp, Endicott, N. Y .; Charles Bertram Perkins, Jr., Endwell, N.Y .; Arthur Frederick Collins,

Jack Ellis Greene,

Albert Allan Magdall,

John Willis Rood, Vestal, N. Y .; Richard Joseph Carnevale,

Bruce Martin Updike, Endwell, N. Y .; Anthony Eugene Villante, Binghampton, N.Y .; Gerrit Anne Blaauw, Poughkeepsie, N. Y .; Helmut Weber, Vestal, N. Y. (V. St. A.)

Claimed priority:

V. St. v. America April 6, 1964 (357 372) -

possibly still determined depending on the results of a subroutine.

The invention is therefore based on the object to provide a circuit arrangement with a Minimum of control circuits and microinstruction storage space and thereby one easy-to-use and flexible instruction set as well as time savings.

The inventive solution to the problem is characterized in that areas of the microinstruction register are connected to the decoder assigned to the main memory and that further areas of the microinstruction register with an additional

709 648/155

union decoder are also connected to the operation code area of the macro instruction register is connected, wherein control signals are formed in both decoders mentioned, which the Determine the address of the next microinstruction using assigned AND circles.

In the following an embodiment of the 'invention with reference to the F i g. 1 and 2 explained will.

F i g. 1 shows the microinstruction memory and associated control devices for selecting one Microinstruction in a data processing system according to the invention;

F i g. 2 shows the flow chart of two microprograms as they are in a data processing system according to the invention can be used.

The data processing system of the exemplary embodiment consists of a large number of individual parts; only some of these parts are used in the present Invention used, and only these parts are described in detail.

The most essential of the parts of the system not involved in the invention are the main memory, which contains the macro instructions, an arithmetic and logic unit, input and output devices and register. These can all be constructed in a manner known per se.

The parts of the data processing system which are used to implement the invention contain a read-only memory 1 with fast access of any form, several registers, several decoders, logic circuits and connections between these parts. Each register consists of several bistable elements, each of which is set depending on the type of bit supplied. Each bistable element and the bit stored in it is identified by its position in the register. For example, the bistable element ZO is the first bistable element in register X that contains the bit ZO.

A status register 5 contains certain operating conditions of the machine, such as. B. Overflow. the Input signals for the operation code register G correspond to the part of the macroinstruction which the Operation to be performed in the machine determines e.g. B. Adding, comparing or exclusive-or.

The read-only memory 1 contains many microinstructions, each of which occupies a specific position in the memory and to which a specific memory address is assigned. In the illustrated embodiment, each microinstruction consists of sixty bits, and these bits are divided into several groups, so-called fields, e.g. B. divided the CN, the CH, the CL and the CF field. Each field consists of a certain number of bits. The output register of the read-only memory 1 is denoted by 5.

The register 5 consists of one hundred and twenty bistable elements, one set of elements SL-IU (odd) to SL-60-U and a second set of elements SL-IG (even) to SL-60-G. Each pair of like-numbered odd and even bistable elements, e.g. B, SL-IU and SL-IG, are connected to a bistable element of a microinstruction register (MI- G register) 7 via AND circuits 6 and an OR circuit 14. These AND circuits, which connect the odd-numbered bistable elements to the M / register 7, are marked with "SIXS ODD", while the AND circuits, which connect the even-numbered bistable elements to the M / register 7, are marked with "SIX STRAIGHT «are marked. The M / register 7 consists of sixty bistable elements. Each bistable element generates a real and a complementary output signal, which indicate the stable state in which the bistable element is. Each microinstruction consists of sixty bits and is entered into the M7 register 7 from the read-only memory 1 via the output register 5.

The bits in the microinstruction are fielded. Each field is used to indicate a specific Execute control and gate functions in the data processing system. The clarity For the sake of this, the sections of the M / register 7 are marked as well as the corresponding ones Fields of microinstruction. For example, the M / register contains a CF field with the two bits of the CF field of the microinstruction. Depending on these bits, the operand is converted into the arithmetic-logical unit of the machine entered; they cause an addition or Subtraction operation is performed.

The outputs of the two bistable elements, which represent the CF field, carry two signals, which the real and two which characterize the complementary states of the bistable elements.

The above-mentioned similar identification for the fields in the microinstruction and in the M / register is shown in FIG. 1 is also applied to the CN field, which consists of six bits, the CH field, which consists of four bits, and the CL field, which consists of three bits. The bistable elements that form the CiV field have twelve outputs CNO to CN 6 and C7V0 to C] V5. The outputs CNO to CN3 are fed to a CiV register 8 in which they are stored in bistable elements. The outputs CiV 4 and CN 5 are supplied as inputs AND circuits 9 and 10. The outputs from the CH field are fed to a Cif decoder 11. Other inputs of the C # decoder 11 are the outputs 51, S 2, 54 and S 6 from the 5 register and the outputs GO to G 6 from the G register. The outputs from the CL field are fed to a CL decoder 12. Other inputs of the CL decoder 12 are connected to the outputs 55 and 57 of the 5 register and the outputs G 5 and G 7 of the G register.

The read-only memory 1 is addressed via a decoder 2, the outputs of which have two coordinates of the Select memory 1. The inputs of the decoder 2 are connected to the outputs of the W register 4 and the Z register 3 connected.

In the present exemplary embodiment, the address of the microinstruction in read-only memory 1 should be Twelve bit number of which the PF register the four highest bit positions and the Z register 3 contains the eight lower bit positions. To the possibility the occurrence of errors as a result of incorrect operation of the electronic parts is to be avoided the system is designed in such a way that the addresses of successive microinstructions that lead to a specific Include microprograms, change them as little as possible. Successive microinstructions of a microprogram are therefore stored in consecutive addresses, and micro-

Instructions that are read out after a branch have addresses that are only in the lower Differentiate places from those in the main strand of the microprogram. It follows that while any macro operation the J-F register 4 unchanged Supplies input signals to the decoder.

The Z register 3 supplies the output signals XO to X 6 to the decoder 2, the output signal X 7 to the AND circuits “SIX ODD” and the output signal X 7 to the AND circuits “SIX EVEN”. The inputs of the X register are the four outputs of the CW register 8, the outputs of the two OR circuits 15 and 16, the output H 3 of the Ctf decoder 11 and the output Ll of the CL decoder 12. The inputs of the OR Circuits 15 and 16 are formed by the outputs Hl and H2 from the CH decoder 11 and the outputs of an AND circuit 9 and 10 each. The decoder 11 also generates a gate signal! 7-4, which is fed to the AND circuits 9 and 10.

The read-only memory 1 is word-oriented. This means that the reading lines are arranged in such a way that whole words instead of single bits are read out. In a preferred embodiment two microinstruction words are simultaneously read out into register 5 to determine the number of read lines and reduce the driver circuits.

The decoders 11 and 12 each contain a number of AND circuits, one of which is for one certain combination of inputs is switched on. An activated AND circuit only generates an output signal such as B. in the CL decoder 12 or more than one output signal such. B. in that C // decoder 11. Such decoders are known per se and are not to be described in detail here will.

To perform an operation, a macro instruction word is read from main memory and stored in Control registers of the data processing system stored. The opcode that is part of the Forms macro command is stored in the G register. By means of known circuits that in Fig. 1, the opcode is decoded to the address of the first microinstruction of the microprogram that is to execute the macroinstruction. It is best to use the System to train so that the same start address of a microprogram sequence by different Operation codes can be generated. The higher digits of the address are in the W register 4 and the lower digits placed in X register 3. For the sake of clarity are the input lines in FIG. 1 not shown.

The bits A0 to X 6 of the Z register 3 and the content of the PF register 4 are fed to the address decoder 2 and are decoded there in order to apply current to a single word read line. Two microinstruction words with sixty bits are read out into the register 5, one into the bistable elements SL-IU to SL-60-U and the other into the bistable elements SL-IG to 5L-60-G. Depending on the bit X 7, one of the microinstruction words is brought into the M / register 7. If the bistable circuit X1 stores a 1-bit, then Xl is high, and if it stores a signal Xl , it is low. The AND circuits “SIX ODD” are opened and the content of the bistable elements SL-IU to SL-60-U is brought into the M / register 7. If the bistable circuit X 7 stores a 0, then the output signal is at low potential and the output signal X 7 is at high potential. The AND circuits “SIX STRAIGHT” are opened and the content of the bistable elements SL-IG to 5L-60-G is brought into the M / register 7.

The output signals of the bistable elements, of which the M / register 7 consists, are sent to all parts of the data processing system in order to control the execution of the first microinstruction read from the memory 1. In addition, the microinstruction provides signals which control the selection of the next microinstruction in the microprogram. Until then, the CN field supplies signals CiVO to CN 3 to the CiV register 8 and signals CN 4 and CN 5 to the AND circuits 9 and 10; the bistable elements of the Ci / field supply output signals in real and complementary form to the C77 decoder 11, and the bistable elements of the CL field supply signals in real and complementary form to the CL decoder 12.

The signals CH, UH and CL, OZ determine which factors are decisive for the selection of the next microinstruction. The next microinstruction can be selected by the current microinstruction in the M / register 7 without any conditions. In this case the signals Ci? and CH one or more AND circuits in the Ci? decoder 11, and the signals CL and ~ CL switch the AND circuit in the CL decoder 12 on. The output signals of the decoder are completely determined in this case and are not influenced by the contents of the S and G registers.

Let it now be assumed that the next microinstruction is determined under the influence of the contents of the S and G registers. In this case, only some of the signals CH, CH and CL, CTL switch on one or more AND circuits in their assigned decoder. The remaining inputs for the partially activated AND circuits come from bistable elements of the S and / or G register. If the remaining inputs should be connected to the bistable elements 54 and G 5, for example, the selection of the AND circuits selected by the signals CH, UH and CL, UL and thus the outputs of the decoders depends on the states of these bistable elements. Such a state is referred to in the following as "selection by 54 and G 5".

The CH decoder 11 supplies output signals at the outputs H1 to H 3 and E / 4. This latter output signal is fed to the AND circuits 9 and 10 and causes the transmission of the bits CiV 4 and CN 5 from the CiV field of the M / register 7 to the bistable elements X 4 and X 5 of the X register 3 via the OR Circuits 15 and 16. The outputs Hl and Hl of the C / 7 decoder 11 together with the outputs of the AND circuits 9 and 10 form the inputs of the OR circuits 15 and 16, which set the bistable elements X 4 and X. 5 determine. The I / 4 signal thus makes it possible either to enter the signals Hl and H 2 directly into the bistable elements X 4 and XZ of the Z register 3 or to carry out an OR link between Hl and CiV4 and Hl and CNS. That means when the t / 4 signal is present and either

Hl or CN 4 is at high potential, then the bistable circuit X 4 is brought into a stable state, which represents a binary 1. The same applies to the outputs H 2 and CTV 5 and the bistable circuit X5. The output signal H3 is fed directly to the bistable circuit 6 of the Z register 3.

The CL decoder 12 generates only a single output signal Ll. This is fed directly to the bistable circuit X 7 of the X register 3. The bistable circuit X 7 generates output signals X 7 and Xl which, as described above, control the selection of one or the two microinstructions that are read from the read-only memory. The output signal L1 may be dependent on the signals CL, CL or the bits SS and 57 of the 5 register or the bits G 5 and G 7 of the G register or any combination of these signals.

So far, a circuit for selecting the address of a microinstruction has been described as follows works that the selection depends on the operation code of the macro instruction being executed is contained in the G register.

As an example of the operation of the invention, it will now be described which micro-operations through the macro operations "fixed point addition" and "fixed point subtraction" with special consideration of the differences between the microprograms of these two operations.

The electronic data processing system which contains the invention has an arithmetic and logic function Unit that performs the subtraction through a complementary addition. Two operands will be brought from main memory or other registers to first and second operand registers. The two operands are then sent simultaneously in parallel through the adder and the result is placed in the first operand register. When the bistable circuit 50 of the status or 5 register is on (this is generally represented by the expression 50 = 1) then the second The operand is complemented before it goes into the adder, and a "carry-on" signal is put into the Brought the lowest digit of the adder, in which a carry-indicating bistable element is switched on will. The result placed in the first operand register represents the difference between the two operands When the bistable circuit 50 is off (50 = 0), both operands are given to the adder supplied not complemented; the bistable circuit storing the carry remains or becomes turned off so that no "carry-on" signal is generated for the lowest digit of the adder. In in this case the result placed in the first operand register is the sum of the two operands.

The operation code for the command "Fixed point addition" is 000 110 10, while that for the "Fixed point Subtraction «00011011 is. These differ only in the last bit, namely G 7.

F i g. Figure 2 shows a flow diagram of these two operations.

Both operation codes lead to the same first microinstruction, which is read from memory 1 into MI register 7. The fields CN, CH and CL of the first microinstruction select the next microinstruction in the manner described above without any condition, and in the same way each microinstruction of the program section A (see FIG. 2) selects the next microinstruction without condition. The first microinstruction in the microprogram, which is the same for “fixed point addition” and “fixed point subtraction”, causes the operands to be transferred to the operand register.

The last microinstruction of program section A requests selection of the next microinstruction on the basis of the G7 bit. That means like above

ίο on the basis of FIG. 1 it was explained that the AND circuits of the Cfi decoder 11, to which signals from the bistable circuit G 7 of the operational register are fed, are only partially prepared by the CH and Ώϊ output signals from the CTY field of the WZ register 7. Which of these AND circuits are fully prepared depends on the state of the bistable circuit G 7. The outputs of the C / Z decoder 11 and thus the outputs of the Z register 3 and the address of the next microinstruction thus depend on bit G 7 of the operation code, ie whether the macroinstruction is an addition or subtraction instruction. This situation is illustrated in FIG. 2 indicated by the diamond, which is the usual symbol for a branch point in a flowchart.

If the bit G 7 is zero, a microinstruction is placed in the M / register 7, which switches the bistable circuit 50 off. This microinstruction will unconditionally select a second microinstruction, which will switch off the bistable circuit for indicating a carry, which has been described above. Thereafter, the first microinstruction of program section B of the microprogram is selected unconditionally.

If the bit G7 is a one, a microinstruction is placed in the M / register 7, which turns the bistable circuit 50 on. This microinstruction will select a second microinstruction without any conditions, which will switch on the bistable circuit to indicate a carry. Thereafter, the first microinstruction of program section B of the microprogram is selected unconditionally. The program section B is a set of microinstructions, each of which is selected unconditionally by the preceding microinstructions. These microinstructions cause the operands to pass through the adders and the result to be placed in the operand register. If the program joins the yes branch of the microprogram

(see Fig. 2), the program section B develops the sum of the two operands, while if the program follows the no branch, the program section determines the difference between the two operands.

The example described above shows that fewer microinstructions are required to execute a macroinstruction are needed if the operation code of the macro instruction is constantly changing the development of the Microprogram acts. The bistable circuit would be 50 and the bistable circuit for displaying the transmitter directly through the operation code of the If the macro command has been controlled, this would have resulted in an inflexible function which at least works on one character of the operation code, and that would be the number of possible macro operations been smaller than in the arrangement according to the invention. By having an opcode bit on the microprogram to be executed at the moment

acts, a flexible instruction set is made available to the programmer, which has a minimum required in control circuits and in microinstruction storage space.

Claims (3)

5 claims: 1. Data processing system with a main memory containing macro instructions with assigned decoders and registers and with a read-only memory containing micro instruction sequences and controlled by the output registers of the main memory, which controls the micro-operations in the individual units of the data processing system via decoders and an associated register, characterized in that areas ( CH and CH) of the microinstruction register (7) are connected to the decoder (11) assigned to the main memory and that further areas (CL and 'CL) of the microinstruction register (7) are connected to an additional decoder (12) which is also connected to the operation code area (G, 5) of the macro command register is connected, with control signals (U 4 and Ll) being formed in both decoders mentioned, which determine the address of the next micro command via assigned AND circles (9, 10 and 6). 2. Data processing system according to claim 1, characterized in that the output lines (H 1, Hl, 773) of the decoder (11) for the macro commands via OR circuits (15 and 16) with areas of address registers (3) of the read-only memory (1) are connected and that the output (L 1) of the additional decoder (12) is connected to a stage of said address register whose output lines (x7 and 3c 7) for selecting an instruction from the microinstruction register (7) with AND and OR circuits (6 or 14), which are between the output register (5) of the read-only memory (1) and the microinstruction register (7) are connected. 3. Data processing system according to claims 1 and 2, characterized in that the Circuit for determining the addresses of the microinstructions consists of decoders, which except a part of the preceding microinstruction the operation code of the macroinstruction and, if applicable Conditions identifying bits are supplied. 1 sheet of drawings 709 648/155 9. 67 © Bunclcsdruckerei Berlin