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DE10345447A1 - Verfahren zum Herstellen eines Halbleiter-Bauteils - Google Patents

Verfahren zum Herstellen eines Halbleiter-Bauteils Download PDF

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Publication number
DE10345447A1
DE10345447A1 DE10345447A DE10345447A DE10345447A1 DE 10345447 A1 DE10345447 A1 DE 10345447A1 DE 10345447 A DE10345447 A DE 10345447A DE 10345447 A DE10345447 A DE 10345447A DE 10345447 A1 DE10345447 A1 DE 10345447A1
Authority
DE
Germany
Prior art keywords
substrate
etchant
trimming
production
comprises forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345447A
Other languages
English (en)
Other versions
DE10345447B4 (de
Inventor
Franz Hirler
Markus Zundel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345447A priority Critical patent/DE10345447B4/de
Priority to US10/955,392 priority patent/US20050118816A1/en
Publication of DE10345447A1 publication Critical patent/DE10345447A1/de
Application granted granted Critical
Publication of DE10345447B4 publication Critical patent/DE10345447B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

Ein Verfahren zum Herstellen eines Halbleiter-Leistungsbauelements (10) weist die folgenden Schritte auf: DOLLAR A - Ausbilden einer Halbleiterstruktur (2) in/auf einem Substrat (1), wobei auf Höhe einer Zieldicke des Halbleiter-Leistungsbauelements (10) durch die Halbleiterstruktur (2) in der Halbleiterstruktur (2) bzw. in dem Substrat (1) ein als Stoppschicht dienender Halbleiterbereich (2) ausgebildet wird, dessen Dotierungskonzentration gegenüber der des Substrats (1) erhöht/vermindert ist und/oder dessen Dotierart gegenüber der des Substrats (1) invertiert ist, und DOLLAR A - Ausdünnen wenigstens eines Teils des Substrats (1) auf die Zieldicke unter Verwendung eines Ätzmittels, dessen Ätzrate abhängig von der Konzentration und/oder der Art der Dotierung ist, wobei das Ätzmittel so gewählt ist, dass der Ausdünnprozess durch den als Stoppschicht dienenden Halbleiterbereich gestoppt bzw. verlangsamt wird.
DE10345447A 2003-09-30 2003-09-30 Verfahren zum Herstellen eines Halbleiter-Bauteils Expired - Fee Related DE10345447B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10345447A DE10345447B4 (de) 2003-09-30 2003-09-30 Verfahren zum Herstellen eines Halbleiter-Bauteils
US10/955,392 US20050118816A1 (en) 2003-09-30 2004-09-30 Method for fabricating a semiconductor component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345447A DE10345447B4 (de) 2003-09-30 2003-09-30 Verfahren zum Herstellen eines Halbleiter-Bauteils

Publications (2)

Publication Number Publication Date
DE10345447A1 true DE10345447A1 (de) 2005-05-04
DE10345447B4 DE10345447B4 (de) 2007-04-26

Family

ID=34399087

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345447A Expired - Fee Related DE10345447B4 (de) 2003-09-30 2003-09-30 Verfahren zum Herstellen eines Halbleiter-Bauteils

Country Status (2)

Country Link
US (1) US20050118816A1 (de)
DE (1) DE10345447B4 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7923330B2 (en) 2007-10-02 2011-04-12 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device
DE112017003587B4 (de) 2016-07-15 2024-05-29 Rohm Co., Ltd. Halbleitervorrichtung und verfahren zur herstellung einer halbleitervorrichtung

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281359B2 (en) 2012-08-20 2016-03-08 Infineon Technologies Ag Semiconductor device comprising contact trenches
US9196568B2 (en) 2013-10-01 2015-11-24 Infineon Technologies Ag Arrangement and method for manufacturing the same
DE102018129594A1 (de) * 2018-11-23 2020-05-28 Infineon Technologies Ag Teilweises entfernen eines halbleiterwafers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4016472C2 (de) * 1990-05-22 1992-04-09 Robert Bosch Gmbh, 7000 Stuttgart, De
DE4228795C2 (de) * 1992-08-29 2003-07-31 Bosch Gmbh Robert Drehratensensor und Verfahren zur Herstellung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347149A (en) * 1989-11-29 1994-09-13 Texas Instruments Incorporated Integrated circuit and method
US5338416A (en) * 1993-02-05 1994-08-16 Massachusetts Institute Of Technology Electrochemical etching process
US7132321B2 (en) * 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4016472C2 (de) * 1990-05-22 1992-04-09 Robert Bosch Gmbh, 7000 Stuttgart, De
DE4228795C2 (de) * 1992-08-29 2003-07-31 Bosch Gmbh Robert Drehratensensor und Verfahren zur Herstellung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7923330B2 (en) 2007-10-02 2011-04-12 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device
DE102008050298B4 (de) * 2007-10-02 2012-09-06 Infineon Technologies Austria Ag Halbleiterbauelement und Verfahren zu seiner Herstellung
DE112017003587B4 (de) 2016-07-15 2024-05-29 Rohm Co., Ltd. Halbleitervorrichtung und verfahren zur herstellung einer halbleitervorrichtung

Also Published As

Publication number Publication date
DE10345447B4 (de) 2007-04-26
US20050118816A1 (en) 2005-06-02

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OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee