DE10247819B4 - Method for producing an image sensor arrangement - Google Patents

Abstract

Method for producing an image sensor arrangement, in which • a plurality of sensor chips are formed on and / or in a substrate, each of which has a plurality of sensor fields; A trench having a depth that is greater than the depth of the sensor fields in the substrate is formed around each of the sensor chips using a lithography method and using an etching method, a separate etched trench around each sensor chip is formed and etching is avoided in areas between different etching trenches; • a respective sensor chip is separated by removing material from the rear side of the substrate to a depth which is at least equal to the difference between the thickness of the substrate and the depth of the trench; • the sensor chips for forming the sensor arrangement are assembled in a form-fitting manner.

Description

The invention relates to a method for producing an image sensor arrangement.

The technology of the digital camera is becoming increasingly important.

However, it is difficult to realize an image sensor arrangement for a digital camera with a dimension as in the case of a 35 mm camera (for example, 24 mm × 36 mm) or as in the case of an even larger camera. With a digital camera with a sensor surface of 24 mm × 36 mm, the advantage would be that a standard 35 mm camera and its optical lens system can also be used for the digital camera. In such a scenario, in a system change from an analog camera to a digital camera, essentially only the rear wall of the camera would have to be modified to replace a conventional film with an image sensor array of a suitable dimension.

One problem with semiconductor fabricated manufacturing of an image sensor array integrated in a semiconductor substrate is that when using a photo stepper as used in many lithographic processes, the maximum field of view is limited (e.g., 19.6 mm x 26.0 mm) a maximum diagonal of 31.1 mm). Thus, only one image field of a limited dimension can be realized. Therefore, forming an image sensor array having a size of 24 mm × 36 mm with only one exposure operation during lithography is not possible.

Furthermore, an image sensor with a field of view of 24 mm × 36 mm is so large that due to an unavoidable defect density during the semiconductor processing an achievable yield of functional image sensor arrangements is low and thus incur high costs. In other words, in a large-scale one-piece image sensor array, a sufficient yield can not be expected, so that manufacturing such an image sensor array is expensive.

In order to address this problem, different approaches are taken according to the prior art.

On the one hand, an attempt is made to adapt the image optics of a conventional camera to a small sensor arrangement with highly integrated sensor fields. However, this generally leads to a deterioration of the picture quality. Furthermore, it is necessary and expensive to adapt the image optics of the camera to the semiconductor-technologically produced small sensor arrangement.

Furthermore, an attempt is made to produce a sensor arrangement with a size that is only just below the image field size of the photo-stepper. In this case, the standard optics of a camera can be used, but expensive and only consuming manufacturable optical correction lenses are required. Furthermore, the exposure parameters of the camera must be set by means of an extension factor. For example, replacing a 36 mm × 24 mm 35 mm film with a 28.7 mm × 19.1 mm digital film will result in approximately the same amount of light on the smaller digital film (due to the effect of the correction optics or a changed distance between lens and film) the larger 35mm film. Therefore, when using corrective lenses, it is often necessary to make a complicated adjustment of the exposure of the digital film. In this context we speak of an extension factor.

Another possibility for producing a sufficiently large sensor arrangement is to produce a large sensor arrangement by means of multiple exposure of several areas of a wafer during the processing of the semiconductor substrate. However, this manufacturing method is expensive due to the complicated multiple exposure and the large chip size of a one-piece sensor assembly and the associated yield problems. A complete wafer exposure is unsuitable for a single sensor cell because of the required texture fineness.

DE 199 62 763 C2 discloses a method of dicing a wafer in which a trench is formed between a plurality of circuit patterns. By means of back material removal from the wafer, the circuit structures are subsequently separated. Furthermore, circuit chips can be combined into circuit modules, whereby chips are assembled from different base materials and manufacturing technologies.

EP 1 187 221 A2 discloses to form a plurality of chips in a wafer and to differentiate one another by means of a V-shaped trench. Subsequently, the chips are separated from the wafer by means of splitting, sawing, cutting or dicing into chips. A plurality of singulated chips may be assembled to form a one-dimensional sensor array.

DE 199 33 472 A1 discloses a network for signal processing with a plurality of chips.

DE 198 40 508 A1 discloses a method for dicing semiconductor devices from a wafer.

The invention is based on the problem of producing a sufficiently large image sensor arrangement with a large number of sensor fields, which has improved quality and reduced production costs.

The problem is solved by a method for producing an image sensor arrangement with the features according to the independent claim.

In the method according to the invention for producing an image sensor arrangement, a plurality of sensor chips are formed on and / or in a substrate, each of which has a plurality of sensor arrays. Further, around each of the sensor chips, using a lithography process and using an etching process, a trench is formed having a depth greater than the depth of the sensor arrays in the substrate, with a separate etch trench around each sensor chip is formed and in areas between different etch trenches an etching is avoided. A respective sensor chip is singulated by removing from the back side of the substrate material of a depth that is at least equal to the difference between the thickness of the substrate and the depth of the trench. Finally, the sensor chips are assembled to form the sensor assembly.

A basic idea of the invention is that a sensor arrangement is composed of a plurality of sensor chips, wherein the dimensioning of a sensor chip is defined using a trench surrounding it and thus by means of a lithographic method. This has the advantage that the distance of a sensor field from an edge of the sensor chip assigned to it can be kept very small (on the order of μm). In addition, this distance can be set with a very high accuracy. The latter is, in turn, a consequence of the usability of a lithographically definable boundary of a sensor chip instead of a mechanically defined boundary (eg separation by means of sawing the wafer).

The depth of the trenches is selected such that the back-side removal of material of the substrate for separating the sensor chips z. B. integrated circuit components of the sensor chip (sensor fields, control circuit components, etc.) are protected from destruction. This avoids that when removing material of the substrate such material is removed, which contains functional components of the sensor chip. In the event that further integrated circuit components are formed underneath the sensor arrays in the substrate, the depth of the trenches is selected so that, when removing material from the back side of the substrate, these additional circuit components are protected from damage. Thus, the depth of the trenches is preferably at least as large as the thickness of the sensor arrays in the substrate plus the thickness of optional additional circuit components. In other words, the trench is preferably formed with a depth that is greater than the depth of the sensor chip in the substrate, i. H. of the functionally or circuitically active region in the substrate. In this area of the sensor chip also drive or readout lines for the individual sensor fields etc. can be accommodated as well as preprocessing electronics (eg amplifiers), etc.

Because of the spatially well-defined limitation of the sensor fields on each of the sensor chips, a plurality of sensor chips can be assembled in such a way that a disturbance in the regular sequence of sensor detectable disturbances (eg, optically) occurs at a boundary region between two adjacent sensor chips. Chips is avoided. The image sensor arrangement (eg for a camera) thus avoids disruptive lines at interfaces between adjacent sensor chips, which otherwise may occur due to interruption of the regular sequence of sensor fields in boundary regions between adjacent sensor chips.

Furthermore, by introducing trenches for defining a sensor chip, a geometrically ideal edge is obtained at the edge of the sensor chip, so that adjacent sensor chips can be joined together accurately.

Clearly, the sensor arrangement is not made of a one-piece component (for example a large piece of silicon), but rather of a plurality of small sensor chips (eg image sensors), each of which can have the same functionality. This is accomplished by etching a sufficiently deep trench around the sensor chip after processing the sensor chips (ie, forming the sensor arrays, etc.). This trench is preferably slightly deeper than the later final thickness of the singulated sensor chips. Due to the alignment accuracy of a semiconductor lithographic process, a sensor array arranged at one edge of a sensor chip can be placed very tightly, typically 1 μm and less, around a sensor chip. Inside the etched trench, the wafer still has enough stability to perform Process Control Monitoring (PCM) and a functionality test. After a related Evaluating the wafer, the wafer is thinned back to its target thickness by abrading material (eg, mechanically abraded) from the backside of the wafer. As a result, a singulation of the sensor chips is realized, wherein each sensor chip has a size defined to a dimension of 1 μm and less.

It is also easily possible to assign the sensor fields on the sensor chip a precisely defined distance to an edge of a sensor chip (again up to an accuracy of 1 μm and less). This accuracy makes it possible to assemble a sensor array (a large image sensor) from a plurality of composite sensor chips (for example, small image sensors) by means of a mounting.

For the application of a digital camera disturbing lines at boundary regions between adjacent sensor chips usually do not occur at a typical image pixel size of 5 microns to 10 microns.

According to the invention, several small components are assembled in order to achieve a higher yield in sensor production. Thereby, it is possible for a digital camera (eg, with the dimension of a 35mm camera) to make an image sensor component avoiding the above-described problems known from the prior art. By reducing the tolerances due to the definition of sensor chips by means of trench etching, it is achieved that the composite sensor arrays have approximately the same resolution as a one-component sensor arrangement.

By means of uniformly cut sensor chips, which preferably all have the same size, edges of ideal geometry and thus very good mating surfaces are obtained. Using a uniform mask further reduces the tolerance. Then, the only limiting criterion is mask resolution, which is significantly better than conventional tolerance in singulating a substrate.

When sawing throwers for separating the chips of the thrower, the manufacturing tolerance is in the range of 50 microns and more. If one were to arrange sensor chips next to one another under these circumstances, this would mean that the points of contact of the individual small image sensors in the digital image would be resolved. In other words, one would not achieve the same functionality in terms of the visual perception of a viewer of an image as in a large-scale image sensor. In particular, disturbing lines would occur in border areas.

By means of the method according to the invention, the manufacturing tolerance is so greatly reduced that multiple sensor chips can be strung together and together achieve the same optical functionality as a one-piece sensor arrangement. Thus, larger and due to the Madularität individual small building blocks and cheaper image sensors can be made than in the prior art.

Preferred developments of the invention will become apparent from the dependent claims.

Preferably, the sensor chips are substantially form-fitting to sammengesetzt. Due to the significantly improved accuracy of fit of the sensor chips, the sensor array is therefore applicable in all areas where a spatially defined assembly of different components with high spatial accuracy is required.

The trench can be formed in such a way that a distance of a sensor field arranged at an edge of a sensor chip from an edge is not substantially greater than an extent of the sensor field. In this case, it is ensured that disruptive lines are avoided in boundary regions between adjacent sensor chips due to a disturbance of the symmetrical arrangement of sensor fields.

The trench is formed using a lithography process. A resolution in the range of micrometers (for example 2 μm to 3 μm) and above can be achieved with a lithography method. Since the sensor fields often have a pixel dimension of 5 .mu.m to 10 .mu.m, it can be ensured that disturbances, distortions or lines at interfaces of adjacent sensor chips are avoided.

The trench is further formed using an etching process. It is preferable to use as an etching method an anisotropic etching method in order to achieve a sufficiently steep edge drop at the edge of a sensor chip, whereby the accuracy of fit in assembling adjacent chips is further increased. The etching process may be a dry etching process. Alternatively, a wet etching method may be used. In general, care must be taken in the etching process that the undercutting, d. H. the isotropic etching component, is kept sufficiently low to ensure a form-fitting juxtaposition of adjacent sensor chips. Sputter etching or reactive ion etching (RIE) is particularly preferred as an etching process.

The material of the substrate may be prepared using a chemical-mechanical polishing Process (CMP process) or an etching process are removed. Alternatively, material can be removed using a laser.

Different sensor chips can be made substantially the same size. In particular, it is possible to form different sensor chips using a common lithography method, that is to say a uniform projector. However, it is also possible to manufacture the different sensor chips of the sensor arrangement from different wafers.

The trench can be formed in such a way that a distance of a sensor field arranged at an edge of a sensor chip from the edge is preferably at most 3 μm, more preferably at most 1 μm.

In the following, the sensor arrangement according to the invention will be described in more detail. Embodiments of the method for producing the sensor arrangement also apply to the sensor arrangement and vice versa.

At least one of the sensor arrays may be a CCD sensor array.

A charge coupled device (CCD) array is illustratively an array of CCD elements, i. H. integrated devices for converting an optical image into an electric charge image by photogenerating electric charges and then converting the charge image into a sequential electrical signal using CCD shift registers.

The sensor field can also be an infrared sensor field, for example for a thermal imaging camera. A thermal imaging camera is based on such infrared sensors, which are sensitive to infrared light. Particularly suitable are CCDs or diodes made of the material HgCdTe (mercury-cadmium telluride). When using a thermal imaging camera, it may be advantageous to cool the sensor arrangement below ambient temperature in order to minimize the infrared radiation radiated by the sensor arrangement itself.

Preferably, each of the sensor chips has a multiplexer area and a pad pad area, the sensor chips being assembled such that the multiplexer areas and the pad areas are arranged to extend along at least part of the edge of the sensor array. In this case, the sensor arrangement is illustratively formed from a central section in which the sensor fields of the sensor chips are arranged. This center area is surrounded by multiplexers for selectively addressing the sensor arrays. By means of the connection pads, the electrical signals of the sensor fields of a processing electronics arranged in the surroundings can be provided.

It should also be noted that a "seal ring" as often formed along a perimeter of a chip for protection purposes may be eliminated in the sensor chips of the invention. If such an edge seal is to be formed, then its thickness is preferably to be selected (smaller than 3 μm) such that the spatial sequence of the sensor fields is not perceptibly influenced in boundary regions between adjacent sensor chips.

It should be noted that the substrate may be made of any material. In particular, the substrate may be a silicon wafer. Alternatively, the substrate may be a glass substrate, a ceramic substrate, etc.

An embodiment of the invention and a comparative example is shown in the figures and will be explained in more detail below.

Show it:

1A a top view of a sensor chip,

1B an enlarged section of the in 1A shown sensor chips,

2A a wafer having a plurality of sensor chips formed thereon during a method of manufacturing a sensor device according to a comparative example,

2 B a cross-sectional view along in 2A shown section line I-I ',

3A a plan view of a wafer with a plurality of sensor chips at a different time during the method for producing a sensor arrangement according to the comparative example,

3B a cross-sectional view along in 3A shown section line II-II ',

4A a wafer with a plurality of sensor chips at a further time during the method for manufacturing a sensor arrangement according to the comparative example,

4B a cross-sectional view along in 4A shown section line III-III ',

5 a sensor arrangement according to the comparative example,

6 a wafer having a plurality of sensor chips formed thereon during a method of manufacturing a sensor array according to an embodiment of the invention.

The same or similar components in different figures are provided with the same reference numerals.

In the following, reference is made to 1A a sensor chip 100 one described.

The sensor chip 100 has a sensor area 101 with a plurality of sensor fields (not shown in FIG 1A ) located in the sensor area 101 of the sensor chip 100 are arranged in a matrix. Furthermore, the sensor chip contains 100 a multiplexer area 102 for selectively controlling the sensor fields of the sensor chip 100 , In an edge area of the sensor chip is a pad pad area 103 provided on the electrical signals of the sensor fields for external processing can be provided.

In the following, reference is made to 1B a border section 104 of the sensor chip 100 described in an enlarged view.

In 1B are a plurality of sensor fields 110 shown on the sensor area 101 of the sensor chip 100 are arranged in a matrix. The on the according to 1B right edge arranged sensor fields 110 are provided from this right edge at a distance of 1 micron. Each of the sensor fields 110 is formed by means of a semiconductor technology processing, so that the accuracy of the spatial location of the sensor fields 110 is defined by means of a lithographic process.

In 2A is a silicon warper 200 shown on the total of twelve sensor chips 100 are trained, each of which like the in 1A shown sensor chip 100 is constructed.

In 2 B is a cross-sectional view of the thrower 200 shown along a section line II '. Deviating from 2A is in 2 B in preparation of a trench etching process to be carried out photoresist 210 on the surface of the thrower 200 deposited (not shown in 2A ) and patterned by a photolithographic exposure. This causes the sensor chips 100 with photoresist 210 whereas the entire intermediate areas (scribe-frame areas) between adjacent sensor chips 100 from a covering with photoresist 210 are free.

In the following, reference is made to 3A the Warfer 200 described in a state after the according to 2 B with structured photoresist 210 covered arrangement has been subjected to a sputter etching process.

Following this, the photoresist 210 freed from the arrangement, causing the Warfer 200 in the 3A shown state is obtained. As in 3A are shown between adjacent sensor chips 100 trenches 300 educated.

As in the 3B shown cross-sectional view along the section line II-II 'from 3A are shown, due to the sufficiently deep trench etching different sensor chips 100 assigned chip areas 310 created by a spacer area 311 are separated from each other. The width of the trench 300 is 30 microns according to the described comparative example. The depth of the trench 300 is 300 microns according to the described comparative example.

In the following, reference is made to 4A . 4B described as the one with trenches 300 provided wafers 200 in a variety of separate sensor chips 100 is isolated.

For this purpose, using a CMP method ("chemical mechanical polishing") on the back 401 of the silicon wafer 200 Material removed until the material of the spacers 311 is completely removed, so the different sensor chips 100 be mechanically separated from each other.

This is from the in 4B shown cross-sectional view along the section line III-III 'from 4A seen. After removing material from the silicon wafer 300 from the back 401 thus become separate sensor chips 100 receive.

As in 4B As shown, the adjacent interfaces of adjacent sensor chips are parallel to each other with sufficient accuracy so that the sensor chips 100 fit together accurately. In particular, it should be noted that due to the use of a lithography process to define the trenches 300 These are adjustable with an accuracy of 1 micron and less.

In the following, reference is made to 5 a sensor arrangement 500 described according to a comparative example.

To the in 5 shown sensor arrangement 500 to receive six of the 4A shown isolated sensor chips 100 precisely fitting and form-fitting joined, whereby in a central area, the sensor areas 101 a large overall sensor area 501 form according to 5 from above and below from a total multiplexer area 502 is surrounded. According to 5 on and below the overall multiplexer area 502 is a total pad area 503 intended.

The size of the sensor areas 101 are chosen so that in the assembled state according to 5 the total sensor area 501 has a dimension of 36mm x 24mm and thus can be operated using standard optics of a conventional 35mm camera. Because the singulation of the sensor chips 100 By trench etching and thus realized using a lithography process, it is ensured that even in border regions of adjacent sensor areas 101 the sensor arrangement 500 a sufficiently defined spatial sequence of the sensor fields adjacent thereto is realized, so that disturbing lines are avoided even in border areas.

In the following, reference is made to 6 a silicon warper 600 during a method of manufacturing a sensor arrangement according to an embodiment of the invention.

The processing of the thrower 600 differs in a significant point from the processing of the thrower 200 referring to 2A to 4B is described. The silicon warper 600 has a plurality of sensor chips formed thereon 100 on, each of which has a sensor area 101 , a multiplexer area 102 and a pad pad area 103 contains. In contrast to the above with respect to 2A to 4B described processing is the spatial definition of the exact size and the singulation of the sensor chips 100 according to 6 not prepared by that throughout the intermediate area 105 between each adjacent sensor chips 100 a vivid common etching trench for all sensor chips 100 is trained. Instead, according to 6 around every sensor chip 100 around a separate ditch 601 formed, whereas in intermediate wafer areas 602 that is, in areas between different etch trenches 601 , an etching is avoided. This is realized by using photoresist on the surface of the silicon wafer using a lithography and an etching process 600 is deposited and structured that the sensor chips 100 as well as the intermediate wafer areas 602 are covered with photoresist, whereas the surface areas of the silicon wafer 600 in which moat 601 is to be introduced, are free of a covering with photoresist material. In a subsequent etching process becomes material of the silicon wafer 600 removed by etching such that etching trenches 601 to be generated. Subsequently, the photoresist is removed from the sensor chips protected from etching 100 and the intermediate wafer areas 602 removed, causing the silicon wafer 600 in the in 6 shown configuration is obtained. According to the described embodiment, it is thus possible, the wafer intermediate areas 602 functionally for any purpose, such as with test structures for testing the functionality of the sensor chips 100 to provide.

By backside etching of the silicon wafer 600 can the sensor chips 100 be separated below. After that, the isolated sensor chips 100 for example in the in 5 shown manner are assembled to form a sensor arrangement according to the invention.

Claims (9)

Method for producing an image sensor arrangement, in which • a plurality of sensor chips are formed on and / or in a substrate, each having a plurality of sensor arrays; Forming around each of the sensor chips, using a lithography process and using an etching process, trenching a depth greater than the depth of the sensor arrays in the substrate, with a separate etch trench around each sensor chip is formed and in areas between different etch trench etching is avoided; Separating a respective sensor chip by removing from the backside of the substrate material of a depth at least equal to the difference between the thickness of the substrate and the depth of the trench; • The sensor chips are assembled in a form-fitting manner to form the sensor arrangement. The method of claim 1, wherein the trench is formed such that a distance of a arranged at an edge of a sensor chip sensor field from the edge is not greater than an extension of the sensor array. Method according to one of claims 1 to 2, wherein the etching method used is an anisotropic etching method. Method according to one of claims 1 to 3, wherein a dry etching method is used as the etching process. Method according to one of Claims 1 to 4, in which the etching method used is sputter etching; or • reactive ion etching is used. Method according to one of claims 1 to 5, in the material of the substrate using • a chemical-mechanical polishing process; or • an etching process is removed. Method according to one of claims 1 to 6, in which different sensor chips are formed the same size. Method according to one of claims 1 to 7, wherein the trench is formed such that a distance of a arranged at an edge of a sensor chip sensor array from the edge is at most 3 microns. Method according to one of claims 1 to 8, wherein the trench is formed such that a distance of a arranged at an edge of a sensor chip sensor array from the edge is at most 1 micron.

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