DD225022A1 - CIRCUIT ARRANGEMENT WITH HYSTERESIS BEHAVIOR IN DIGITAL CIRCUITS - Google Patents

Abstract

The invention relates to digital circuits whose transfer characteristic has a hysteresis behavior, in particular circuits with TTL logic. The invention is directed to creating interference-proof input stages for digital circuits with hysteresis behavior, which reliably recognize the logical TTL level range without restrictions. According to the invention, a Schottky diode is inserted in the reference branch responsible for the position of the switching thresholds.

Description

Prankfurt (Oder), the Zk6

Inventors: Böttcher, Wolfgang, Dipl.-Ing · Maasch, Günter, Dipl.-Ing · Kühn, Rainer, Dr.-Ing · Kühne1, Dieter, Dipl.-Ing ·

Title of the invention

Circuit arrangement with hysteresis behavior in digital circuits

Field of application of the invention

The invention relates to a digital circuit arrangement which makes it possible to build circuits whose transfer characteristic has a hysteresis, in particular circuits with TTL logic.

Characteristic of the known technical solutions

Conventional TTL circuits, as are well known from the literature, in many cases use multi-emitter npn or pnp transistors as components at the input of the circuit. The type of connection of these input transistors to the transistors of the subsequent switching path leads to the destruction the switching threshold for the entire structure, because for TTL standard circuits, input voltages ^ 0.3 Y

should be recognized as "low" and -2.0 7 as "high", the switching threshold Uj _{3 is} most favorable at about 1.4 V; ie there are approximately the same interference safety with respect to the low and the high level, An increase in this interference can be achieved if the input circuit has hysteresis properties; d, h · the turn Ojßj, (transition Low - High on the input) gröJ3er than the turn-off ^ XSH (^ ^via S ^AID S High - Low at the input) is · One way of generating such a hysteresis is shown in EP 0041363 , However, the variation version shown there has "the drawback that it can not work with the above-mentioned TTL Singangsbedingungen because the achieved hysteresis is not symmetrical to the most favorable switching threshold of 1.4" 7. The threshold voltages reached are about 1.3 VC ^ jcr) and 0.9? ^ tsh ^ ·· ^ ^{he max} ^ ^M8L ^ permissible low level at the input of the circuit "must thus be limited to about 0.6 7, because he no longer at low plus voltages of lying in Beferenzzweig transistors and / or increased ambient temperatures is reliably detected ·

Object of the invention

The object of the present invention is to provide fail-safe input stages for digital circuits which have a hysteresis behavior and reliably recognize the logical TTL level without restrictions,

Explanation of the essence of the invention

The object of the invention is the entire voltage hysteresis in positive. Move the direction so that the increase of the noise immunity for both logical input levels is effective and ensures safe operation of the circuit in compliance with the above Ü? TL-Singangspegel. According to the invention, this object is achieved in that a Schottky diode is responsible for the position of the switching thresholds.

literal reference branch is inserted. Depending on the design of this Schottky diode; According to their geometrical dimensions and the height of the potential barrier, the threshold voltages are shifted in the positive direction by the value of the diode voltage. Ss results in the switching thresholds

^Ü ISH ⁼ " ^ϋ ΕΒΣ1 ^{+ ϋ} ΒΞΣ4 ^{+ U} BEX2 ^{+ Ü} BEX3 ^{+ U} F ^;

Pi QA ₁  IKjJZiXi * J t r Ff i ^ t ·ζ ? "* / \ ~) X

The introduced Schottky diode is preferably to be connected directly to the emitter of the responsible for the generation of the hysteresis transistor in order to avoid an effect of the potential shift on the function of the input stage subsequent circuit. It is also connected to an input circuit.

Thus, both interference factors are increased, with sufficient safety distances to the minimum or maximum permissible input voltage levels for the two logic states being present.

Ausführungsbe ispiel

The solution according to the invention is described below with reference to an exemplary embodiment.

Figure 1 schematic diagram

FIG. 2 Driver stage using the solution according to the invention

Figure 3 transmission curves of the driver stages at different ambient temperatures

Figure 4-6 Different variants of the input circuit

In the following, the operation of the circuit according to figure will be described.

At low level at the input, the pnp transistor T1 conducts; the reference path T4 (T5) - D2-T2-T3 is blocked. · The Darlington transistor T8 / T9 is turned on. · This results in a high potential at the output of the switching circuit. · The reference terminal for switching on the feedback is the basic connection τοη Τ7.

^ DA ⁺ % ET6 ^{+ U} BCT7 ^{= Ü} BET7 ^{+ U} CET2 ^{+ U} BET3 ^#

If T2 is disabled, the entire base current of T7 flows into the base of T6 and controls it. Thus, the base current is removed from the transistor T5; it is disabled · When the input voltage is increased up to the value of the switch-on threshold, T2 is turned on; at the output of the circuit is low potential · At the same time opens the base-emitter diode of TT; TS gets no base current and blocks · This causes T5, and the base-emitter diode of T4 is bridged with the gated collector-emitter path of the transistor T5. Thus, the reference path at the input of the circuit changes, so that only when a turn-off voltage Ujsj, "which is about 0.3 - 0.5 Y is lower than the turn-on threshold Ujcgj, the low signal is detected at the input · Then it turns up the initial state described again; d. h ·, even T5 locks again and thus has no influence on the input reference path. A corresponding diagram with the representation of transfer curves of this circuit at different ambient temperatures is shown in FIG.

live the input configuration shown in Figure 1 variants with other input elements are possible, which cause the same effect as described above in connection with the Schottky diode D2

 Such input elements are:

the multi-emitter pnp transistor T11 (Pig. 4),

npn transistor T21 (FIG. 5),

- Scfaottkydiode D11 (Fig. 6).

Claims (5)

Erfindungsazispruch 1. Circuit arrangement with hysteresis behavior in digital circuits with two transistors, wherein the collector of the second transistor and the base of the first transistor are connected, characterized in that the emitters of both transistors (T4, T5) together via a Schottky diode (D2) with the base connected downstream driver transistors (T2; T3) and via further switching elements (LS; RK) to the base of (T5), wherein the cathode of the diode (D2) is further connected to an input circuit (ES) » 2 * circuit arrangement according to item 1, characterized in that the input switching (ES) is realized by a pnp transistor (T1) · 3 · Circuit arrangement according to item 1, characterized in that the input circuit (ES) is realized by a multi-emitter pnp transistor (TH) » 4 · Circuit arrangement according to item 1, characterized in that the input circuit (ES) is realized by an NPN-Traasistor (T21) · 5 · Circuit arrangement according to item 1, characterized in that the input circuit (ES) by a Schottky diode (D11) is realized. For this purpose ... page drawings