CN2676218Y

CN2676218Y - Device for testing digital circuit

Info

Publication number: CN2676218Y
Application number: CN 03248613
Authority: CN
Inventors: 李石平; 王建宏; 李懿; 孙恩元
Original assignee: Zhuzhou CSR Times Electric Co Ltd
Current assignee: Zhuzhou CRRC Times Electric Co Ltd
Priority date: 2003-08-22
Filing date: 2003-08-22
Publication date: 2005-02-02
Anticipated expiration: 2013-08-22

Abstract

The utility model relates to a device for testing digital circuit, comprising a single-chip microcomputer, a bus, a decoder drive circuit, a relay matrix and a 48 core interface. The single-chip microcomputer is connected with a host computer by an RS232 interface. The decoder drive circuit contains three decoder drive circuits which are connected with the single-chip microcomputer by the bus. The relay matrix are a relay matrix which are respectively composed of three relays, and the control coil of every relay matrix is respectively connected with the corresponding driving output terminal which is corresponding with the decoder drive circuit. The right ends of the relay controlled contact points of the first relay matrix, the second relay matrix and the third relay matrix are respectively connected with the power supply, 12 V power supply and a simulating data acquisition path; the other ends connected in parallel are connected with one corresponding terminal port of the 48core interface. The other end of the 48core interface 5 is connected with a measured circuit board. The utility model can solve the problem of testing the digital circuit by the stimulating circuit.

Description

A kind of device of testing digital circuit

Technical field

The utility model relates to a kind of automatic testing equipment, particularly a kind of device of testing digital circuit.

Background technology

Often need carry out performance test to it in the production of electric product, at present, digital circuit normally be adopted in the test of the digital circuit of electric product, the cost of test board, circuit structure are comparatively complicated, realize that difficulty is big.Particularly adopted the machine system of the MC14500 of MOTORAL to carry out logic control in the stored program controlled of the electric control system of large-scale maintenance machinery, total system is made up of CPU board, input/output board, time-delay plate.Electronic package all is the plug connection by 48 cores in the MC14500 system of MOTORAL.System bus is made up of 4 address wires, 1 data lines and 4 control lines, and the single-chip microcomputer of its bus protocol, level, speed and present main flow is incompatible.This has brought very big difficulty for the test to input/output board, time-delay plate.The redesign test circuit can increase design cost, prolong the design cycle.

This programme utilizes test board existing technical conditions (relay matrix and power supply) well to solve this problem.Certainly wherein there is long shortcoming of response time.

Technology contents

The purpose of this utility model aims to provide a kind of circuit structure device simple, that realize easily, that adopt the analog circuit test digital circuit.It comprises:

Single-chip microcomputer 1, bus 2, decoder driver circuit 3, relay matrix 4 and 48 core interfaces 5;

Described single-chip microcomputer 1 links to each other with host computer by the RS232 interface;

Described decoder driver circuit 3 comprises first decoder driver circuit 31, second decoder driver circuit 32 and the 3rd decoder driver circuit 33 that links to each other with single-chip microcomputer 1 by bus 2 respectively;

Described relay matrix 4 is three relay matrix that are made of 48 relays respectively, comprise first relay matrix 41, second relay matrix 42 and the 3rd relay matrix 43, wherein the drive output that each control coil of first relay matrix 41 is corresponding with first decoder driver circuit 31 respectively links to each other, the drive output that each control coil of second relay matrix 42 is corresponding with second decoder driver circuit 32 links to each other, and the drive output that each control coil of the 3rd relay matrix 43 is corresponding with the 3rd decoder driver circuit 33 links to each other;

The right end in controlled contact of each relay of described first relay matrix 41, second relay matrix 42 and the 3rd relay matrix 43 links to each other with power supply ground, 12V power supply and analog data acquisition passage respectively, links to each other with a corresponding port of 48 core interfaces 5 after the other end parallel connection;

The other end of described 48 core interfaces 5 links to each other with the circuit-under-test plate.

This scheme can solve the problem with the analog circuit test digital circuit preferably, wherein has long shortcoming of response time certainly.

Description of drawings

Fig. 1 is the utility model theory diagram;

Fig. 2 is the relay matrix principle schematic.

Embodiment

As shown in Figure 1, 2, it comprises:

The switching of signal is finished by the relay matrix of 3*48.One of them meets 12V (logical one), a ground connection (logical zero), and another connects the analog acquisition passage.A termination common port of 48 relay contacts in every matrix, i.e. signal input part, the other end are received 48 core plugs (as figure) of circuit-under-test plate respectively.As long as corresponding relay closes, signal just can be delivered to any one pin on tested electronic package 48 cores by this relay.Fig. 2 is the relay matrix principle schematic.

Control is finished by 8031 Single Chip Microcomputer (SCM) system, according to the test truth table of circuit-under-test plate control information (closing order of relay) is delivered to decoder driver circuit by bus earlier.Earlier by the corresponding latch of 3-8 decoding gating.Control coding is delivered to each latch by data bus, and then the latch that passes through is delivered to switch triode and made the corresponding relays closure.

In digital circuit, only have 0,1 and three kinds of states of high resistant.Because 4500 is CMOS level of 12V, for address bus and control bus, only has two kinds of situations of ground connection and 12V; Single bus only exists ground connection, 12V and unsettled three kinds of situations.

To the test of non-CPU board, the sequential of bus is listed corresponding test logic truth table, and is stored in the computing machine during earlier according to tested electronic package operate as normal.During the test beginning, computing machine accesses corresponding logic true value table, is compiled into the steering order of relay matrix then, by the corresponding level signal of bus pilot relay matrix output in certain sequence.

For tested electronic package, input high level is just with corresponding relays closure on No. 2 relay boards, the relay of closed No. 1 plate of low level.The output of data line switches to the high resistant acquisition channel by No. 3 relay boards, when the big 11V of voltage that gathers just thinks that data are " 1 ", just thinks that less than 3V data are " 0 ", and other are exactly high-impedance state.For fear of occurring nondeterministic statement occurring in the relay switching, every road signal is by the resistance eutral grounding of a 10K simultaneously.But the edge signal of the triggering of its input can obtain by the sequence of movement and the time of relay.

Claims

1, a kind of device of testing digital circuit is characterized in that:

It comprises single-chip microcomputer (1), bus (2), decoder driver circuit (3), relay matrix (4) and 48 core interfaces (5);

Described single-chip microcomputer (1) links to each other with host computer by the RS232 interface;

Described decoder driver circuit (3) comprises first decoder driver circuit (31), second decoder driver circuit (32) and the 3rd decoder driver circuit (33) that links to each other with single-chip microcomputer (1) by bus (2) respectively;

Described relay matrix (4) is three relay matrix that are made of 48 relays respectively, comprise first relay matrix (41), second relay matrix (42) and the 3rd relay matrix (43), wherein the drive output that each control coil of first relay matrix (41) is corresponding with first decoder driver circuit (31) respectively links to each other, the drive output that each control coil of second relay matrix (42) is corresponding with second decoder driver circuit (32) links to each other, and the drive output that each control coil of the 3rd relay matrix (43) is corresponding with the 3rd decoder driver circuit (33) links to each other;

The right end in described first relay matrix (41), second relay matrix (42) and the controlled contact of each relay of the 3rd relay matrix (43) links to each other with power supply ground, 12V power supply and analog data acquisition passage respectively, links to each other with a corresponding port of 48 core interfaces (5) after the other end parallel connection;

The other end of described 48 core interfaces (5) links to each other with the circuit-under-test plate.