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CN2562364Y - Semiconductor package shell and installation structure - Google Patents

Semiconductor package shell and installation structure Download PDF

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Publication number
CN2562364Y
CN2562364Y CN 01231200 CN01231200U CN2562364Y CN 2562364 Y CN2562364 Y CN 2562364Y CN 01231200 CN01231200 CN 01231200 CN 01231200 U CN01231200 U CN 01231200U CN 2562364 Y CN2562364 Y CN 2562364Y
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China
Prior art keywords
package casing
semiconductor package
lead frame
package
circuit substrate
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Expired - Fee Related
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CN 01231200
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Chinese (zh)
Inventor
小川正则
福荣贵史
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a semiconductor package shell used for surface mounting, which comprises a connection face facing the circuit substrate side during the surface mounting, a package shell 7 made of insulating material and on the outer surface at the back of the connection face, a lead frame 1 with a first face and a second face at the back of the first face, and a semiconductor element 2 arranged on the first face of the lead frame. The lead frame 1 is arranged inside the package shell 7 in a way that the second face thereof is faced to the outer surface of the package shell. The heat produced by the semiconductor element 2 is dissipated to the exterior by the outer surface of the package shell. With the above arrangement, the package shell 7 has no influence on the circuit substrate, so that the circuit substrate has large degree of freedom in material and circuit design.

Description

半导体封装外壳及其安装结构Semiconductor packaging shell and its mounting structure

(1)技术领域(1) Technical field

本发明涉及用于表面安装的半导体封装外壳的结构及其安装结构。The present invention relates to the structure of a semiconductor package case for surface mounting and its mounting structure.

(2)背景技术(2) Background technology

图3表示作为以往技术的半导体封装外壳一个例子的晶体管封装外壳的内部结构。将晶体管芯片2安装在引线框架1的第1面上。因晶体管芯片2的下面是其集电极，所以引线框架1具有作为晶体管芯片2的集电极电极的功能。同时，引线框架1具有作为散热片的功能，是以晶体管芯片2的发热为主，从第1面的背面的第2面进行散热。引线框架1与集电极端3连接。用铝线等的金属线6将晶体管芯片2上表面的压焊点与发射极引线端4和栅极引线端5连接。为了固定各个引线端和保证晶体管芯片2的可靠性，使用环氧树脂等的绝缘物制造的封装外壳7。图4表示内装图3结构的封装外壳7的立体图。集电极端3、发射极端4和栅极端5的引线端与封装外壳下表面几乎是同一平面。封装外壳7具有在表面安装时向着电路基板侧的连接面及其背面的外侧表面。图4的封装外壳7的下表面是连接面。封装外壳7在连接面一侧与电路基板连接。引线框架1配置在封装外壳7内，将其第2面向着封装外壳的连接面。在对大功率进行控制的晶体管封装外壳7中，为了使晶体管芯片2的发热进行散热，将引线框架1的第2面从封装外壳的连接面露出。如前所述，因引线框架1的第2面向着封装外壳7的连接面，所以晶体管芯片2的发热主要通过封装外壳7的连接面向着电路基板散发。也就是说，电气连接通路与散热通路是一致的。其结果，为了承受来自封装外壳7的热量，电路基板的材质选择和电路设计的自由度就受到限制。本发明用于解决以往的这些问题。FIG. 3 shows the internal structure of a transistor package as an example of a conventional semiconductor package. The transistor chip 2 is mounted on the first surface of the lead frame 1 . Since the lower surface of the transistor chip 2 is the collector thereof, the lead frame 1 functions as a collector electrode of the transistor chip 2 . At the same time, the lead frame 1 has a function as a heat sink, and the heat generated by the transistor chip 2 is mainly dissipated from the second surface on the back side of the first surface. The lead frame 1 is connected to a collector terminal 3 . The pads on the upper surface of the transistor chip 2 are connected to the emitter terminal 4 and the gate terminal 5 by metal wires 6 such as aluminum wires. In order to fix each lead terminal and ensure the reliability of the transistor chip 2, a packaging case 7 made of an insulator such as epoxy resin is used. FIG. 4 shows a perspective view of the packaging case 7 incorporating the structure of FIG. 3 . The lead terminals of the collector terminal 3, the emitter terminal 4 and the gate terminal 5 are almost on the same plane as the lower surface of the package shell. The package case 7 has a connection surface facing the circuit board side and an outer surface on the back thereof during surface mounting. The lower surface of the package case 7 of FIG. 4 is a connection surface. The package case 7 is connected to the circuit board on the connection surface side. The lead frame 1 is disposed in the package case 7 with its second surface facing the connection surface of the package case. In the transistor package 7 that controls high power, the second surface of the lead frame 1 is exposed from the connection surface of the package in order to dissipate heat generated by the transistor chip 2 . As mentioned above, since the second surface of the lead frame 1 faces the connection surface of the package case 7 , the heat generated by the transistor chip 2 is mainly dissipated toward the circuit substrate through the connection surface of the package case 7 . That is to say, the electrical connection path is consistent with the heat dissipation path. As a result, in order to withstand the heat from the package case 7, the selection of the material of the circuit board and the degree of freedom in circuit design are limited. The present invention is intended to solve these conventional problems.

(3)发明内容(3) Contents of the invention

本发明的表面安装用半导体封装外壳，包括具有在表面安装时向着电路基板侧的连接面及其背面的外侧表面的绝缘物制造的封装外壳，具有第1面及其背面的第2面的引线框架，和安装在引线框架的第1面上的半导体元件。前述引线框架配置在封装外壳内，将其第2面向着封装外壳的外侧表面。因引线框架的第2面向着封装外壳的外侧表面，所以半导体元件的发热主要通过封装外壳的外侧表面向外部空间散热。因此，电路基板不受封装外壳散热的影响，所以电路基板的材质选定和电路设计的自由度增加。The semiconductor package case for surface mounting of the present invention includes a package case made of an insulator having a connection surface facing the circuit board side and an outer surface on the back side during surface mounting, and has a first surface and leads on a second surface on the back side frame, and a semiconductor element mounted on the first surface of the lead frame. The aforementioned lead frame is disposed in the package case with its second surface facing the outer surface of the package case. Since the second surface of the lead frame faces the outer surface of the package, the heat generated by the semiconductor element is mainly dissipated to the external space through the outer surface of the package. Therefore, the circuit substrate is not affected by the heat dissipation of the package case, so the degree of freedom in selecting the material of the circuit substrate and in circuit design increases.

(4)附图说明(4) Description of drawings

图1表示本发明一实施例的半导体封装外壳的结构图。FIG. 1 shows a structural diagram of a semiconductor package case according to an embodiment of the present invention.

图2表示本发明其它实施例的控制装置的结构图。Fig. 2 is a block diagram showing a control device of another embodiment of the present invention.

图3表示以往的半导体封装外壳的结构图。FIG. 3 shows a configuration diagram of a conventional semiconductor package.

图4表示以往的半导体封装外壳的外形图。FIG. 4 shows an outline view of a conventional semiconductor package.

(5)具体实施方式(5) specific implementation

下面，参照附图对实施本发明的实施例进行说明。Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

实施例1Example 1

图1表示本实施例的晶体管封装外壳的内部结构。将晶体管芯片2安装在引线框架1的第1面上。因晶体管芯片2的下面是其集电极，所以引线框架1具有作为晶体管芯片2的集电极电极的功能。同时，引线框架1具有作为散热片的功能，是以晶体管芯片2的发热为主，从第1面的背面的第2面进行散热。引线框架1与集电极端3连接。用金属线6将晶体管芯片2上面的压焊点与发射极引线端4和栅极引线端5连接。在图3所示的以往技术中，形成的与电路基板连接的集电极端3、发射极端4和栅极端5等引脚端是与封装外壳下表面几乎在同一平面，但在本实施例中，是向着封装外壳上表面弯曲，并且成形的前端与封装外壳上表面平行。为了固定各个引线端和保全晶体管芯片2的可靠性，使用环氧树脂等的绝缘物制造的封装外壳7。封装外壳7具有在表面安装时向着电路基板侧的连接面及其背面的外侧表面。本实施例的封装外壳7的上表面是连接面。封装外壳7在连接面侧与电路基板连接。引线框架1配置在封装外壳7内，将其第2面向着封装外壳的外侧表面。在对大功率进行控制的晶体管封装外壳7中，为了使晶体管芯片2的发热进行散热，至少将引线框架1的第2面的一部分从封装外壳的外侧表面露出。在本实施例的封装外壳7中，因引线框架1的第2面向着封装外壳7的外侧表面，所以晶体管芯片2的发热主要通过封装外壳7的外侧表面向着外部空间散热，向着电路基板的部分很少。因此，将电气连接通路与散热通路分离。这样，封装外壳的散热设计自由度和电路基板的材质选定以及电路设计等的自由度增加。FIG. 1 shows the internal structure of the transistor package of this embodiment. The transistor chip 2 is mounted on the first surface of the lead frame 1 . Since the lower surface of the transistor chip 2 is the collector thereof, the lead frame 1 functions as a collector electrode of the transistor chip 2 . At the same time, the lead frame 1 has a function as a heat sink, and the heat generated by the transistor chip 2 is mainly dissipated from the second surface on the back side of the first surface. The lead frame 1 is connected to a collector terminal 3 . The pads on the transistor chip 2 are connected to the emitter terminal 4 and the gate terminal 5 by metal wires 6 . In the prior art shown in FIG. 3 , the collector terminal 3, the emitter terminal 4, and the gate terminal 5 that are formed to be connected to the circuit substrate are almost on the same plane as the lower surface of the package case, but in this embodiment , is bent toward the upper surface of the package shell, and the shaped front end is parallel to the upper surface of the package shell. In order to fix each lead terminal and secure the reliability of the transistor chip 2, a package case 7 made of an insulator such as epoxy resin is used. The package case 7 has a connection surface facing the circuit board side and an outer surface on the back thereof during surface mounting. The upper surface of the packaging case 7 in this embodiment is the connection surface. The package case 7 is connected to the circuit board on the connection surface side. The lead frame 1 is arranged in the package case 7 with its second surface facing the outer surface of the package case. In the transistor package 7 that controls high power, at least a part of the second surface of the lead frame 1 is exposed from the outer surface of the package in order to dissipate heat generated by the transistor chip 2 . In the package case 7 of this embodiment, because the second face of the lead frame 1 faces the outer surface of the package case 7, the heat generated by the transistor chip 2 is mainly dissipated toward the external space through the outer surface of the package case 7, toward the part of the circuit board. rare. Therefore, the electrical connection path is separated from the heat dissipation path. In this way, the degree of freedom in the heat dissipation design of the package case, the selection of the material of the circuit substrate, and the degree of freedom in circuit design and the like increase.

实施例2Example 2

下面，参照图1对本发明的实施例2进行说明。如图1所示。本实施例的半导体封装外壳的上表面具有集电极端3、发射极端4和栅极端5，并且将封装外表壳上面向着电路基板侧在电路基板上进行表面安装。另一方面，由于晶体管芯片2的损耗而产生的热量，主要通过引线框架1的第2面与封装外壳的外侧表面的热传导，从封装外壳的外侧表面散热。所以，也可以将散热器安装在封装外壳的外侧表面或者从封装外壳的外侧表面露出的引线框架1的第2面上。Next, Embodiment 2 of the present invention will be described with reference to FIG. 1 . As shown in Figure 1. The upper surface of the semiconductor package of this embodiment has a collector terminal 3 , an emitter terminal 4 and a gate terminal 5 , and surface mounting is performed on the circuit substrate with the upper surface of the package outer package facing the circuit substrate side. On the other hand, the heat generated due to the loss of the transistor chip 2 is dissipated from the outer surface of the package mainly through heat conduction between the second surface of the lead frame 1 and the outer surface of the package. Therefore, the heat sink may also be mounted on the outer surface of the package case or the second surface of the lead frame 1 exposed from the outer surface of the package case.

实施例3Example 3

图2表示本发明实施例3的结构。是将安装半导体封装外壳8的电路基板9以及与封装外壳8热耦合的散热器10大致平行配置，并将前述半导体封装外壳8夹在两者之间。将电路元器件11安装在电路基板9上，以便实现例如逆变器驱动功能。Fig. 2 shows the structure of Embodiment 3 of the present invention. The circuit board 9 on which the semiconductor package 8 is mounted and the heat sink 10 thermally coupled to the package 8 are arranged approximately in parallel, and the semiconductor package 8 is sandwiched between them. Circuit components 11 are mounted on the circuit board 9 in order to realize, for example, an inverter driving function.

实施例4Example 4

下面，参照图2对本发明的实施例4进行说明。安装在电路基板9上的封装外壳8夹在电路基板9与散热器10之间。由于封装外壳8和散热器10中的平面度和平行度的变化，有可能使封装外壳8与散热器10的导热系数降低，所以将高传热媒体12隔在封装外壳8和散热器10之间，能防止热接触的降低。特别，借助于用具有柔软性的低硬度高热传导性层12进行热耦合，就能吸收平面度和平行度的变化，防止热接触的降低。此外，用热传导性复合材料代替低硬度高热传导性层12，填加在半导体封装外壳8与散热器10之间以及半导体封装外壳8的侧面和上表面，也能防止热接触的降低。此外，也可以用在未硬化时是糊状的热硬化性热传导性材料代替低硬度高热传导性层12，填加在半导体封装外壳8与散热器10之间以及半导体封装外壳8的侧面和上表面，来防止热接触的降低。此外，用凝胶状的热传导性材料代替低硬度高热传导性层12，填加在半导体封装外壳8与散热器10之间以及半导体封装外壳8的侧面和上表面，也能防止热接触的降低。此外，用两端的二极管或晶体管与二极管的复合元件代替前述的三端的晶体管芯片2，也能得到相同的效果。将端子形成在半导体封装外壳的单面上，呈平面形状，来代替在成形处理中形成端子的引脚型的集电极端3、发射极端4和栅极端5，也能得到相同的效果。此外，填入足够深度的具有热传导性及绝缘性能的树脂，直到将控制基板埋入为止，通过这样能进一步提高热传导性能。Next, Embodiment 4 of the present invention will be described with reference to FIG. 2 . The package case 8 mounted on the circuit substrate 9 is sandwiched between the circuit substrate 9 and the heat sink 10 . Due to the changes in the flatness and parallelism of the package shell 8 and the heat sink 10, it is possible to reduce the thermal conductivity of the package shell 8 and the heat sink 10, so the high heat transfer medium 12 is separated between the package shell 8 and the heat sink 10 between, can prevent the reduction of thermal contact. In particular, by performing thermal coupling with the flexible, low-hardness, and high-thermal-conductivity layer 12, changes in flatness and parallelism can be absorbed, and a decrease in thermal contact can be prevented. In addition, replacing the low-hardness and high-thermal-conductivity layer 12 with a heat-conductive composite material is added between the semiconductor package case 8 and the heat sink 10 and on the side and upper surface of the semiconductor package case 8 to prevent thermal contact from being reduced. In addition, it is also possible to replace the low hardness and high thermal conductivity layer 12 with a thermosetting thermally conductive material that is pasty when it is not hardened, and add it between the semiconductor package case 8 and the heat sink 10 and on the side and upper sides of the semiconductor package case 8. surface, to prevent degradation of thermal contact. In addition, the low hardness and high thermal conductivity layer 12 is replaced by a gel-like thermally conductive material, which is added between the semiconductor package case 8 and the heat sink 10 and on the side and upper surface of the semiconductor package case 8 to prevent the reduction of thermal contact. . In addition, the same effect can also be obtained by replacing the aforementioned three-terminal transistor chip 2 with two-terminal diodes or a composite element of transistors and diodes. The same effect can also be obtained by forming the terminals on one side of the semiconductor package in a planar shape instead of the lead-type collector terminal 3, emitter terminal 4, and gate terminal 5 formed in the forming process. In addition, it is possible to further improve thermal conductivity by filling a resin having thermal conductivity and insulating performance to a sufficient depth until the control substrate is embedded.

Claims (7)

1. a semiconductor package casing that carries out mounted on surface on circuit substrate comprises
Have when mounted on surface the package casing of making towards the insulant of the outer surface at the joint face of circuit substrate side and the back side thereof,
The 2nd lead frame with the 1st and back side,
Be installed on the 1st of lead frame semiconductor element and
Be fixed on a plurality of ends that are electrically connected with semiconductor element on the package casing,
It is characterized in that,
The leadframe configurations that will on the 1st semiconductor element be installed is in package casing, with its 2nd outer surface towards package casing.
2. semiconductor package casing as claimed in claim 1 is characterized in that,
Outer surface to a part of the 2nd of major general's lead frame from package casing is exposed to the outside.
3. a control device comprises
The circuit substrate of mounted on surface semiconductor package casing as claimed in claim 1 and
The outside is installed in the radiator on the package casing outer surface,
It is characterized in that,
Circuit substrate, semiconductor package casing and radiator are parallel in the horizontal direction.
4. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, soft high thermal conductivity layer is set.
5. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, the heat conductivity composite material is set.
6. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, being arranged on when unhardened is the thermosetting thermally-conductive materials of pasty state.
7. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, gelatinous thermally-conductive materials is set.
CN 01231200 2000-08-01 2001-08-01 Semiconductor package shell and installation structure Expired - Fee Related CN2562364Y (en)

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JP2000232640A JP2002050722A (en) 2000-08-01 2000-08-01 Semiconductor package and application device thereof
JP232640/2000 2000-08-01

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