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CN2463958Y - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
CN2463958Y
CN2463958Y CN 01200542 CN01200542U CN2463958Y CN 2463958 Y CN2463958 Y CN 2463958Y CN 01200542 CN01200542 CN 01200542 CN 01200542 U CN01200542 U CN 01200542U CN 2463958 Y CN2463958 Y CN 2463958Y
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CN
China
Prior art keywords
integrated circuit
substrate
signal input
sides
weld pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 01200542
Other languages
Chinese (zh)
Inventor
叶乃华
范光宇
郑清水
何孟南
邱咏盛
陈志宏
黄富勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
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Kingpak Technology Inc
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Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to CN 01200542 priority Critical patent/CN2463958Y/en
Application granted granted Critical
Publication of CN2463958Y publication Critical patent/CN2463958Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors

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  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An integrated circuit is composed of a substrate with signal input and output ends, an integrated circuit with a lower surface with multiple welding pads on its both ends, and two sealing layers filled on both sides of said substrate and integrated circuit for sealing said metal wires.

Description

一种集成电路an integrated circuit

本实用新型涉及一种集成电路,尤指一种具有芯片尺寸大小的、可使产品具有轻、薄、短小优点、符合现今产品需求的集成电路。The utility model relates to an integrated circuit, in particular to an integrated circuit with a chip size, which can make products light, thin and short, and meet the needs of current products.

如图1所示,现有的集成电路包括一基板10,其具有一上表面12及一下表面14,上表面12具有一信号输入端16,下表面具有一信号输出端18,其与一印刷电路板19连接;一集成电路20设置在基板10的上表面12上,且其上具有数个焊垫22,其由数条金属线24连接到基板10的信号输入端16;一封胶层26密封在集成电路20与基板10上方,将数条金属线24覆盖住,用来保护集成电路20及数条金属线24。As shown in Figure 1, the existing integrated circuit includes a substrate 10, which has an upper surface 12 and a lower surface 14, the upper surface 12 has a signal input terminal 16, and the lower surface has a signal output terminal 18, which is connected to a printed circuit board. The circuit board 19 is connected; an integrated circuit 20 is arranged on the upper surface 12 of the substrate 10, and there are several welding pads 22 thereon, which are connected to the signal input terminal 16 of the substrate 10 by several metal lines 24; the sealant layer 26 is sealed above the integrated circuit 20 and the substrate 10 and covers the several metal wires 24 to protect the integrated circuit 20 and the several metal wires 24 .

上述的封装,基板10的面积必须大于集成电路20的面积,以便在将金属线24打线在基板10未被集成电路20覆盖的表面上,所以,封装完成的集成电路的体积较大,无法达到产品轻、簿、短小的要求。In the above-mentioned packaging, the area of the substrate 10 must be larger than the area of the integrated circuit 20, so that the metal wire 24 is bonded on the surface of the substrate 10 not covered by the integrated circuit 20, so the volume of the completed integrated circuit is large and cannot Meet the requirements of light, thin and short products.

为使芯片的封装体积达到与芯片的尺寸相同的要求,以达到轻薄短小的目的,将芯片直接覆盖在基板上,由芯片焊垫上的金属接点直接连接在基板上,不需由额外的金属打线作业便完成电连接,因此,基板可制成与芯片的尺寸相同,而达到与芯片的尺寸大小相同的要求,然而,此种封装方法成本相当高,并不适用于所有芯片的封装。In order to make the packaging volume of the chip meet the same requirements as the size of the chip, and to achieve the purpose of thinness and shortness, the chip is directly covered on the substrate, and the metal contact on the chip pad is directly connected to the substrate without additional metal bonding. Therefore, the substrate can be made the same size as the chip to meet the same size requirements as the chip. However, this packaging method is quite expensive and is not suitable for packaging of all chips.

本实用新型的主要目的在于提供一种集成电路,其与芯片的尺寸大小相同,满足轻、薄、短小的需求。The main purpose of the utility model is to provide an integrated circuit, which has the same size as the chip and meets the requirements of lightness, thinness and shortness.

本实用新型的另一目的在于提供一种集成电路,其便于制造,降低生产成本。Another object of the present invention is to provide an integrated circuit, which is easy to manufacture and reduces production cost.

本实用新型的目的是通过如下的技术方案实现的:The purpose of this utility model is achieved by the following technical solutions:

一种集成电路,它包括:An integrated circuit comprising:

一基板,其具有一上表面及一下表面,该下表面设有一信号输入端及一电连接于该信号输入端、用于连接到印刷电路板上的信号输出端;A substrate, which has an upper surface and a lower surface, and the lower surface is provided with a signal input terminal and a signal output terminal electrically connected to the signal input terminal for connecting to a printed circuit board;

一集成电路,其设有一用以固定到该基板上表面的下表面,该下表面两端具有复数个焊垫,当该集成电路的下表面固定到该基板上时,该复数个焊垫由该基板露出;An integrated circuit, which is provided with a lower surface for fixing to the upper surface of the substrate, with a plurality of solder pads at both ends of the lower surface, when the lower surface of the integrated circuit is fixed to the substrate, the plurality of solder pads are formed by the substrate is exposed;

复数条金属线,其以打线方式电连接到该集成电路的复数个焊垫及基板下表面的信号输入端;A plurality of metal wires are electrically connected to a plurality of welding pads of the integrated circuit and signal input terminals on the lower surface of the substrate by way of bonding;

二个分别填充在该基板与集成电路两侧、用以将该复数条金属线密封的封胶层。Two sealing glue layers are respectively filled on both sides of the substrate and the integrated circuit, and are used to seal the plurality of metal lines.

所述的基板的面积小于该集成电路的面积,当该集成电路固定到该基板的上表面时,该集成电路上的复数个焊垫裸露在该基板外。The area of the substrate is smaller than that of the integrated circuit, and when the integrated circuit is fixed on the upper surface of the substrate, a plurality of welding pads on the integrated circuit are exposed outside the substrate.

所述的基板两侧相对于集成电路设有复数个焊垫的位置分别具有一镂空槽,当该集成电路固定到该基板上时,其两侧复数个焊垫由该基板的镂空槽中露出。The two sides of the substrate are provided with a plurality of welding pads relative to the integrated circuit. There are hollow grooves respectively. When the integrated circuit is fixed on the substrate, the plurality of welding pads on both sides are exposed from the hollow grooves of the substrate. .

所述的集成电路的下表面与该基板的上表面相互黏结。The lower surface of the integrated circuit is bonded to the upper surface of the substrate.

所述的基板的信号输出端为球栅阵列金属球。The signal output end of the substrate is a ball grid array metal ball.

所述的基板的信号输入端位于该基板的两侧。The signal input ends of the substrate are located on both sides of the substrate.

本实用新型可减少基板的材料用量,降低了生产成本;使集成电路封装尺寸与芯片尺寸大小相同,达到轻、薄、对短、小的需求;与芯片尺寸大小相同的封装方法,其制造过程简便,降低了生产成本。The utility model can reduce the material consumption of the substrate and reduce the production cost; the packaging size of the integrated circuit is the same as the size of the chip to meet the requirements of lightness, thinness, shortness and smallness; the packaging method with the same size as the chip, its manufacturing process Simple and convenient, reducing production cost.

以下结合附图及实施例对本实用新型作进一步的详细说明:Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

图1为现有的集成电路的剖视图。FIG. 1 is a cross-sectional view of a conventional integrated circuit.

图2为本实用新型一实施例的剖视图。Fig. 2 is a sectional view of an embodiment of the utility model.

图3为本实用新型另一实施例的剖视图。Fig. 3 is a cross-sectional view of another embodiment of the present invention.

如图2所示,本实用新型包括有:As shown in Figure 2, the utility model includes:

一基板28,其具有一上表面30及一下表面32,下表面32两侧设有信号输入端34及与信号输入端34连接的信号输出端36,信号输出端36为球栅阵列金属球,用来与印刷电路板38连接,将基板28的信号传递到印刷电路板38。A substrate 28, which has an upper surface 30 and a lower surface 32, the lower surface 32 both sides are provided with a signal input terminal 34 and a signal output terminal 36 connected to the signal input terminal 34, the signal output terminal 36 is a ball grid array metal ball, It is used to connect with the printed circuit board 38 and transmit the signal of the substrate 28 to the printed circuit board 38 .

一集成电路40,其设有一用来固定在基板28上表面30的下表面42,下表面42两侧有数个焊垫44,使得当集成电路40的下表面42固定在基板28的上表面30时,数个焊垫44裸露在基板28外;本实施例中集成电路40比基板28大,因此,集成电路40上的焊垫44不致被基板28覆盖住,可以由基板28露出。An integrated circuit 40, which is provided with a lower surface 42 for fixing on the upper surface 30 of the substrate 28, and several welding pads 44 are arranged on both sides of the lower surface 42, so that when the lower surface 42 of the integrated circuit 40 is fixed on the upper surface 30 of the substrate 28 In this embodiment, the integrated circuit 40 is larger than the substrate 28, so the solder pads 44 on the integrated circuit 40 are not covered by the substrate 28 and can be exposed by the substrate 28.

数条金属线46以打线方式连接在集成电路40的数个焊垫44及基板28的下表面32的信号输入端34,使集成电路40的信号传递到基板28上,由基板28的信号输出端36传递到印刷电路板38上。Several metal wires 46 are connected to several welding pads 44 of the integrated circuit 40 and the signal input terminals 34 of the lower surface 32 of the substrate 28 in a wire-bonding mode, so that the signals of the integrated circuit 40 are transmitted to the substrate 28, and the signals of the substrate 28 The output 36 passes to a printed circuit board 38 .

二个封胶层48分别填充在基板28与集成电路40的两侧,将数条金属46线密封,其用来保护复数条金属线46。The two sealing layers 48 are respectively filled on both sides of the substrate 28 and the integrated circuit 40 to seal the plurality of metal lines 46 and are used to protect the plurality of metal lines 46 .

如此,即可将两侧设有焊垫44的集成电路40封装在一比集成电路尺寸小的基板28上,使集成电路40封装后的尺寸与集成电路40的尺寸相同,达到与芯片尺寸相同的封装要求,具有轻薄短小特点,且其制造程序相当简单,可降低封装的生产成本。In this way, the integrated circuit 40 with pads 44 on both sides can be packaged on a substrate 28 smaller than the size of the integrated circuit, so that the packaged size of the integrated circuit 40 is the same as that of the integrated circuit 40, reaching the same size as the chip. It has the characteristics of light, thin and short, and its manufacturing process is quite simple, which can reduce the production cost of packaging.

如图3所示为本实用新型的另一实施例,基板28具有一上表面30及一下表面32,下表面32两侧设有信号输入端34及与信号输入端34电连接的信号输出端36,信号输出端36为球栅阵列金属球,用于连接到印刷电路板38上,将基板28的信号传递至印刷电路板38。As shown in Figure 3, it is another embodiment of the utility model, the substrate 28 has an upper surface 30 and a lower surface 32, and the lower surface 32 both sides are provided with a signal input terminal 34 and a signal output terminal electrically connected with the signal input terminal 34 36 . The signal output terminal 36 is a ball grid array metal ball, which is used to connect to the printed circuit board 38 and transmit the signal of the substrate 28 to the printed circuit board 38 .

该基板28两侧设有贯穿基板28的镂空槽50,当集成电路40的下表面42黏着在基板28的上表面30时,集成电路40两侧的焊垫44由基板28的镂空槽50露出,使复数条金属线46穿过镂空槽50连接到集成电路40的焊垫44与基板28的信号输入端34,封胶层48路填充在镂空槽50内,用于保护复数条金属线46。Both sides of the substrate 28 are provided with hollow grooves 50 penetrating through the substrate 28. When the lower surface 42 of the integrated circuit 40 is adhered to the upper surface 30 of the substrate 28, the solder pads 44 on both sides of the integrated circuit 40 are exposed from the hollow grooves 50 of the substrate 28. , so that a plurality of metal wires 46 are connected to the pad 44 of the integrated circuit 40 and the signal input terminal 34 of the substrate 28 through the hollow groove 50, and the sealant layer 48 is filled in the hollow groove 50 to protect the plurality of metal wires 46 .

Claims (6)

1, a kind of integrated circuit is characterized in that, it comprises:
One substrate, it has a upper surface and a lower surface, and this lower surface is provided with a signal input part and and is electrically connected on this signal input part, is used to be connected to the signal output part on the printed circuit board (PCB);
One integrated circuit, it is provided with one in order to be fixed to the lower surface of this upper surface of base plate, and these lower surface two ends have a plurality of weld pads, and when the lower surface of this integrated circuit was fixed on this substrate, these a plurality of weld pads were exposed by this substrate;
A plurality of metal wires, it is electrically connected to a plurality of weld pads of this integrated circuit and the signal input part of base lower surface in the routing mode;
Two be filled in this substrate and integrated circuit both sides respectively, in order to adhesive layer with these a plurality of metal wires sealings.
2, a kind of integrated circuit as claimed in claim 1 is characterized in that: described this substrate area is less than the area of this integrated circuit, and when this integrated circuit was fixed to the upper surface of this substrate, a plurality of weld pads on this integrated circuit exposed outside this substrate.
3, a kind of integrated circuit as claimed in claim 1, it is characterized in that: described these substrate both sides have a hollow slots respectively with respect to the position that integrated circuit is provided with a plurality of weld pads, when this integrated circuit is fixed on this substrate, expose in the hollow slots of a plurality of weld pads in its both sides by this substrate.
4, a kind of integrated circuit as claimed in claim 1 is characterized in that: the lower surface of described this integrated circuit and the upper surface of this substrate cohere mutually.
5, a kind of integrated circuit as claimed in claim 1 is characterized in that: the signal output part of described this substrate is the ball grid array Metal Ball.
6, a kind of integrated circuit as claimed in claim 1 is characterized in that: the signal input part of described this substrate is positioned at the both sides of this substrate.
CN 01200542 2001-02-01 2001-02-01 Integrated circuit Expired - Lifetime CN2463958Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 01200542 CN2463958Y (en) 2001-02-01 2001-02-01 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 01200542 CN2463958Y (en) 2001-02-01 2001-02-01 Integrated circuit

Publications (1)

Publication Number Publication Date
CN2463958Y true CN2463958Y (en) 2001-12-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 01200542 Expired - Lifetime CN2463958Y (en) 2001-02-01 2001-02-01 Integrated circuit

Country Status (1)

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CX01 Expiry of patent term

Expiration termination date: 20110201

Granted publication date: 20011205