CN222602900U

CN222602900U - SiC MOSFET device with double-gate groove

Info

Publication number: CN222602900U
Application number: CN202423179215.2U
Authority: CN
Inventors: 马鸿铭; 钟炜; 王哲
Original assignee: Beijing Xingan Technology Co ltd
Current assignee: Beijing Xingan Technology Co ltd
Priority date: 2024-12-23
Filing date: 2024-12-23
Publication date: 2025-03-11
Anticipated expiration: 2034-12-23

Abstract

The utility model relates to a SiC MOSFET device with a double-gate groove, and belongs to the technical field of semiconductors. The device includes an active region and a termination region. A first grid groove and a second grid groove are arranged in the active region, a P-type base region is arranged below the first grid groove, a grid oxide layer is covered on the side wall and the bottom, a polycrystalline silicon electrode is filled in the active region and interlayer medium is filled in the active region, a P-type protection region is arranged below the second grid groove, and the side wall and the bottom of the P-type protection region also cover the grid oxide layer and fill the polycrystalline silicon electrode. An N+ type source region and a P+ type source region penetrating through the N+ type source region are arranged between the first grid groove and the second grid groove, and a source ohmic contact electrode is formed on the surface of the source region. Through optimization of the double-gate trench structure and the doping design, the utility model realizes high reliability of the gate oxide layer, uniformity of electric field distribution and excellent conduction performance, and is suitable for high-power density occasions.

Description

SiC MOSFET device with double-gate groove

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to a SiC MOSFET device with a double-gate groove.

Background

In a trench SiC MOSFET, the bottom of the gate trench is prone to electric field concentration effects, which may lead to reduced reliability of the gate oxide layer, and thus affect long-term operation performance of the device. By increasing the junction depth of the P+ region to be obviously larger than the depth of the gate trench, the coverage area of the space charge region below the gate trench can be expanded, so that high voltage is effectively shielded, and the gate oxide layer is protected.

However, in practical applications, increasing the junction depth of the p+ region also presents certain challenges. For the active region of the device, the excessive difference between the junction depth of the P+ region and the depth of the gate trench can cause the compression of a current channel, thereby increasing the specific on-resistance, and for the terminal region, the larger junction depth of the P+ region can cause the position of the peak value of the main junction electric field to move downwards, so that the electric field peak value is difficult to be transferred through a conventional JTE structure. In addition, increasing the junction depth of the p+ region requires increasing the implantation energy, which puts higher demands on the mask process, and this also limits the minimum spacing between adjacent p+ implantation regions, thereby affecting the application of the conventional field limiting ring structure.

Thus, while the introduction of deep p+ regions in trench SiC MOSFETs can significantly improve the reliability of the gate oxide, it can also lead to reduced turn-on capability and reduced breakdown voltage of the device due to mismatch with conventional termination designs. Therefore, the designs for the active and termination regions need to be further optimized to achieve a balance of performance and reliability.

Disclosure of utility model

The utility model aims to provide a SiC MOSFET device with a double-gate groove, which solves the defects in the prior art, and the technical problem to be solved by the utility model is realized by the following technical scheme.

The utility model provides a SiC MOSFET device with a double-gate trench, which comprises an active region and a terminal region, wherein the active region and the terminal region are provided with a SiC substrate and a drift layer positioned on the SiC substrate, the active region comprises a plurality of cell structures,

The cell structure is provided with a first grid groove A and a second grid groove B, wherein a P-type base region is arranged below the first grid groove A, a gate oxide layer is arranged on the side wall and the two end areas of the bottom of the first grid groove A, a polysilicon electrode is arranged on the gate oxide layer in the two end areas of the bottom, and an interlayer medium is filled in the first grid groove A between the polysilicon electrodes;

A layer of P-type protection area is arranged below the second gate groove B, a layer of gate oxide layer is arranged on the side wall and the bottom of the second gate groove B, and a polysilicon electrode is arranged in the second gate groove B;

a P-type base region, an N+ type source region and a P+ type source region are arranged between the first grid electrode groove A and the second grid electrode groove B, the N+ type source region is positioned above the P-type base region, the P+ type source region penetrates through the P-type base region and the N+ type source region and extends into the drift layer, the surface of the P+ type source region is flush with the N+ type source region, and a source ohmic contact electrode is arranged on the P+ type source region;

The terminal region is provided with a residual P+ type source region and an etching region which is formed by etching the terminal region and the first gate trench A at the same time, the depth of the residual P+ type source region is the depth of the first gate trench A subtracted from the injection junction depth of the P+ type source region, and a P type base region is arranged in the etching region.

The back of the SiC substrate is provided with a drain ohmic contact electrode, and the cellular structure is further provided with a layer of front metal.

Further, the depth and the width of the first gate trench a are larger than those of the second gate trench B.

Further, the width of the first gate trench a is not less than 3 μm.

Further, the depth of the first gate trench a is not less than 1.2 μm.

Further, the angle of the sidewall of the first gate trench a is not less than 70 °.

Further, the implantation junction depth of the P+ type source region is not less than 1.5 μm.

Further, the width and depth of the second gate trench B do not exceed 1 μm.

Further, the doping concentration of the P-type protection region is not more than 1×10 ¹⁸cm^-3.

Further, a width of the P-type base region directly below the first gate trench a of the active region is not more than 2 μm.

The device has the advantages that the depth and the width of the second grid electrode groove are smaller than those of the first grid electrode groove, the second grid electrode groove is conducted under low voltage to ensure the starting of the device, the first grid electrode groove is conducted under the condition that the voltage is increased to improve the performance of the device under high current, and the use of the double grid electrode grooves can optimize the overall conduction characteristic of the device. In addition, the P-type base region of the termination region is implanted into the etching region, so that the effective implantation depth can be increased, the JTE or Rings function is exerted on the outer side of the main junction, the electric field peak value is relieved, the breakdown voltage of the device is increased, and the blocking characteristic can be optimized without introducing an additional termination region implantation process.

Drawings

FIG. 1 is a block diagram of a SiC MOSFET device having a dual gate trench of the present utility model;

Detailed Description

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

As shown in fig. 1, the present utility model provides a SiC MOSFET device having a double-gate trench structure, which includes an active region and a termination region having a SiC substrate 1 and a drift layer 2 on the SiC substrate 1. The active region includes a plurality of cell structures having a first gate trench a and a second gate trench B. The P-type base region 5 is arranged below the first gate trench A, the side wall and bottom end regions of the P-type base region are covered with the gate oxide layer 6, the polysilicon electrode 7 is filled on the gate oxide layer, and an interlayer medium 8 is filled in the first gate trench A to provide electrical isolation and mechanical support.

A P-type protection region 10 is disposed under the second gate trench B, and the doping concentration of the P-type protection region 10 is controlled to be not more than 1×101 ⁸cm^- to prevent the compression of the current path. The side walls and the bottom of the second gate trench B are also covered with a gate oxide layer 6, and the polysilicon electrode 7 is filled inside. A P-type base region 5, an N+ type source region 3 and a P+ type source region 4 are arranged between the first gate trench A and the second gate trench B. The n+ type source region 3 is located above the P type base region, and the p+ type source region 4 penetrates the P type base region and the n+ type source region 3 and extends into the drift layer 2. The implantation junction depth of the p+ type source region 4 is designed to be not less than 1.5 μm to ensure that the p+ implantation can function as a protection gate oxide layer, and the surface of the p+ type source region is flush with the surface of the n+ type source region 3. The edges of the P-type base region 5 and the edges of the first gate trench a need to overlap by at least 0.2 μm, so that the P-type base region 5 can wrap the bottom corner of the first gate trench a for protection, and meanwhile, when the alignment of two layers of photoetching plates deviates in the process manufacturing process, the two sides of the first gate trench a can be ensured to normally form a conductive channel.

Source ohmic contact electrodes 9 are provided on the p+ -type source regions 4 and the n+ -type source regions 3 to ensure good current conduction performance. In addition, a layer of front metal 12 is further formed on the surface of the cellular structure to facilitate external wiring.

The structure of the terminal region is optimized, and the P+ type source region is etched, so that the final depth is the depth of the injection junction depth of the P+ type source region minus the depth of the first grid groove A, and the problem of uneven electric field distribution of the terminal region is effectively solved. The terminal region is provided with an etching region which is formed by etching the terminal region and the first grid electrode groove A at the same time, a P-type base region is formed by injecting the inside of the etching region, so that the effective injection depth can be improved, the effect of JTE or Rings is exerted on the outer side of the main junction, the electric field peak value is relieved, the breakdown voltage of the device is improved, and the blocking characteristic of the device structure can be optimized without introducing an additional terminal region injection process. The optimized terminal area design meets the compatibility with a conventional junction end extension structure, and the breakdown voltage performance of the device can be remarkably improved. A drain ohmic contact electrode 11 is provided on the back surface of the SiC substrate 1, and a low-resistance connection is formed with an external circuit.

In the double-gate trench design of the utility model, the depth and width of the first gate trench A are larger than those of the second gate trench B, the width of the first gate trench is not smaller than 3 μm for being compatible with a large-scale etching process of a terminal area, and the depth of the first gate trench is not smaller than 1.2 μm for ensuring that the electric field distribution of the terminal area can be optimized while the specific on-resistance of an active area is reduced. To optimize the electric field distribution of the termination region, the sidewalls of the first gate trench a may be designed to have an angle (not less than 70 °) and the design does not affect the normal performance of the active region trench. The width and depth of the second gate trench B are controlled to be within 1 μm to compress the cell size. Furthermore, the width of the P-type base region 5 immediately below the first gate trench a is controlled to not more than 2 μm to avoid excessive compression of the current path.

The following further describes the key fabrication method of the device. First, a piece of SiC epitaxial wafer having a SiC substrate and a drift layer is prepared, wherein the thickness and doping concentration of the drift layer are designed according to the target withstand voltage requirements of the device. And then, forming an N+ region in the active region by utilizing an ion implantation process, wherein parameters of implantation energy and dosage are optimized to ensure that the N+ region has proper depth and doping concentration, and good conductive performance is provided for the device. Meanwhile, a P+ region is formed in the active region and the terminal region, and the junction depth and the doping concentration of the P+ region are designed to ensure the protection effect on the gate oxide layer.

And etching the first grid groove in the active area and the terminal area simultaneously through an etching process. The etching process needs to control the depth and the side wall angle of the groove, the side wall of the first grid groove can have a certain angle which is not smaller than 70 degrees, so that the electric field distribution of the terminal area is optimized, and the normal performance of the groove of the active area is ensured. And then, forming a P-type base region in the active region and the terminal region by using an ion implantation process. The implant dose and energy are adjusted according to design requirements to optimize the threshold voltage of the device and provide the necessary shielding function under the first gate trench without adversely affecting other region performance.

And forming a second gate trench by performing the etching process again. The width and depth of the trench are controlled to be within 1 μm to compress the cell size. And after the etching is finished, performing ion implantation by using the same mask plate, and forming a P-type protection region below the second grid electrode groove.

After the trench structure is completed, the whole wafer is subjected to thermal oxidation treatment, and gate oxide layers are generated on the side walls and the bottoms of the first gate trench and the second gate trench. A polysilicon layer is then deposited on the wafer and patterned by an etching process to fill the trenches with polysilicon and form gate electrodes.

For electrical isolation and mechanical support, an interlayer dielectric (ILD) is further deposited over the entire wafer, and then an opening is made in the ILD layer by an etching process to expose the p+ and n+ regions, providing a channel for the formation of the source ohmic contact electrode. In the open pore region, source ohmic contact electrode is formed by metallization process, the metal material is usually nickel or titanium, and contact performance is optimized by rapid thermal annealing process. And forming a drain ohmic contact electrode on the SiC substrate.

Finally, a layer of metal is formed on the front side of the device. The front metal is prepared by a deposition process, and a low-resistance metal material such as aluminum is selected to facilitate external connection. The whole device is manufactured by a passivation process, so that the environmental adaptability and the long-term stability of the device are improved.

By introducing the double-gate trench structure and optimizing the doping and geometric design of the P-type base region and the P-type protection region, the utility model obviously improves the reliability and high-voltage breakdown performance of the gate oxide layer of the SiC MOSFET device, and simultaneously realizes the uniform distribution of the electric field in the terminal region. The whole design realizes excellent conduction performance while maintaining high reliability, and provides a high-efficiency solution for power electronic devices with high power density and long service life.

It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.

In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A SiC MOSFET device with dual gate trenches, comprising an active region and a terminal region, wherein the active region and the terminal region have a SiC substrate (1) and a drift layer (2) located on the SiC substrate (1), wherein the active region comprises a plurality of cell structures, and wherein:

The cell structure comprises a first gate trench A and a second gate trench B; a P-type base region (5) is provided below the first gate trench A, a gate oxide layer (6) is provided on the sidewall and the two end regions of the bottom, polysilicon electrodes (7) are provided on the gate oxide layer (6) in the two end regions of the bottom, and an interlayer dielectric (8) is filled in the first gate trench A between the polysilicon electrodes (7);

A P-type protection layer (10) is provided below the second gate trench B, a gate oxide layer (6) is provided on the sidewall and bottom of the second gate trench B, and a polysilicon electrode (7) is provided inside the second gate trench B;

A P-type base region (5), an N+ type source region (3) and a P+ type source region (4) are provided between the first gate trench A and the second gate trench B, the N+ type source region (3) being located above the P-type base region (5), the P+ type source region (4) penetrating the P-type base region (5) and the N+ type source region (3) and extending into the drift layer (2); the surface of the P+ type source region (4) is flush with the N+ type source region (3), and a source ohmic contact electrode (9) is provided on the P+ type source region (4); the P-type base region (5) wraps around the bottom corner of the first gate trench A;

The terminal region has a residual P+ type source region and an etched region formed by etching simultaneously with the first gate trench A, the depth of the residual P+ type source region is the injection junction depth of the P+ type source region minus the depth of the first gate trench A, and there is a P-type base region inside the etched region;

A drain ohmic contact electrode (11) is provided on the back side of the SiC substrate (1), and a layer of front metal (12) is further provided on the cell structure.

2. The SiC MOSFET device with dual gate trenches according to claim 1, wherein the depth and width of the first gate trench A are greater than those of the second gate trench B.

3 . The SiC MOSFET device with dual gate trenches according to claim 1 , wherein a width of the first gate trench A is not less than 3 μm.

4 . The SiC MOSFET device with dual gate trenches according to claim 1 , wherein a depth of the first gate trench A is not less than 1.2 μm.

5 . The SiC MOSFET device with dual gate trenches according to claim 1 , wherein an angle of a sidewall of the first gate trench A is not less than 70°.

6. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that the implantation junction depth of the P+ type source region (4) is not less than 1.5 μm.

7 . The SiC MOSFET device with dual gate trenches according to claim 1 , wherein a width and a depth of the second gate trench B are both less than 1 μm.

8. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that the doping concentration of the P-type protection zone (10) does not exceed 1×10 ¹⁸ cm ^-3 .

9. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that the width of the P-type base region (5) directly below the first gate trench A of the active region does not exceed 2 μm.