CN107731926B - MOSFET device with improved withstand voltage range and preparation method thereof - Google Patents

Abstract

The invention relates to a MOSFET device and a preparation method thereof, in particular to a MOSFET device with improved withstand voltage range and a preparation method thereof, belonging to the technical field of semiconductor devices. The active cell in the cell area adopts a trench structure. Several terminal trenches are arranged in the terminal protection zone. The depth of the terminal trench is greater than that of the cell trench. The terminal trench conducts polysilicon through the terminal trench insulating oxide layer. It is insulated and isolated from the sidewall and bottom wall of the terminal trench; the terminal trench adjacent to the cell area is in contact with the second conductivity type base area above the sidewall of the cell trench adjacent to the terminal protection area, which can effectively improve the withstand voltage range , compatible with existing technology, safe and reliable.

Description

MOSFET device with improved withstand voltage range and preparation method thereof

technical field

The invention relates to a MOSFET device and a preparation method thereof, in particular to a MOSFET device with improved withstand voltage range and a preparation method thereof, belonging to the technical field of semiconductor devices.

Background technique

VDMOSFET (high voltage power MOSFET) can reduce the on-resistance by reducing the thickness of the drain drift region. However, reducing the thickness of the drain drift region will reduce the breakdown voltage of the device. Therefore, in the VDMOSFET, improve the device's performance. The breakdown voltage and reducing the on-resistance of the device are a pair of contradictions. The shielded gate MOSFET structure adopts two vertical polycrystalline field plates in the trench, which not only makes the device introduce two new ones in the drift region. The peak value of the electric field increases the breakdown voltage (BV) of the device, and forms a more concentrated accumulation layer around the vertical drain plate of the device, reducing the on-resistance. Due to the vertical field plate existing between the vertical gate and the drain field plate of this new type of device, the gate-drain capacitance value that affects the switching speed of the device is partially converted into the gate-source capacitance and drain-source capacitance of the device. The high breakdown voltage is achieved at the concentration, so as to obtain low on-resistance and high breakdown voltage at the same time, breaking the theoretical limit of the on-resistance of traditional power MOSFETs.

The shielded gate MOSFET structure has the advantages of low conduction loss, low gate charge, fast switching speed, low device heat generation, and high energy efficiency. The product can be widely used in personal computers, notebook computers, netbooks or mobile phones, lighting (high pressure gas discharge lamps) Products and power supplies or adapters for high-end consumer electronics such as TVs (LCD or Plasma) and game consoles.

For the shielded gate MOSFET junction, the withstand voltage is mainly borne by the thick oxygen column of the gate structure below the deep trench structure, but the limitation of process capability often limits the continued development in the direction of high voltage/ultra-high voltage.

Therefore, it is necessary to provide a shielded gate MOSFET structure and a fabrication method thereof to further improve the withstand voltage capability of a high-voltage MOSFET device.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a MOSFET device with improved withstand voltage range, which has a compact structure, can effectively improve the withstand voltage range, is compatible with the existing technology, and is safe and reliable.

According to the technical solution provided by the present invention, the MOSFET device with improved withstand voltage range includes a cell area on the semiconductor substrate and a terminal protection area, the cell area is located in the center area of the semiconductor substrate, and the terminal protection area is located in the middle of the cell area. The outer ring and the terminal protection area surround the cell area; the semiconductor substrate includes a first conductivity type substrate and a first conductivity type drift layer located above the first conductivity type substrate; the active element in the cell area The cell adopts a trench structure, and a trench gate structure is arranged in the cell trench; a second conductivity type base region is arranged above the sidewall of the cell trench, and the second conductivity type base region is located in the first conductivity type The type drift layer is in contact with the sidewalls of the corresponding cell trenches; the first conductivity type source regions are set in the second conductivity type base regions above the sidewalls between the adjacent cell trenches, and the first conductivity type source regions are the regions are in contact with the sidewalls of the corresponding cell trenches;

A plurality of terminal trenches are arranged in the terminal protection zone, the terminal trenches are located in the first conductivity type drift layer, and the depth of the terminal trenches in the first conductivity type drift layer is greater than that of the cell trenches in the first conductivity type drift layer The terminal trench is provided with terminal conductive polysilicon, and the terminal trench conductive polysilicon is insulated from the sidewall and bottom wall of the terminal trench through the terminal trench insulating oxide layer; the terminal trench adjacent to the cell region is separated from the adjacent The second conductivity type base contacts on the outer side of the cell trench sidewall of the terminal protection area.

The trench gate structure in the cell trench includes a shielded gate structure, and the shielded gate structure includes a lower polysilicon body in the trench and an upper polysilicon body in the trench, and the outer ring of the lower polysilicon body in the trench passes through the trench. The lower insulating oxide layer in the trench is insulated from the sidewall and bottom wall of the cell trench, and the outer ring of the upper polysilicon body in the trench passes through the upper insulating oxide layer in the trench and the sidewall of the cell trench and the lower layer in the trench. The polysilicon body is insulated and isolated, and the width of the upper polysilicon body in the trench is greater than the width of the lower polysilicon body in the trench;

The upper polysilicon body in the trench is in ohmic contact with the gate metal above the drift layer of the first conductivity type, and the polysilicon body of the lower layer in the trench is in ohmic contact with the source metal above the drift layer of the first conductivity type; the source metal is also in ohmic contact with the phase An ohmic contact is made between the base region of the second conductivity type above the outer sidewalls of the inter-cell trenches and the source region of the first conductivity type located in the base region of the second conductivity type.

The depth of the cell trench is 3 μm˜6 μm, and the thickness of the insulating oxide layer of the terminal trench is consistent with the thickness of the lower insulating oxide layer in the trench.

A first conductivity type auxiliary layer is provided between the first conductivity type substrate and the first conductivity type drift layer, and the first conductivity type auxiliary layer is adjacent to the first conductivity type substrate and the first conductivity type drift layer respectively. The thickness of the conductive type auxiliary layer is 10 μm˜20 μm.

A preparation method of a MOSFET device with improved withstand voltage range, the preparation method of the MOSFET device comprises the steps:

Step 1. Provide a semiconductor substrate with a first conductivity type, the semiconductor substrate comprising a first conductivity type substrate and a first conductivity type drift layer located above the first conductivity type substrate; selectively masking and etching a first conductivity type drift layer, so as to obtain the required cell trenches and terminal auxiliary trenches in the first conductivity type drift layer;

Step 2: Etching the above-mentioned terminal auxiliary trench again to obtain the required terminal trench, the depth of the terminal trench is greater than the depth of the cell trench, and the depth of the terminal trench is less than the drift of the first conductivity type the thickness of the layer;

Step 3. Perform the required trench gate preparation process on the cell trench to obtain the required trench gate structure in the cell trench, and when the trench gate structure is prepared, in the terminal trench The terminal conductive polysilicon is obtained, and the terminal trench conductive polysilicon is insulated and isolated from the sidewall and bottom wall of the terminal trench through the terminal trench insulating oxide layer;

Step 4. Implantation of second conductivity type impurity ions is performed on the top of the first conductivity type drift layer, and after diffusion, the required second conductivity type base region is formed on both sides of the cell trench, and the second conductivity type base region is formed. contacting with the cell trench, and the terminal trench adjacent to the cell region is in contact with the second conductive type base region outside and above the sidewall of the cell trench adjacent to the terminal protection protection area;

Step 5. Implantation of first conductivity type impurity ions is performed above the first conductivity type drift layer, so as to obtain the first conductivity type source located in the second conductivity type base region outside and above the sidewalls of the adjacent cell trenches region, the first conductive type source region is in contact with the sidewall of the corresponding cell trench;

Step 6, depositing a metal layer above the first conductivity type drift layer to obtain source metal and gate metal above the first conductivity type drift layer, the source metal and the first conductivity type source region and all The second conductive type base region where the first conductive type source region is located is in ohmic contact, and the gate metal is electrically connected to the trench gate structure in the cell trench.

In step 3, when the prepared trench gate structure is a shielded gate structure, the specific process includes the following steps:

Step 3-1. A first trench insulating oxide layer is simultaneously arranged in the cell trench and the terminal trench, and the first trench insulating oxide layer in the cell trench covers the sidewall and bottom wall of the cell trench, The first trench insulating oxide layer in the terminal trench covers the sidewall and bottom wall of the terminal trench, and after the first trench insulating oxide layer is provided, a first polysilicon filling hole is formed in the cell trench, and the terminal A terminal trench polysilicon filling hole is formed in the trench;

Step 3-2: Conducting conductive polysilicon deposition on the first conductivity type drift layer to obtain a cell polysilicon filling body filled with the first polysilicon filling hole, and a terminal conductive polysilicon filling body filling the terminal trench polysilicon filling hole polysilicon; the first trench insulating oxide layer corresponding to the terminal conductive polysilicon forms a terminal trench insulating oxide layer;

Step 3-3, etching the above-mentioned cell polysilicon filling body to obtain the lower polysilicon body in the trench and the etching positioning hole directly above the lower polysilicon body in the trench;

Step 3-4, using the above-mentioned etching positioning holes to fully etch the first trench insulating oxide layer in the upper part of the cell trench, so as to obtain the lower insulating oxide layer in the trench corresponding to the lower polysilicon in the trench and the lower insulating oxide layer in the trench; an upper groove body directly above the lower polysilicon body in the groove, the width of the upper groove body is consistent with the width of the cell groove;

Step 3-5, a second trench insulating oxide layer is arranged in the upper tank body, the second trench insulating oxide layer covers the sidewall and the bottom of the upper tank body, and the second trench insulating oxide layer is arranged in the upper tank body to form the second trench insulating oxide layer. Two polysilicon filled holes;

Steps 3-6: Conduct conductive polysilicon filling in the second polysilicon filling hole to obtain an upper polysilicon body in the trench filled with the second polysilicon filling hole, and a second polysilicon body corresponding to the upper polysilicon body in the trench. The trench insulating oxide layer forms an upper insulating oxide layer in the trench, and the upper polysilicon body in the trench is insulated from the sidewall of the cell trench and the lower polysilicon body in the trench through the upper insulating oxide layer in the trench; the upper layer in the trench is insulated and isolated; The width of the polysilicon body is greater than the width of the underlying polysilicon body in the trench;

The gate metal is in ohmic contact with the upper polysilicon body in the trench, and the source metal is in ohmic contact with the lower polysilicon body in the trench.

A first conductivity type auxiliary layer is provided between the first conductivity type substrate and the first conductivity type drift layer, and the first conductivity type auxiliary layer is adjacent to the first conductivity type substrate and the first conductivity type drift layer respectively. The thickness of the conductive type auxiliary layer is 10 μm˜20 μm.

The material of the semiconductor substrate includes silicon, and the depth of the cell trench is 3 μm˜6 μm.

Among the "first conductivity type" and "second conductivity type", for N-type power MOSFET devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power MOSFET devices, the first conductivity type refers to N-type. A conductivity type and a second conductivity type refer to types that are just opposite to N-type semiconductor devices.

The advantages of the present invention: the active cell in the cell region adopts a trench structure, a plurality of terminal trenches are arranged in the terminal protection zone, the depth of the terminal trench is greater than that of the cell trench, and the terminal trench conducts polysilicon through the terminal The trench insulating oxide layer is insulated and isolated from the sidewall and bottom wall of the terminal trench; the terminal trench adjacent to the cell region is in contact with the second conductive type base region outside the sidewall of the cell trench adjacent to the terminal protection protection area, which can Effectively improve the withstand voltage range, compatible with existing processes, safe and reliable.

Description of drawings

FIG. 1 is a schematic structural diagram of the present invention.

2 to 11 are cross-sectional views of the specific implementation process steps of the present invention, wherein

FIG. 2 is a cross-sectional view of the present invention after obtaining the cell trench and the terminal auxiliary trench.

FIG. 3 is a cross-sectional view of the terminal trench obtained by the present invention.

4 is a cross-sectional view of the present invention after obtaining the first polysilicon filled hole and the terminal trench polysilicon filled hole.

5 is a cross-sectional view of the present invention after obtaining a cell polysilicon filling body and terminal conductive polysilicon.

FIG. 6 is a cross-sectional view of the present invention after obtaining an etched positioning hole.

FIG. 7 is a cross-sectional view of the present invention after the upper tank body is obtained.

FIG. 8 is a cross-sectional view of the present invention after obtaining the first polysilicon filled hole.

FIG. 9 is a cross-sectional view of the present invention after obtaining the upper layer polysilicon body in the trench.

FIG. 10 is a cross-sectional view of an N+ source region obtained by the present invention.

11 is a cross-sectional view of the source metal and gate metal obtained in the present invention.

Reference numeral description: 201-N+ substrate, 202-N-type auxiliary layer, 203-N-type drift layer, 204-Insulating oxide layer in the lower trench, 205-Polysilicon body in the lower layer in the trench, 206- Upper in the trench Insulating oxide layer, 207-polysilicon body in the upper layer of the trench, 208-P-type base region, 209-N+ source region, 210-source metal, 211-gate metal, 212-cell trench, 213-terminal trench , 214-terminal trench insulating oxide layer, 215-terminal conductive polysilicon, 216-terminal auxiliary trench, 217-first trench insulating oxide layer, 218-first polysilicon filling hole, 219-terminal trench polysilicon filling Hole, 220-cell polysilicon filling body, 221-etched positioning hole, 222-upper groove body and 223-second polysilicon filling hole.

Detailed ways

The present invention will be further described below with reference to the specific drawings and embodiments.

As shown in Figures 1 and 11: In order to effectively improve the withstand voltage range, taking an N-type MOSFET device as an example, the present invention includes a cell area and a terminal protection area located on the semiconductor substrate, and the cell area is located in the central area of the semiconductor substrate. , the terminal protection area is located in the outer ring of the cell area and the terminal protection area surrounds the cell area; the semiconductor substrate includes an N+ substrate 201 and an N-type drift layer 203 located above the N+ substrate 201; the cell area The active cell adopts a trench structure, and a trench gate structure is arranged in the cell trench 212; a P-type base region 208 is provided above the sidewall of the cell trench 212, and the P-type base region 208 Located in the N-type drift layer 203 and in contact with the sidewalls of the corresponding cell trenches 212; N+ source regions 209 and N+ source regions are provided in the P-type base region 208 above the sidewalls of the adjacent cell trenches 212 209 is in contact with the sidewall of the corresponding cell trench 212;

A plurality of terminal trenches 213 are arranged in the terminal protection zone, the terminal trenches 213 are located in the N-type drift layer 203, and the depth of the terminal trenches 213 in the N-type drift layer 203 is greater than that of the cell trench 212 in the N-type drift layer Depth in 203; terminal conductive polysilicon 215 is provided in the terminal trench 213, and the terminal trench conductive polysilicon 215 is insulated from the sidewall and bottom wall of the terminal trench 213 through the terminal trench insulating oxide layer 214; adjacent to the cell area The termination trenches 213 of the terminating trenches are in contact with the P-type base region 208 above the outer sidewalls of the cell trenches 212 adjacent to the termination protection zone.

Specifically, the material of the semiconductor substrate can be silicon or other commonly used semiconductor materials. The cell area is located in the central area of the semiconductor substrate, and the terminal protection area surrounds the cell area. The specific functions and distribution positions of the cell area and the terminal protection area are related to The existing power MOSFET devices are the same and will not be repeated here. The doping concentration of the N+ substrate 201 in the semiconductor substrate is greater than the doping concentration of the N-type drift layer 203 .

A P-type base region 208 is provided on the outside and above the sidewall of each cell trench 212 , and the P-type base region 208 extends vertically downward from the upper surface of the N-type drift layer 203 . outside wall contact. The N+ source region 209 is provided in the P-type base region 208 above the sidewalls of the adjacent cell trenches 213 , and the N+ source region 209 and the P-type base region 208 where it is located are in contact with the outer wall of the corresponding cell trench 213 at the same time. Therefore, for the cell trench 213 adjacent to the terminal protection zone, there is no adjacent cell trench 213 on the side adjacent to the terminal protection zone of the cell trench 213 adjacent to the terminal protection zone. There is no N+ source region 209 in the P-type base region 208 on the side of the cell trench 213 adjacent to the terminal protection zone.

A number of terminal grooves 213 are set in the terminal protection zone, and the number of the terminal grooves 213 can be selected and determined as required. The termination trench 213 is located in the N-type drift layer 203 , the notch of the termination trench 213 and the notch of the cell trench 212 are located on the same level, and the depth of the termination trench 213 is greater than that of the cell trench 212 in the N-type drift. The depth in the layer 203 is smaller than the thickness of the N-type drift layer 203 . The terminal trench 213 is provided with a terminal trench insulating oxide layer 214 and a terminal conductive polysilicon body 215 . The terminal trenches 213 adjacent to the cell region are in contact with the P-type base region 208 above the sidewalls of the cell trenches 212 adjacent to the terminal protection zone. The remaining terminal trenches 213 are independent of each other and are not associated with the cell region. . By setting the depth of the terminal trench 213, the terminal conductive polysilicon 215 and the terminal trench insulating oxide layer 214 in the terminal protection zone, the withstand voltage range can be effectively improved, and the application field of the obtained MOSFET device can be expanded.

The terminal conductive polysilicon 214 in the terminal trench 213 and the terminal trench insulating oxide layer 214 form a floating field plate. After the depth of the terminal trench 213 is greater than the depth of the cell trench 212, the insulating oxide layer distributed in the terminal trench will be oxidized. The potential density in the layer 214 is reduced, thereby avoiding electric field concentration and improving the withstand voltage. In general, the higher the withstand voltage, the faster the lateral depletion of the electric field, so more terminal trenches 213 are required.

Further, the trench gate structure in the cell trench 212 includes a shielded gate structure, and the shielded gate structure includes a lower polysilicon body 205 in the trench and an upper polysilicon body 207 in the trench. The lower polysilicon in the trench The outer ring of the body 205 is insulated from the sidewall and bottom wall of the cell trench 212 by the lower insulating oxide layer 204 in the trench, and the outer ring of the upper polysilicon body 207 in the trench is connected to the cell through the upper insulating oxide layer 206 in the trench. The sidewalls of the cell trench 212 and the lower polysilicon body 205 in the trench are insulated and isolated, and the width of the upper polysilicon body 207 in the trench is greater than the width of the lower polysilicon body 205 in the trench;

The upper polysilicon body 207 in the trench is in ohmic contact with the gate metal 211 above the N-type drift layer 203, and the lower polysilicon body 205 in the trench is in ohmic contact with the source metal 210 above the N-type drift layer 203; the source metal 210 It is also in ohmic contact with the P-type base region 208 above the outer sidewalls of the adjacent cell trenches 212 and the N+ source region 209 located in the P-type base region 208 .

In the embodiment of the present invention, the trench gate structure in the cell trench 212 may adopt a shielded gate structure or other common gate structures. When a shielded gate is adopted, the lower polysilicon body 205 in the trench and the upper layer in the trench are included. For the polysilicon body 207, the width of the upper polysilicon body 207 in the trench is larger than the width of the lower polysilicon body 205 in the trench. The source metal 210 is in ohmic contact with the N+ source region 209, the P-type base region 208 where the N+ source region 209 is located, and the underlying polysilicon body 205 in the trench. The source metal 210 can be used to form the source electrode of the MOSFET device, and the gate metal 211 and The upper polysilicon body 207 in the trench is in ohmic contact, and the gate electrode of the MOSFET device can be formed by using the gate metal 211 . The active cells in the cell region are connected to each other through the source metal 210 to be integrated.

Of course, in the specific implementation, an insulating dielectric layer needs to be provided between the source metal 210, the gate metal 211 and the N-type drift layer 203 to achieve the required insulating isolation. The structure of the specific insulating dielectric layer is set in the technical field It is well known to people and will not be repeated here.

In a specific implementation, the depth of the cell trench 212 is 3 μm˜6 μm, and the thickness of the insulating oxide layer 204 of the terminal trench is consistent with the thickness of the lower insulating oxide layer 204 in the trench. An N-type auxiliary layer 202 is disposed between the N+ substrate 201 and the N-type drift layer 203 , the N-type auxiliary layer 202 is adjacent to the N+ substrate 201 and the N-type drift layer 203 respectively, and the thickness of the N-type auxiliary layer 202 is 10 μm～ 20 μm, the cut-off electric field of the MOSFET device can be effectively improved through the N-type auxiliary layer 202 .

As shown in FIG. 2 to FIG. 11 , the above-mentioned MOSFET device with improved withstand voltage range can be prepared by the following process steps. Specifically, the preparation method of the MOSFET device includes the following steps:

Step 1. Provide a semiconductor substrate with N conductivity type, the semiconductor substrate includes an N+ substrate 201 and an N-type drift layer 203 located above the N+ substrate 201; selectively mask and etch the N-type drift layer 203, To obtain the required cell trenches 212 and terminal auxiliary trenches 216 in the N-type drift layer 203;

Specifically, the material of the semiconductor substrate can be silicon or other materials, and the cell trench 212 and the terminal auxiliary trench 216 can be simultaneously obtained in the N-type drift layer 203 by using technical means commonly used in the technical field, and the cell trench 212 . The terminal auxiliary trench 216 extends vertically downward from the upper surface of the N-type drift layer 203 , and the depths of the cell trench 212 and the terminal auxiliary trench 216 are the same, as shown in FIG. 2 . The specific process of preparing the cell trench 212 and the terminal auxiliary trench 216 is well known to those skilled in the art, and will not be repeated here.

In addition, an N-type auxiliary layer 202 is provided between the N+ substrate 201 and the N-type drift layer 203 , the N-type auxiliary layer 203 is adjacent to the N+ substrate 201 and the N-type drift layer 203 respectively, and the thickness of the N-type auxiliary layer 202 is 10μm～20μm.

Step 2: Etching the above-mentioned terminal auxiliary trench 216 again to obtain the required terminal trench 213, the depth of the terminal trench 213 is greater than the depth of the cell trench 212, and the depth of the terminal trench 213 is less than The thickness of the N-type drift layer 203;

Specifically, only the terminal auxiliary trench 215 is etched by using technical means commonly used in the technical field, so as to obtain the terminal trench 213 with a depth greater than that of the cell trench 212, and the depth of the cell trench is 3 μm˜6 μm, as shown in FIG. 3 shown.

Step 3. Perform the required trench gate preparation process on the cell trench 212 to obtain the required trench gate structure in the cell trench 212, and when the trench gate structure is prepared, the terminal trench is A terminal conductive polysilicon 215 is obtained in the groove 213, and the terminal trench conductive polysilicon 215 is insulated from the sidewall and bottom wall of the terminal trench 213 through the terminal trench insulating oxide layer 214;

Specifically, when the prepared trench gate structure is a shielded gate structure, the specific technological process includes the following steps:

Step 3-1. A first trench insulating oxide layer 217 is provided in the cell trench 212 and the terminal trench 213 at the same time, and the first trench insulating oxide layer 217 in the cell trench 212 covers the cell trench 212. The sidewall and bottom wall, the first trench insulating oxide layer 217 in the terminal trench 213 covers the sidewall and bottom wall of the terminal trench, and after the first trench insulating oxide layer 217 is provided, the cell trench 212 forming a first polysilicon filling hole 218, and forming a terminal trench polysilicon filling hole 219 in the terminal trench 213;

As shown in FIG. 4 , the first trench insulating oxide layer 217 can be a silicon dioxide layer, the first trench insulating oxide layer 217 covers the cell trench 212 and the terminal trench 213 at the same time, and the first trench insulating oxide layer 217 The setting method of the layer 217 may adopt the method of thermal oxidation or filling, which may be selected and determined as required, and will not be repeated here.

Step 3-2. Conduct conductive polysilicon deposition on the above N-type drift layer 203 to obtain a cell polysilicon filling body 220 filling the first polysilicon filling hole 218 and a polysilicon filling body 219 filling the terminal trench. The terminal conductive polysilicon 215; the first trench insulating oxide layer 217 corresponding to the terminal conductive polysilicon 215 forms the terminal trench insulating oxide layer 214;

As shown in FIG. 5 , the conductive polysilicon filled in the terminal trench polysilicon filling hole 219 forms the terminal conductive polysilicon 215 , and after the terminal conductive polysilicon 215 is obtained, the first trench insulating oxide layer 217 in the terminal trench 213 forms the terminal trench The length of the trench insulating oxide layer 214 and the terminal conductive polysilicon 215 is greater than the length of the cell polysilicon filling body 220 .

Step 3-3, etch the above-mentioned cell polysilicon filling body 220 to obtain the lower polysilicon body 205 in the trench in the cell trench 212 and the etching directly above the lower polysilicon body 205 in the trench. Etch the positioning hole 221;

As shown in FIG. 6 , only the cell polysilicon filling body 220 is etched by using technical means commonly used in the technical field to remove the upper part of the cell polysilicon filling body 220 , that is, the lower part of the cell polysilicon filling body 220 is in the cell trench The lower polysilicon body 205 in the trench is formed in the groove 212. After removing the upper part of the cell polysilicon filling body 220, an etching positioning hole 221 is formed directly above the lower polysilicon body 205 in the trench. The outer diameter of the underlying polysilicon body 205 in the trench is the same.

Step 3-4, using the above-mentioned etching positioning holes 221 to fully etch the first trench insulating oxide layer 217 in the upper part of the cell trench 212, so as to obtain the inner trench corresponding to the lower polysilicon body 205 in the trench. The insulating oxide layer 204 and the upper groove body 222 located directly above the lower polysilicon body 205 in the trench, the width of the upper groove body 222 is consistent with the width of the cell trench 212;

As shown in FIG. 7 , when the first trench insulating oxide layer 217 is etched by using the etching positioning holes 221, an upper groove body 222 is obtained. The height of the upper groove body 222 is the same as that of the etching positioning holes 221. is the same as the width of the cell trench 212 . After the first trench insulating oxide layer 217 on the upper part of the cell trench 212 is etched, the remaining first trench insulating oxide layer 217 is the lower insulating oxide layer 204 in the trench.

Step 3-5, a second trench insulating oxide layer 224 is provided in the upper groove body 222, the second trench insulating oxide layer 224 covers the sidewall and bottom of the upper groove body 222, and a second groove is formed in the upper groove body 222 A second polysilicon filling hole 223 is formed after the trench insulating oxide layer 224;

As shown in FIG. 8 , the second trench insulating oxide layer 224 is used to form the upper insulating oxide layer 206 in the trench, and the thickness of the upper insulating oxide layer 206 in the trench is smaller than the thickness of the lower insulating oxide layer 204 in the trench. After the second trench insulating oxide layer 224 is provided, the second polysilicon filled hole 223 is obtained.

Step 3-6: Filling the second polysilicon filling hole 223 with conductive polysilicon to obtain the upper polysilicon body 207 in the trench filled with the second polysilicon filling hole 223, and the upper polysilicon body 207 in the trench The corresponding second trench insulating oxide layer 224 forms the upper insulating oxide layer 206 in the trench, and the upper polysilicon body 207 in the trench passes through the upper insulating oxide layer 206 in the trench and the sidewall of the cell trench 212 and the lower layer in the trench. The polysilicon body 205 is insulated and isolated; the width of the upper polysilicon body 207 in the trench is greater than the width of the lower polysilicon body 205 in the trench;

As shown in FIG. 9, the thickness of the upper insulating oxide layer 206 in the trench is the same as the thickness of the second trench insulating oxide layer 224, and the width of the upper polysilicon body 207 in the trench is larger than the width of the lower polysilicon body 205 in the trench, so , the thickness of the upper insulating oxide layer 206 in the trench is smaller than the thickness of the lower insulating oxide layer 204 in the trench.

Step 4. Implantation of P-type impurity ions is performed above the N-type drift layer 203, and after diffusion, the required P-type base region 208, the P-type base region 208 and the cell trench are formed on both sides of the cell trench 212. The groove 212 is in contact, and the terminal trench 213 adjacent to the cell region is in contact with the P-type base region 208 above the outer wall of the cell trench side 212 adjacent to the terminal protection zone;

Specifically, the P-type impurity ion implantation is performed by using technical means commonly used in the technical field, and the P-type base regions 208 are distributed on both sides of each cell trench 212; Extending downward, when the trench gate in the cell trench 212 adopts a shielded gate structure, the P-type base region 208 is located above the bottom of the upper polysilicon body 207 in the trench.

Step 5. Perform N-type impurity ion implantation on the above-mentioned N-type drift layer 203 to obtain N+ source regions 209 and N+ source regions in the P-type base region 208 located above the sidewalls of the adjacent cell trenches 212 209 is in contact with the sidewall of the corresponding cell trench 212;

As shown in FIG. 10 , the implantation of N-type impurity ions is performed by using technical means commonly used in the technical field, and the N+ source region 209 is only distributed in the P-type base region 208 above the sidewalls between the adjacent cell trenches 212. Therefore, There is no N+ source region 209 in the P-type base region 208 between the termination trench 213 and the cell trench 212 .

Step 6, depositing a metal layer above the N-type drift layer 203 to obtain the source metal 210 and the gate metal 211 above the N-type drift layer 203, the source metal 210 and the N+ source region 209 and the The P-type base region 208 where the N+ source region 209 is located is in ohmic contact, and the gate metal 211 is electrically connected to the trench gate structure in the cell trench 211 .

As shown in FIG. 11 , the source metal 210 and the gate metal 211 are prepared by depositing a metal layer by using technical means commonly used in the technical field. When the shielded gate structure is adopted, the gate metal 211 and the upper polysilicon body 207 in the trench are formed. Ohmic contact, the source metal 210 is in ohmic contact with the underlying polysilicon body 205 in the trench. The specific process of setting the source metal 210 and the gate metal, and realizing the extraction process can be realized by using a common process first, and details are not repeated here. In specific implementation, the source metal 210 and the gate metal are isolated from each other, and the source metal 210, the gate metal and the N-type drift layer 203 can be isolated by insulation such as an insulating medium layer, and the active element in the cell area of the MOSFET device The cells are connected together by the source metal 210 .

In addition, a drain structure needs to be provided on the lower surface of the N+ substrate 201, and the drain electrode of the MOSFET device can be formed through the drain structure. The specific process of forming the drain electrode and the specific form of the drain structure can be selected or referred to. Existing materials will not be repeated here.

Claims (2)

1. A MOSFET device for improving the withstand voltage range, comprising a cell area and a terminal protection area located on a semiconductor substrate, the cell area is located in the center area of the semiconductor substrate, the terminal protection area is located in the outer ring of the cell area, and the terminal protection area is Surrounding and surrounding the cell area; the semiconductor substrate includes a first conductivity type substrate and a first conductivity type drift layer located above the first conductivity type substrate; the active cell in the cell area adopts a trench structure, A trench gate structure is arranged in the cell trench; a second conductivity type base region is arranged above the sidewall of the cell trench, and the second conductivity type base region is located in the first conductivity type drift layer and is connected with the first conductivity type drift layer. Corresponding cell trench sidewalls are in contact; first conductivity type source regions are set in the second conductivity type base regions outside and above the sidewalls between adjacent cell trenches, and the first conductivity type source regions are connected to the corresponding cell trenches The side walls of the slot are in contact; characterized by: A plurality of terminal trenches are arranged in the terminal protection zone, the terminal trenches are located in the first conductivity type drift layer, and the depth of the terminal trenches in the first conductivity type drift layer is greater than that of the cell trenches in the first conductivity type drift layer The terminal trench is provided with terminal conductive polysilicon, and the terminal trench conductive polysilicon is insulated from the sidewall and bottom wall of the terminal trench through the terminal trench insulating oxide layer; the terminal trench adjacent to the cell region is separated from the adjacent the second conductivity type base contact on the outer side of the cell trench sidewall of the terminal protection area; The trench gate structure in the cell trench includes a shielded gate structure, and the shielded gate structure includes a lower polysilicon body in the trench and an upper polysilicon body in the trench, and the outer ring of the lower polysilicon body in the trench passes through the trench. The lower insulating oxide layer in the trench is insulated from the sidewall and bottom wall of the cell trench, and the outer ring of the upper polysilicon body in the trench passes through the upper insulating oxide layer in the trench and the sidewall of the cell trench and the lower layer in the trench. The polysilicon body is insulated and isolated, and the width of the upper polysilicon body in the trench is greater than the width of the lower polysilicon body in the trench; The upper polysilicon body in the trench is in ohmic contact with the gate metal above the drift layer of the first conductivity type, and the polysilicon body of the lower layer in the trench is in ohmic contact with the source metal above the drift layer of the first conductivity type; the source metal is also in ohmic contact with the phase an ohmic contact with a second conductive type base region above the outer sidewalls of the adjacent cell trenches and a first conductive type source region located in the second conductive type base region; The depth of the cell trench is 3 μm˜6 μm, and the thickness of the insulating oxide layer of the terminal trench is consistent with the thickness of the lower insulating oxide layer in the trench; A first conductivity type auxiliary layer is provided between the first conductivity type substrate and the first conductivity type drift layer, and the first conductivity type auxiliary layer is adjacent to the first conductivity type substrate and the first conductivity type drift layer respectively. The thickness of the conductive type auxiliary layer is 10 μm˜20 μm. 2. a preparation method of the MOSFET device that improves withstand voltage range, is characterized in that, the preparation method of described MOSFET device comprises the steps: Step 1. Provide a semiconductor substrate having a first conductivity type, the semiconductor substrate comprising a first conductivity type substrate and a first conductivity type drift layer located above the first conductivity type substrate; selectively masking and etching a first conductivity type drift layer, so as to obtain the required cell trenches and terminal auxiliary trenches in the first conductivity type drift layer; Step 2: Etching the above-mentioned terminal auxiliary trench again to obtain the required terminal trench, the depth of the terminal trench is greater than the depth of the cell trench, and the depth of the terminal trench is less than the drift of the first conductivity type the thickness of the layer; Step 3. Perform the required trench gate preparation process on the cell trench to obtain the required trench gate structure in the cell trench, and when the trench gate structure is prepared, in the terminal trench The terminal conductive polysilicon is obtained, and the terminal trench conductive polysilicon is insulated and isolated from the sidewall and bottom wall of the terminal trench through the terminal trench insulating oxide layer; Step 4. Implantation of second conductivity type impurity ions is performed on the top of the first conductivity type drift layer, and after diffusion, the required second conductivity type base region is formed on both sides of the cell trench, and the second conductivity type base region is formed. contacting the cell trench, and the terminal trench adjacent to the cell region is in contact with the second conductive type base region above the outer sidewall of the cell trench adjacent to the terminal protection protection area; Step 5. Implantation of first conductivity type impurity ions is performed above the first conductivity type drift layer, so as to obtain the first conductivity type source located in the second conductivity type base region outside and above the sidewalls of the adjacent cell trenches region, the first conductive type source region is in contact with the sidewall of the corresponding cell trench; Step 6, depositing a metal layer above the first conductivity type drift layer to obtain source metal and gate metal above the first conductivity type drift layer, the source metal and the first conductivity type source region and all the second conductive type base region where the first conductive type source region is located is in ohmic contact, and the gate metal is electrically connected to the trench gate structure in the cell trench; In step 3, when the prepared trench gate structure is a shielded gate structure, the specific process includes the following steps: Step 3-1. A first trench insulating oxide layer is simultaneously arranged in the cell trench and the terminal trench, and the first trench insulating oxide layer in the cell trench covers the sidewall and bottom wall of the cell trench, The first trench insulating oxide layer in the terminal trench covers the sidewall and bottom wall of the terminal trench, and after the first trench insulating oxide layer is provided, a first polysilicon filling hole is formed in the cell trench, and the terminal A terminal trench polysilicon filling hole is formed in the trench; Step 3-2: Conducting conductive polysilicon deposition on the first conductivity type drift layer to obtain a cell polysilicon filling body filled with the first polysilicon filling hole, and a terminal conductive polysilicon filling body filling the terminal trench polysilicon filling hole polysilicon; the first trench insulating oxide layer corresponding to the terminal conductive polysilicon forms a terminal trench insulating oxide layer; Step 3-3, etching the above-mentioned cell polysilicon filling body to obtain the lower polysilicon body in the trench and the etching positioning hole directly above the lower polysilicon body in the trench; Step 3-4, using the above-mentioned etching positioning holes to fully etch the first trench insulating oxide layer in the upper part of the cell trench, so as to obtain the lower insulating oxide layer in the trench corresponding to the lower polysilicon in the trench and the lower insulating oxide layer in the trench; an upper groove body directly above the lower polysilicon body in the groove, the width of the upper groove body is consistent with the width of the cell groove; Step 3-5, a second trench insulating oxide layer is arranged in the upper tank body, the second trench insulating oxide layer covers the sidewall and the bottom of the upper tank body, and the second trench insulating oxide layer is arranged in the upper tank body to form the second trench insulating oxide layer. Two polysilicon filled holes; Steps 3-6: Conduct conductive polysilicon filling in the second polysilicon filling hole to obtain an upper polysilicon body in the trench filled with the second polysilicon filling hole, and a second polysilicon body corresponding to the upper polysilicon body in the trench. The trench insulating oxide layer forms an upper insulating oxide layer in the trench, and the upper polysilicon body in the trench is insulated from the sidewall of the cell trench and the lower polysilicon body in the trench through the upper insulating oxide layer in the trench; the upper layer in the trench is insulated and isolated; The width of the polysilicon body is greater than the width of the underlying polysilicon body in the trench; The gate metal is in ohmic contact with the upper polysilicon body in the trench, and the source metal is in ohmic contact with the lower polysilicon body in the trench; A first conductivity type auxiliary layer is provided between the first conductivity type substrate and the first conductivity type drift layer, and the first conductivity type auxiliary layer is adjacent to the first conductivity type substrate and the first conductivity type drift layer respectively. The thickness of the conductive type auxiliary layer is 10 μm to 20 μm; The material of the semiconductor substrate includes silicon, and the depth of the cell trench is 3 μm˜6 μm.

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