CN105679810A - Semiconductor structure suitable for charge coupled device and manufacturing method of semiconductor structure - Google Patents

Abstract

The present invention relates to a semiconductor structure suitable for a charge-coupled device and a manufacturing method thereof. On the cross-section of the semiconductor device, a second well region of a second conductivity type is provided in a drift region of a first conductivity type in a terminal protection region, The second well region of the second conductivity type is located in the upper part of the drift region of the first conductivity type, and a plurality of terminal trenches are arranged in the terminal protection zone, and the terminal trenches are located in the second well region of the second conductivity type, and the depth extends to into the drift region of the first conductivity type under the second well region of the second conductivity type; the termination dielectric body and the terminal conductor are filled in the termination trench, and the termination conductor is the same as the adjacent active region outside the termination trench The second conductivity type second well region on the side is electrically connected. The invention has a compact structure, can effectively improve the high-voltage resistance characteristic of the device, is compatible with the existing technology, reduces the cost, has wide application range, and is safe and reliable.

Description

Semiconductor structure suitable for charge-coupled device and its manufacturing method

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor structure suitable for a charge-coupled device and a manufacturing method thereof, belonging to the technical field of semiconductor devices.

Background technique

Regulatory agencies and end customers are increasingly demanding DC-DC power supply efficiency, and new designs require lower on-resistance without compromising unclamped inductive switching (UIS) capability or increasing switching losses.

DC-DC designers are always challenged to improve efficiency and power density. On-resistance (Rds-on) and gate charge (Qg) are two key parameters of power semiconductors. Generally, one always decreases while the other increases. Therefore, power MOSFET designers must consider the trade-off between the two, and the continuous advancement of power MOSFET technology helps them alleviate this contradiction. The charge-coupled MOSFET process can reduce the on-resistance without affecting the gate charge. This technology enables power supply designers to achieve new levels of efficiency and power density.

The higher doping concentration in the drift region of the charge-coupled device has a lower resistivity, which makes it have a lower on-state resistance, but this advantage can become a disadvantage in some respects. First of all, the transverse electric field becomes irregular when it transitions from the device active region to the terminal region, which reduces the reliability of the device; secondly, the longitudinal electric field distribution in the terminal region must be considered, if this is ignored, the breakdown voltage of the terminal region may Much lower than the active area. Therefore, the terminal design of charge-coupled devices is more difficult than that of general power devices.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a semiconductor structure suitable for a charge-coupled device and its manufacturing method, which has a compact structure, can effectively improve the high-voltage resistance characteristics of the device, and is compatible with the existing technology. Cost reduction, wide adaptability, safety and reliability.

According to the technical solution provided by the present invention, the semiconductor structure suitable for charge-coupled devices includes an active region and a terminal protection region on the semiconductor substrate on the top view plane of the semiconductor device, and the active region is located on the semiconductor substrate. In the central area of the substrate, the terminal protection area is located at the outer circle of the active area and surrounds the active area; on the cross-section of the semiconductor device, the semiconductor substrate has two corresponding main surfaces, and the two main surfaces include the first a main surface and a second main surface corresponding to the first main surface, and a drift region of the first conductivity type is included between the first main surface and the second main surface of the semiconductor substrate;

On the cross section of the semiconductor device, a second conductivity type second well region is provided in the first conductivity type drift region of the terminal protection region, and the second conductivity type second well region is located in the first conductivity type drift region In the upper part, a number of terminal grooves are provided in the terminal protection area, and the terminal grooves are located in the second well region of the second conductivity type, and extend deeply into the drift region of the first conductivity type below the second well region of the second conductivity type; The terminal trench is filled with a terminal dielectric body and a terminal conductor, and the terminal conductor is electrically connected to the second conductive type second well region adjacent to the active region outside the terminal trench.

The terminal conductor is located in the central area of the terminal groove, and the terminal dielectric body surrounds the terminal conductor; a second conductive type third well area is provided below the bottom of the terminal groove, and the second conductive The type third well region covers the bottom of the termination trench.

On the cross-section of the semiconductor device, a first well region of a second conductivity type is provided in the drift region of the first conductivity type in the active region, and the first well region of the second conductivity type is located in the drift region of the first conductivity type Upper part: the cells in the active region adopt a trench structure, and the cell trench is located in the first well region of the second conductivity type, and extends deeply into the drift region of the first conductivity type below the first well region of the second conductivity type Inside, the central area in the cell groove is filled with a cell conductor and a cell dielectric body located on the outer ring of the cell conductor, and a cell surrounding the cell conductor is arranged on the upper part of the cell groove. An intracellular trench, an insulating gate oxide layer is grown in the intracellular trench, and gate conductive polysilicon is filled in the intracellular trench with the insulating gate oxide layer grown therein;

A source region of the first conductivity type is provided above the outer wall side of the adjacent cell trench, the source region of the first conductivity type is located in the first well region of the second conductivity type, and the source region of the first conductivity type is connected to the first well region of the second conductivity type The outer wall of the cell groove is in contact; a source metal is provided above the first main surface of the semiconductor substrate, and the source metal is electrically conductive with the source region of the first conductivity type, the first well region of the second conductivity type, and the cell Body ohmic contact, the cells in the active area are connected in parallel through the gate conductive polysilicon to form a whole.

Between the first main surface and the second main surface of the semiconductor substrate, there is also a base of the first conductivity type, the base of the first conductivity type is located under the drift region of the first conductivity type, and the base of the first conductivity type is adjacent to the first conductivity type. type drift region, a drain metal is provided on the substrate of the first conductivity type, and the drain metal is in ohmic contact with the substrate of the first conductivity type.

The cell grooves and terminal grooves are the same process manufacturing layer, the distance between adjacent cell grooves in the active area is the same, and the distance between the cell grooves adjacent to the terminal protection area and the terminal grooves adjacent to the active area The distance is not greater than the distance between adjacent cell grooves, and the distance between adjacent terminal grooves in the terminal protection area is the same or gradually increases along the direction from the active area to the terminal protection area.

The cellular dielectric body and the terminal dielectric body are layers manufactured by the same process.

A method of manufacturing a charge-coupled semiconductor device, the method of manufacturing the semiconductor device comprises the steps of:

a. Provide a semiconductor substrate with two opposite main surfaces, the two opposite main surfaces include a first main surface and a second main surface corresponding to the first main surface, and a first main surface is included between the first main surface and the second main surface a conductivity type substrate and a first conductivity type drift region, the first conductivity type substrate is located below the first conductivity type drift region, and the first conductivity type substrate is adjacent to the first conductivity type drift region;

b. setting a hard mask layer on the first main surface of the semiconductor substrate, and selectively masking and etching the hard mask layer to obtain the desired mask layer window penetrating the hard mask layer;

c. Perform trench etching on the first main surface of the semiconductor substrate by using the above-mentioned mask layer window, so as to obtain the cell trench of the first conductivity type drift region in the active region and the first conductivity type in the terminal protection region Termination trenches in the drift region;

d. Remove the hard mask layer on the first main surface, and perform selective implantation of impurity ions of the second conductivity type on the first main surface of the semiconductor substrate, so as to obtain the second conductive type impurity ions located in the terminal protection area. A well region and a second conductivity type third well region, the second conductivity type second well region is located in the upper part of the first conductivity type drift region of the terminal protection region, and the second conductivity type third well region is located in the second conductivity type second Below the well region, and the third well region of the second conductivity type covers the bottom of the terminal trench;

e. Carry out dielectric filling in the above-mentioned cell trenches and terminal trenches to obtain a cell dielectric body located in the cell trenches, a cell conductor filling hole formed in the central area of the cell trenches, and a cell conductor located in the terminal The terminal dielectric body in the trench and the terminal conductor filling hole formed in the central area of the terminal trench;

f. Filling the conductors in the above-mentioned cell conductor filling holes and terminal conductor filling holes, so as to obtain the cell conductors located in the cell grooves and the terminal conductors located in the terminal grooves;

g. Etching the cellular dielectric body in the cellular trench to obtain an intracellular trench located at the upper part of the cellular trench;

h. Arranging the required insulating gate oxide layer and gate conductive polysilicon in the trench in the above-mentioned cell;

i. Selectively implanting impurity ions of the second conductivity type above the first main surface of the semiconductor substrate to obtain a first well region of the second conductivity type in the drift region of the first conductivity type in the active region;

j. Selectively implanting impurity ions of the first conductivity type above the first main surface of the semiconductor substrate to obtain a source region of the first conductivity type in the first well region of the second conductivity type;

k. Depositing an insulating dielectric layer on the first main surface of the above-mentioned semiconductor substrate, and performing contact hole etching on the insulating dielectric layer;

l. Depositing a front metal layer on the first main surface of the semiconductor substrate, and patterning the front metal layer to obtain source metal, gate metal and terminal connections above the first main surface of the semiconductor substrate Metal, the source metal is in ohmic contact with the first well region of the second conductivity type, the source region of the first conductivity type and the cell conductor, the gate metal is electrically connected with the gate conductive polysilicon, and the terminal conductor is in contact with the terminal trench The second well region of the second conductivity type on the side adjacent to the active region outside the groove is electrically connected to

m. A drain metal is disposed on the second main surface of the semiconductor substrate, and the drain metal is in ohmic contact with the substrate of the first conductivity type.

The distance between adjacent cell grooves in the active region is the same, the distance between the cell groove adjacent to the terminal protection region and the terminal groove adjacent to the active region is not greater than the distance between adjacent cell grooves, and the terminal protection The distance between adjacent terminal trenches in the region is the same or increases gradually along the direction from the active region to the terminal protection region.

The material of the semiconductor substrate includes silicon.

The cell dielectric body and the terminal dielectric body are silicon dioxide.

Among the "first conductivity type" and "second conductivity type", for N-type semiconductor devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type semiconductor devices, the first conductivity type The type and the type referred to by the second conductivity type are just opposite to the N-type semiconductor device.

Advantages of the present invention: the terminal conductor in the terminal trench is electrically connected to the second well region of the second conductivity type on the side close to the active region, when a reverse voltage is applied between the drain metal and the source metal of the device , the potential in the drift region of the first conductivity type gradually decreases from bottom to top, and the terminal conductor in the terminal trench is at the same potential as the corresponding second conductivity type second well region, so that the potential of the terminal conductor is lower than that of the terminal trench A certain potential difference is formed in the drift region of the first conductivity type outside the trench, and due to the charge coupling effect, the degree of depletion of the drift region of the first conductivity type around the termination trench can be enhanced, that is, the depletion in the horizontal direction of the bottom area of the termination trench can be enhanced;

The existence of the third well region of the second conductivity type effectively enhances the depletion of the drift region of the first conductivity type around it. The depletion region extends to all aspects, including the horizontal direction. As the reverse voltage increases, the adjacent two terminals The depletion layer generated under the bottom of the trench is connected in the horizontal direction, which reduces the curvature of the depletion layer in the terminal region, especially effectively slows down the electric field concentration when the active region transitions to the terminal region, and the breakdown characteristics of the device are significantly improved. The structure is simple, the compatibility with the conventional process of the device is good, the manufacturing difficulty is small, and it is beneficial to the control of yield rate and manufacturing cost.

Description of drawings

Fig. 1 is a structural schematic diagram of the present invention.

Fig. 2 ~ Fig. 12 are the sectional views of the specific implementation process steps of the present invention, wherein

FIG. 2 is a cross-sectional view of a semiconductor substrate of the present invention.

Fig. 3 is a cross-sectional view of cell grooves and terminal grooves obtained in the present invention.

Fig. 4 is a cross-sectional view after the P-type second well region and the P-type third well region are obtained according to the present invention.

Fig. 5 is a cross-sectional view of the obtained cellular dielectric body and trench dielectric body according to the present invention.

Fig. 6 is a cross-sectional view of the cellular conductor and the terminal dielectric body of the present invention.

Fig. 7 is a cross-sectional view of the intracellular groove obtained in the present invention.

FIG. 8 is a cross-sectional view of the gate conductive polysilicon obtained in the present invention.

FIG. 9 is a cross-sectional view of the P-type first well region obtained in the present invention.

FIG. 10 is a cross-sectional view of an N+ source region obtained in the present invention.

FIG. 11 is a cross-sectional view of the source metal obtained in the present invention.

Fig. 12 is a cross-sectional view of the drain metal obtained in the present invention.

Explanation of reference numerals: 1-N-type substrate, 2-N-type drift region, 3-cellular trench, 4-terminal trench, 5-P-type first well region, 6-P-type third well region, 7- -P-type second well region, 8-N+ source region, 9-cell dielectric body, 10-cell conductor, 11-terminal dielectric body, 12-terminal conductor, 13-insulating gate oxide layer, 14- Gate conductive polysilicon, 15-cellular conductor filling hole, 16-terminal conductor filling hole, 17-inner trench, 18-source metal, 19-drain metal, 100-active area and 200- terminal protected area.

detailed description

The present invention will be further described below in conjunction with specific drawings and embodiments.

As shown in Figure 1 and Figure 12: In order to effectively improve the high-voltage resistance characteristics of the device, reduce the cost, and improve the scope of application, taking the semiconductor device of N-type MOSFET as an example, the present invention includes the The active area 100 and the terminal protection area 200 on the semiconductor substrate, the active area 100 is located in the central area of the semiconductor substrate, the terminal protection area 200 is located in the outer circle of the active area 100 and surrounds the active area 100; On the cross section of the semiconductor device, the semiconductor substrate has two corresponding main surfaces, the two main surfaces include a first main surface and a second main surface corresponding to the first main surface, the first main surface of the semiconductor substrate and the second main surface An N-type drift region 2 is included between the two main surfaces;

On the cross-section of the semiconductor device, a P-type second well region 7 is provided in the N-type drift region 2 of the terminal protection region 200, and the P-type second well region 7 is located in the upper part of the N-type drift region 2, and the terminal A number of terminal trenches 4 are provided in the protection area 200, and the terminal trenches 4 are located in the P-type second well region 7, and extend deeply into the N-type drift region 2 below the P-type second well region 7; The trench 4 is filled with a terminal dielectric body 11 and a terminal conductor 12 , and the terminal conductor 12 is electrically connected to the P-type second well region 7 on the side adjacent to the active region 100 outside the termination trench 4 .

Specifically, the active area 100 is located in the central area of the semiconductor substrate, and the terminal protection area 200 is located around the active area 100. The specific functions of the active area 100 and the terminal protection area 200 are the same as the existing ones, and will not be repeated here. The material of the semiconductor substrate can be commonly used silicon, etc. For an N-type semiconductor device, an N-type drift region 2 is included between the first main surface and the second main surface of the semiconductor substrate. In addition, the semiconductor substrate can also include an N-type base 1, The N-type substrate 1 is adjacent to the N-type drift region 2, the N-type drift region 2 is located above the N-type substrate 1, the upper surface of the N-type drift region 2 forms the first main surface of the semiconductor substrate, and the lower surface of the N-type substrate 1 forms the semiconductor substrate. The second main surface of the substrate is well known to those skilled in the art, and will not be repeated here.

A P-type second well region 7 is provided in the terminal protection region 200, the P-type second well region 7 is located on the upper part of the N-type drift region 2, and the P-type second well region 7 extends downward from the first main surface of the semiconductor substrate. Enter the N-type drift region 2. Several terminal trenches 4 are arranged in the terminal protection area 200, the terminal trenches 4 are located in the P-type second well region 7, the notches of the terminal trenches 4 are located on the first main surface of the semiconductor substrate, and the grooves of the terminal trenches 4 The bottom is located in the N-type drift region 2 below the P-type second well region 7 , that is, the terminal trench 4 vertically extends into the N-type drift region 2 in the P-type second well region 7 . The terminal dielectric body 11 is filled in the terminal groove 4, and the terminal dielectric body 11 covers the side wall and the bottom wall of the terminal groove 4. The terminal dielectric body 11 can be a silicon dioxide layer, and the terminal conductor 12 passes through the terminal dielectric body 11 and the bottom wall. The inner wall and the bottom wall of the terminal trench 4 are insulated and isolated. On the cross-section of the semiconductor device, both sides outside the terminal trench 4 have a P-type second well region 7, and the terminal conductor 12 in the terminal trench 4 is the same as the adjacent active region 100 outside the terminal trench 4. The P-type second well region 7 on the side is electrically connected. During specific implementation, the terminal conductor 12 may be conductive polysilicon, and the terminal conductor 12 is electrically connected to the P-type second well region 7 corresponding to the side adjacent to the active region 100 through the terminal connection metal located above the terminal trench 4 .

Further, the terminal conductor 12 is located in the central area of the terminal trench 4, and the terminal dielectric body 11 surrounds the terminal conductor 12; a P-type third well area is provided below the bottom of the terminal trench 4 6. The P-type third well region 6 covers the bottom of the termination trench 4 .

In the embodiment of the present invention, the terminal conductor 12 is distributed coaxially with the terminal groove 4 , and the terminal dielectric body 11 surrounds the terminal conductor 12 . The P-type third well region 6 is located below the bottom of the termination trench 4 and covers the bottom of the termination trench 4, that is, the bottom of each termination trench 4 has a P-type third well region 6, and the P-type The third well region 6 is located in the N-type drift region 2, and the use of the P-type third well region 6 can effectively slow down the electric field concentration when the active region 100 transitions to the terminal protection region 200, and effectively improve the anti-breakdown characteristics of the semiconductor device.

Taking the semiconductor device of N-type MOSFET and the cells of the active region 100 adopting a trench structure as an example, on the cross section of the semiconductor device, a P-type first well is arranged in the N-type drift region 2 of the active region 100 Region 5, the P-type first well region 5 is located in the upper part of the N-type drift region 2; the cells in the active region 100 adopt a trench structure, and the cell trench 3 is located in the P-type first well region 5, Deeply protruding into the N-type drift region 2 below the P-type first well region 5, the central region in the cellular trench 3 is filled with a cellular conductor 10 and cells located on the outer ring of the cellular conductor 10. The cellular dielectric body 9 is provided with an intracellular trench 17 surrounding the cellular conductor 10 on the upper part of the cellular trench 3, and an insulating gate oxide layer 13 is grown in the intracellular trench 17. The intracellular trenches 17 grown with the insulating gate oxide layer 13 are filled with gate conductive polysilicon 14;

An N+ source region 8 is provided above the outer wall side of the adjacent cell trench 3, the N+ source region 8 is located in the P-type first well region 5, and the N+ source region 8 is connected to the cell trench 3 The outer walls are in contact; a source metal 18 is provided above the first main surface of the semiconductor substrate, and the source metal 18 is in ohmic contact with the N+ source region 8, the P-type first well region 5 and the cell conductor 10, and has The cells in the source region 100 are connected in parallel through the gate conductive polysilicon 14 to form a whole.

In the embodiment of the present invention, the P-type first well region 5 is located in the N-type drift region 2, and the P-type first well region 5 extends downward from the first main surface of the semiconductor substrate into the N-type drift region 2, and the active region 100 It includes a number of cells. When the trench structure is adopted, the cell trench 3 vertically extends from the P-type first well region 5 into the N-type drift region 1, and the notch of the cell trench 3 is located on the first semiconductor substrate. On one main surface, the upper part of the cell trench 3 passes through the P-type first well region 5 . The cellular trench 3 is filled with a cellular dielectric body 9 and a cellular conductor 10, the cellular dielectric body 9 may be silicon dioxide, and the cellular conductor 10 is located in the central area of the cellular trench 3, that is, the cellular conductor The body 10 is insulated and isolated from the side wall and the bottom wall of the cell trench 3 through the cell dielectric body 9 , and the cell conductor 10 can be made of conductive polysilicon.

In order to be able to form the source of the MOSFET, an intracellular trench 17 is also provided in the cellular trench 3, and the intracellular trench 17 can be obtained by etching the upper part of the cellular dielectric body 9 in the cellular trench 3 . The depth of the intracellular trench 17 is smaller than the depth of the intracellular trench 3, the bottom of the intracellular trench 17 is located below the P-type first well region 5, and an insulating gate oxide layer 13 is grown in the intracellular trench 17 As well as the gate conductive polysilicon 14 , the insulating gate oxide layer 13 and the gate conductive polysilicon 14 both surround the cell conductor 10 . The cellular dielectric body 9 and the terminal dielectric body 11 are layers manufactured by the same process.

The N+ source region 8 is located in the P-type first well region 5 , and the N+ source region 8 is in contact with the outer sidewall of the intracellular trench 17 growing the insulating gate oxide layer 13 . The N+ source region 8 is distributed above the outer walls of the adjacent cell trenches 3 . The source metal 18 is in ohmic contact with the N+ source region 8 , the P-type first well region 5 and the cell conductor 10 , so as to form a charge-coupled active region 100 structure. The cells in the active region 100 are connected to each other through the gate conductive polysilicon 14 and then connected in parallel to form a whole. The gate conductive polysilicon 14 and the source metal 18 are insulated from each other. In the embodiment of the present invention, the specific structure of the active region 100 suitable for charge coupling is well known to those skilled in the art, and will not be repeated here.

Further, the semiconductor substrate further includes an N-type substrate 1 between the first main surface and the second main surface, the N-type substrate 1 is located below the N-type drift region 2, and the N-type substrate 1 is adjacent to the N-type drift region 2. A drain metal 19 is provided on the N-type substrate 1 , and the drain metal 19 is in ohmic contact with the N-type substrate 1 .

In the embodiment of the present invention, the drain metal 19 is in ohmic contact with the N-type substrate 1 so as to form the drain terminal of the MOSFET device, which is well known to those skilled in the art.

The cellular trenches 3 and terminal trenches 4 are the same process manufacturing layer, and the distance between adjacent cellular trenches 3 in the active region 100 is the same, and the cellular trenches 3 adjacent to the terminal protection region 200 are the same as those adjacent to the active region. The distance between the terminal grooves 4 in the region 100 is not greater than the distance between the adjacent cell grooves 3, and the distance between the adjacent terminal grooves 4 in the terminal protection area 200 is the same or points to the terminal protection area 200 along the active area 100 direction gradually increases.

As shown in Figures 2 to 12, the above-mentioned semiconductor device suitable for charge coupling can be prepared through the following process steps. Specifically, the manufacturing method of the semiconductor device includes the following steps:

a. Provide a semiconductor substrate with two opposite main surfaces, the two opposite main surfaces include a first main surface and a second main surface corresponding to the first main surface, between the first main surface and the second main surface, an N-type A substrate 1 and an N-type drift region 2, the N-type substrate 1 is located below the N-type drift region 2, and the N-type substrate 1 is adjacent to the N-type drift region 2;

Specifically, the material of the semiconductor substrate can be commonly used silicon, and the thickness of the N-type drift region 2 is greater than the thickness of the N-type substrate 1, as shown in Figure 2, the specific form of the semiconductor substrate can also be selected according to the needs, specifically for this technology It is well known to those in the field and will not be repeated here.

b. setting a hard mask layer on the first main surface of the semiconductor substrate, and selectively masking and etching the hard mask layer to obtain the desired mask layer window penetrating the hard mask layer;

In the embodiment of the present invention, the hard mask layer is deposited on the first main surface of the semiconductor substrate. The material of the hard mask layer and the process of setting the hard mask layer are well known to those skilled in the art. Herein No longer. The masking and etching of the hard mask layer can be realized by coating photoresist on the hard mask layer, and the window of the mask layer penetrates the hard mask layer, so that the corresponding first main surface of the semiconductor substrate can exposed. During specific implementation, the mask layer windows include windows located in the active area and windows located in the terminal protection area.

c. Groove etching is performed on the first main surface of the semiconductor substrate by using the above-mentioned mask layer window to obtain the cell trench 3 in the N-type drift region 2 in the active region 100 and the N-type cell trench in the terminal protection region 200 The termination trench 4 of the drift region 2;

In the embodiment of the present invention, after trench etching is performed on the first main surface of the semiconductor substrate by using the mask layer window, the cellular trench 3 and the terminal trench 4 can be obtained, and the cellular trench 3 and the terminal trench 4 can be obtained. The notches are all located on the first main surface, and the cell trench 3 and the terminal trench 4 extend vertically downward from the first main surface of the semiconductor substrate. During specific implementation, the spacing between adjacent cell trenches 3 in the active region 100 is the same, and the distance between the cell trenches 3 adjacent to the terminal protection region 200 and the terminal trenches 4 adjacent to the active region 100 is not greater than that of the adjacent cell trenches 3. The distance between the cell trenches 3 is the same as the distance between adjacent terminal trenches 4 in the terminal protection area 200 or increases gradually along the direction from the active region 100 to the terminal protection area 200 . The spacing between the cell trenches 3 and the spacing between the terminal trenches 4 can be controlled through the window of the above mask layer, which is well known to those skilled in the art and will not be repeated here.

d. Remove the hard mask layer on the first main surface, and perform selective implantation of P-type impurity ions on the first main surface of the semiconductor substrate, so as to obtain the P-type second well region 7 located in the terminal protection area 200 And the P-type third well region 6, the P-type second well region 7 is located in the upper part of the N-type drift region 2 of the terminal protection region 200, the P-type third well region 6 is located below the P-type second well region 7, and The P-type third well region 6 covers the bottom of the terminal trench 4;

In the embodiment of the present invention, the hard mask layer is removed by conventional technical means, as shown in FIG. 3 . After removing the hard mask layer, perform P-type impurity ion implantation on the first main surface of the semiconductor substrate, such as implanting boron ions, thereby obtaining the P-type second well region 7 and the P-type third well region 6, and the terminal trench 4 The upper part passes through the P-type second well region 7, as shown in FIG. 4 . The process of implanting P-type impurity ions on the first main surface to obtain the P-type second well region 7 and the P-type third well region 6 is well known to those skilled in the art. In addition, the P-type second well region 7 and the P-type third well region The well region 6 can also be formed through a two-step implantation process, which can be selected according to needs, and will not be repeated here.

e. Carry out dielectric filling in the above-mentioned cellular trench 3 and terminal trench 4, so as to obtain the cellular dielectric body 9 located in the cellular trench 3 and the cellular conductor formed in the central area of the cellular trench 3 Filling hole 15, terminal dielectric body 11 located in terminal trench 4, and terminal conductor filling hole 16 formed in the central area of terminal trench 4;

In the embodiment of the present invention, the cellular dielectric body 9 and the terminal dielectric body 11 are silicon dioxide, which can be obtained by first thermally oxidizing and then depositing silicon dioxide. The thickness of the cellular dielectric body 9 and the terminal dielectric body 11 is determined by the semiconductor The withstand voltage specification of the device and the determination of the doping concentration of the N-type drift region 1 are well known to those skilled in the art, and will not be repeated here. The cell conductor filling hole 15 is located in the central area of the cell trench 3, the cell conductor filling hole 15 is formed by filling the cell dielectric body 9 in the cell trench 3, and the terminal conductor filling hole 16 is located in the terminal trench In the central area of the groove 4 , the terminal conductor filling hole 16 is formed by filling the terminal dielectric body 11 in the terminal groove 4 , as shown in FIG. 5 .

f. Carry out conductor filling in the above-mentioned cellular conductor filling hole 15 and terminal conductor filling hole 16, so as to obtain the cellular conductor 10 located in the cellular trench 3 and the terminal conductor located in the terminal trench 4 Body 12;

In the embodiment of the present invention, the conductive polysilicon can be used as the conductor shown, and the conductor can be deposited on the first main surface of the semiconductor substrate. After the conductor fills the cell conductor filling hole 15 and the terminal conductor filling hole 16 respectively , etc. are used to etch back by dry etching to obtain the cell conductor 10 in the cell trench 3 and the terminal conductor 12 in the terminal trench 4, as shown in FIG. 6 , the specific process is in the technical field It is well known to personnel and will not be repeated here.

g. Etching the cellular dielectric body 9 in the cellular trench 3 to obtain an intracellular trench 17 located at the upper part of the cellular trench 3;

In the embodiment of the present invention, the intracellular groove 17 is obtained after the cellular dielectric body 9 is etched by conventional technical means, and the intracellular groove 17 extends vertically downward from the notch of the cellular groove 17, as shown in Figure 7 described.

h, setting the required insulating gate oxide layer 13 and gate conductive polysilicon 14 in the trench 17 in the above-mentioned cell;

In the embodiment of the present invention, the insulating gate oxide layer 13 is first grown in the intracellular trench 17, and the gate conductive polysilicon 14 is filled in the intracellular trench 17 after the insulating gate oxide layer 13 is grown. 14 and the cellular conductor 10 are insulated and isolated through the insulating gate oxide layer 13 and the cellular dielectric body 9 , as shown in FIG. 8 .

i. Selectively implanting P-type impurity ions above the first main surface of the semiconductor substrate to obtain a P-type first well region 5 in the N-type drift region 2 of the active region 100;

In the embodiment of the present invention, the P-type impurity ions may be boron ions, and only the P-type impurity ions are implanted into the active region 100 to obtain the P-type first well region 5 on the upper part of the N-type drift region 2, and the P-type first well region 5. The depth of the first well region 5 may be smaller than the depth of the P-type second well region 7 , and the P-type first well region 5 is located at intervals between adjacent cell trenches 3 . The P-type second well region 7 adjacent to the active region 100 is in contact with the outer wall of the cell trench 3 adjacent to the terminal protection region 200, and the P-type first well region 5 is located above the bottom of the intracellular trench 17, as Figure 9 shows.

j. Selectively implanting N-type impurity ions above the first main surface of the semiconductor substrate to obtain an N+ source region 8 in the P-type first well region 5;

In the embodiment of the present invention, the N-type impurity ions can be phosphorus ions or arsenic ions, and the N+ source region 8 is located in the P-type first well region 5. The process of obtaining the N+ source region 8 is well known to those skilled in the art. No more details here, as shown in Figure 10.

k. Depositing an insulating dielectric layer on the first main surface of the above-mentioned semiconductor substrate, and performing contact hole etching on the insulating dielectric layer;

In the embodiment of the present invention, the insulating dielectric layer may be a silicon dioxide layer, and the insulating dielectric layer covers the first main surface of the semiconductor substrate. The process of depositing the insulating dielectric layer and the process of etching the contact hole of the insulating dielectric layer are both It is well known to those skilled in the art, and will not be repeated here.

1. Deposit a front metal layer on the first main surface of the semiconductor substrate, and pattern the front metal layer to obtain the source metal 18, gate metal and terminal located above the first main surface of the semiconductor substrate Connect the metal, the source metal 18 is in ohmic contact with the P-type first well region 5, the N+ source region 8 and the cell conductor 10, the gate metal is connected with the gate conductive polysilicon circuit 14, and the terminal conductor 12 is in contact with the cell conductor 10. The P-type second well region 7 on the side adjacent to the active region 100 outside the terminal trench 4 is electrically connected through a terminal connection metal;

In the embodiment of the present invention, the front metal layer is supported on the insulating medium layer. After patterning the front metal layer, the source metal 8, the gate metal and the terminal connection metal are respectively obtained. The source metal 8 is located in the active region 100, The source metal 8 can be in ohmic contact with the P-type first well region 5, the N+ source region 8 and the cell conductor 10 through the contact hole in the active region 100, and the gate metal is in contact with the gate conductive polysilicon in the active region 100. 14, so that the cells in the active region 100 can be connected in parallel to form a whole. The terminal connection metal is located above the terminal protection area 200, and the terminal conductor 12 in the terminal trench 4 is electrically connected to the P-type second well region 7 on the side adjacent to the active region 100 outside the terminal trench 4 through the terminal connection metal. connection, as shown in Figure 11. FIG. 11 does not show the gate metal, the terminal connection metal, and the insulating dielectric layer. The specific connection forms are well known to those skilled in the art and will not be repeated here.

m. A drain metal 19 is provided on the second main surface of the semiconductor substrate, and the drain metal 19 is in ohmic contact with the N-type substrate 1 .

In the embodiment of the present invention, the drain terminal of the MOSFET device is formed through the drain metal 19 , as shown in FIG. 12 .

In the embodiment of the present invention, after the terminal conductor 12 in the terminal trench 4 in the terminal region 200 is electrically connected to the P-type second well region 7 on the side near the active region 100 outside the terminal trench 4, when When a reverse voltage is applied between the drain metal 19 and the source metal 18 (that is, a positive voltage is applied to the drain metal 19 and a negative voltage is applied to the source metal 18), the potential in the N-type drift region 2 gradually decreases from bottom to top , and the terminal conductor 12 in the terminal trench 4 has the same potential as the P-type second well region 7 adjacent to the active region 100, so that the potential of the terminal conductor 12 is lower than that of the N-type drift region on the periphery of the terminal trench 4 2. A certain potential difference is formed. Due to the charge coupling effect, the degree of depletion of the N-type drift region 2 at the periphery of the terminal trench 4 is enhanced. The enhanced depletion shown includes depletion in the horizontal direction of the bottom area of the terminal trench 4 .

In addition, the P-type third well region 6 is injected into the bottom of the terminal trench 4 in the terminal protection region 200. When a reverse voltage is applied between the drain metal 19 and the source metal 18 of the device, the P-type third well region 6 There is an effective enhancement of the depletion of the surrounding N-type drift region 2, and the depletion region extends in all directions, including the horizontal direction. As the reverse voltage increases, the depletion generated below the bottom of the two adjacent terminal trenches 4 The layers are connected in the horizontal direction, which reduces the curvature of the depletion layer in the terminal protection area 200, especially effectively slows down the electric field concentration when the active area 100 transitions to the terminal protection area 200, and significantly improves the breakdown characteristics of the device. If the P-type third well region 6 is not provided at the bottom of the terminal trench 4 in the terminal protection region 200, as the reverse voltage increases, the device will strike in advance in the transition region between the active region 100 and the terminal protection region 200. wear, which can effectively improve the high pressure resistance characteristics.

The description and application of the invention herein is illustrative and is not intended to limit the scope of the invention to the above-described embodiments. Variations and changes to the embodiments disclosed herein are possible, and substitutions and equivalents for various components of the embodiments are known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other modifications and changes may be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims (10)

1. A semiconductor structure suitable for charge-coupled devices, on the top view plane of the semiconductor device, including an active area and a terminal protection area on a semiconductor substrate, the active area is located in the central area of the semiconductor substrate, and the terminal protection area Located on the outer ring of the active region and surrounding the active region; on the cross-section of the semiconductor device, the semiconductor substrate has two corresponding main surfaces, the two main surfaces include the first main surface and the first main surface The second main surface corresponding to the surface, the first main surface of the semiconductor substrate and the second main surface include a drift region of the first conductivity type; it is characterized by: On the cross section of the semiconductor device, a second conductivity type second well region is provided in the first conductivity type drift region of the terminal protection region, and the second conductivity type second well region is located in the first conductivity type drift region In the upper part, a number of terminal grooves are provided in the terminal protection area, and the terminal grooves are located in the second well region of the second conductivity type, and extend deeply into the drift region of the first conductivity type below the second well region of the second conductivity type; The terminal trench is filled with a terminal dielectric body and a terminal conductor, and the terminal conductor is electrically connected to the second conductive type second well region adjacent to the active region outside the terminal trench. 2. The semiconductor structure suitable for charge-coupled devices according to claim 1, characterized in that: the terminal conductor is located in the central area of the terminal trench, and the terminal dielectric body surrounds the terminal conductor; A third well region of the second conductivity type is provided below the bottom of the termination trench, and the third well region of the second conductivity type covers the bottom of the termination trench. 3. The semiconductor structure suitable for a charge-coupled device according to claim 1, characterized in that: on the cross section of the semiconductor device, a second conductivity type first drift region is provided in the active region. Well region, the first well region of the second conductivity type is located in the upper part of the drift region of the first conductivity type; the cells in the active region adopt a trench structure, and the cell trenches are located in the first well region of the second conductivity type , protruding deeply into the drift region of the first conductivity type below the first well region of the second conductivity type, the central region in the cell trench is filled with a cell conductor and cells located at the outer ring of the cell conductor A dielectric body, an intracellular trench surrounding the cellular conductor is provided on the upper part of the cellular trench, an insulating gate oxide layer is grown in the intracellular trench, and an insulating gate oxide layer is grown in the cellular trench. The intracellular trenches of the layer are filled with gate conductive polysilicon; A source region of the first conductivity type is provided above the outer wall side of the adjacent cell trench, the source region of the first conductivity type is located in the first well region of the second conductivity type, and the source region of the first conductivity type is connected to the first well region of the second conductivity type The outer wall of the cell groove is in contact; a source metal is provided above the first main surface of the semiconductor substrate, and the source metal is electrically conductive with the source region of the first conductivity type, the first well region of the second conductivity type, and the cell Body ohmic contact, the cells in the active area are connected in parallel through the gate conductive polysilicon to form a whole. 4. The semiconductor structure suitable for charge-coupled devices according to claim 1, characterized in that: the semiconductor substrate further includes a substrate of a first conductivity type between the first main surface and the second main surface, and the first conductive type substrate is located below the drift region of the first conductivity type, and the substrate of the first conductivity type is adjacent to the drift region of the first conductivity type, and a drain metal is arranged on the substrate of the first conductivity type, and the drain metal is ohmic with the substrate of the first conductivity type touch. 5. The semiconductor structure suitable for a charge-coupled device according to claim 3, characterized in that: the cell trenches and terminal trenches are manufactured in the same process, and the adjacent cell trenches in the active region The spacing is the same, the distance between the cell groove adjacent to the terminal protection area and the terminal groove adjacent to the active area is not greater than the distance between adjacent cell grooves, and the distance between adjacent terminal grooves in the terminal protection area is the same or It gradually increases along the direction from the active area to the terminal protection area. 6 . The semiconductor structure suitable for charge-coupled devices according to claim 3 , characterized in that: the cellular dielectric body and the terminal dielectric body are manufactured layers in the same process. 7. A method for manufacturing a semiconductor structure suitable for a charge-coupled device, wherein the method for manufacturing a semiconductor device comprises the steps of: (a), providing a semiconductor substrate having two opposite main surfaces, the two opposite main surfaces include a first main surface and a second main surface corresponding to the first main surface, and between the first main surface and the second main surface includes a first conductivity type substrate and a first conductivity type drift region, the first conductivity type substrate is located below the first conductivity type drift region, and the first conductivity type substrate is adjacent to the first conductivity type drift region; (b) disposing a hard mask layer on the first main surface of the semiconductor substrate, selectively masking and etching the hard mask layer, so as to obtain the desired mask layer window penetrating the hard mask layer; (c) Groove etching is performed on the first main surface of the semiconductor substrate by using the mask layer window, so as to obtain the cell trench of the drift region of the first conductivity type located in the active region and the first cell trench located in the terminal protection region. Termination trenches in the conductivity type drift region; (d) removing the hard mask layer on the first main surface, and performing selective implantation of impurity ions of the second conductivity type on the first main surface of the semiconductor substrate to obtain the second conductivity type in the terminal protection area The second well region and the second conductivity type third well region, the second conductivity type second well region is located in the upper part of the first conductivity type drift region of the terminal protection region, and the second conductivity type third well region is located in the second conductivity type Below the second well region, and the third well region of the second conductivity type covers the bottom of the terminal trench; (e) filling the above-mentioned cell trenches and terminal trenches with dielectrics to obtain a cell dielectric body located in the cell trenches, a cell conductor filling hole formed in the central area of the cell trenches, a terminal dielectric body located in the terminal trench and a terminal conductor filling hole formed in the central area of the terminal trench; (f), filling the conductors in the above-mentioned cell conductor filling holes and terminal conductor filling holes, so as to obtain the cellular conductors located in the cell grooves and the terminal conductors located in the terminal grooves; (g) Etching the cellular dielectric body in the cellular trench to obtain an intracellular trench located at the upper part of the cellular trench; (h), setting the required insulating gate oxide layer and gate conductive polysilicon in the trench in the above cell; (i) selectively implanting impurity ions of the second conductivity type over the first main surface of the above-mentioned semiconductor substrate to obtain a first well region of the second conductivity type in the drift region of the first conductivity type in the active region; (j) selectively implanting impurity ions of the first conductivity type over the first main surface of the semiconductor substrate to obtain a source region of the first conductivity type in the first well region of the second conductivity type; (k), depositing an insulating dielectric layer on the first main surface of the above-mentioned semiconductor substrate, and performing contact hole etching on the insulating dielectric layer; (l) Depositing a front metal layer on the first main surface of the above-mentioned semiconductor substrate, and patterning the front metal layer, so as to obtain the source metal, gate metal and The terminal is connected to the metal, the source metal is in ohmic contact with the first well region of the second conductivity type, the source region of the first conductivity type and the cell conductor, the gate metal is electrically connected with the gate conductive polysilicon, and the terminal conductor is in contact with the cell conductor The second well region of the second conductivity type on the side adjacent to the active region outside the terminal trench is electrically connected through the terminal connection metal; (m) A drain metal is provided on the second main surface of the semiconductor substrate, and the drain metal is in ohmic contact with the substrate of the first conductivity type. 8. The method for manufacturing a semiconductor structure suitable for a charge-coupled device according to claim 7, wherein the spacing between adjacent cell trenches in the active region is the same, and the cell trenches adjacent to the terminal protection region are the same as those adjacent to the adjacent cell trenches. The distance between the terminal grooves in the active region is not greater than the distance between adjacent cell grooves, and the distance between adjacent terminal grooves in the terminal protection area is the same or increases gradually along the direction from the active area to the terminal protection area. 9 . The method for manufacturing a semiconductor structure suitable for a charge-coupled device according to claim 7 , wherein the material of the semiconductor substrate includes silicon. 10 . The method for manufacturing a semiconductor structure suitable for a charge-coupled device according to claim 7 , wherein the cell dielectric body and the terminal dielectric body are silicon dioxide. 11 .