CN221595639U - Terminal equipment for triggering hard disk detection - Google Patents

Abstract

The embodiment of the utility model discloses a terminal device for triggering hard disk detection, which comprises a box body, wherein a main board is arranged in the box body, a south bridge chip and a detection trigger circuit are arranged on the main board, and the detection trigger circuit is connected with the south bridge chip; and the detection trigger circuit detects a trigger signal of the output periodic pulse after power-on, and controls the south bridge chip to periodically detect the connection state of the hard disk according to the rising edge of the trigger signal. The trigger signal is based on periodic pulse, each period has a rising edge and is always generated after power-on, so that the connection state of the hard disk can be continuously detected when the terminal equipment works, whether the hard disk data is lost or not can be timely found, and the problem that the connection state of the hard disk cannot be detected when the existing terminal equipment works in a working mode is solved.

Description

Terminal equipment for triggering hard disk detection

Technical Field

The utility model relates to the technical field of electronics, in particular to terminal equipment for triggering hard disk detection.

Background

In the using process of the computer host, if the computer host is vibrated (if the computer host is knocked down), the hard disk line may be loosened or disconnected, so that the hard disk data is lost. Therefore, the client requires the computer to automatically detect and alarm, and the BIOS (basic input/output system ⁾) inside the south bridge chip detects the input/output device during the starting process, but after the computer host enters the OS (computer operating system, i.e. enters the working mode), the BIOS does not detect the connection state of the hard disk at this time after the BIOS has been detected during the starting process, and thus, the client cannot find whether the hard disk has a connection failure during the use process (i.e. after the BIOS has been detected), so that the hard disk data is lost, and the function of alarm loss cannot be realized.

Disclosure of utility model

Aiming at the technical problems, the embodiment of the utility model provides a terminal device for triggering hard disk detection, which aims to solve the problem that the existing terminal device cannot detect the connection state of a hard disk in a working mode.

The embodiment of the utility model provides a terminal device for triggering hard disk detection, which comprises a box body, wherein a main board is arranged in the box body, a south bridge chip is arranged on the main board, a detection trigger circuit is also arranged on the main board, and the detection trigger circuit is connected with the south bridge chip;

And the detection trigger circuit detects a trigger signal of the output periodic pulse after power-on, and controls the south bridge chip to periodically detect the connection state of the hard disk according to the rising edge of the trigger signal.

Optionally, in the terminal device for triggering hard disk detection, the detection triggering circuit includes a rising module and a falling module, where the rising module is connected with the falling module and the south bridge chip;

When the rising module detects the system voltage, a high-level trigger signal is output and the falling module is controlled to delay, and the falling module pulls down the trigger signal after the delay time is up;

The rising module also controls the falling module to delay according to the low-level trigger signal and then cut off, and the rising module outputs the high-level trigger signal again according to the system voltage and controls the falling module to delay.

Optionally, in the terminal device for triggering hard disk detection, the rising module includes a first switch tube, a first resistor and a first capacitor;

The grid electrode of the first switch tube is connected with one end of the first resistor, one end of the first capacitor and the descending module; the drain electrode of the first switching tube is connected with the falling module, the other end of the first resistor is input with system voltage, and the source electrode of the first switching tube and the other end of the first capacitor are grounded; one end of the first resistor outputs a trigger signal and is connected with the south bridge chip.

Optionally, in the terminal device for triggering hard disk detection, the dropping module includes a second switching tube, a third switching tube, a second resistor, a third resistor, a second capacitor and a third capacitor;

The grid electrode of the second switching tube is connected with one end of the second resistor, one end of the second capacitor and the drain electrode of the first switching tube; the drain electrode of the second switching tube is connected with the grid electrode of the third switching tube, one end of the third resistor and one end of the third capacitor; the drain electrode of the third switching tube is connected with one end of the first resistor, and the other end of the second resistor and the other end of the third resistor are both input with system voltage; the source electrode of the second switch tube, the source electrode of the third switch tube, the other end of the second capacitor and the other end of the third capacitor are grounded.

Optionally, in the terminal device for triggering hard disk detection, the first switching tube is an NMOS tube.

Optionally, in the terminal device for triggered hard disk detection, the resistance value of the first resistor is 100kΩ, and the capacitance value of the first capacitor is 0.1uF.

Optionally, in the terminal device for triggering hard disk detection, the second switching tube and the third switching tube are NMOS tubes.

Optionally, in the terminal device for triggered hard disk detection, the resistance values of the second resistor and the third resistor are 200kΩ.

Optionally, in the terminal device for triggering hard disk detection, the capacitance value of the second capacitor and the third capacitor is 10uF.

In the technical scheme provided by the embodiment of the utility model, the terminal equipment for triggering hard disk detection comprises a box body, wherein a main board is arranged in the box body, a south bridge chip and a detection trigger circuit are arranged on the main board, and the detection trigger circuit is connected with the south bridge chip; and the detection trigger circuit detects a trigger signal of the output periodic pulse after power-on, and controls the south bridge chip to periodically detect the connection state of the hard disk according to the rising edge of the trigger signal. The trigger signal is based on periodic pulse, each period has a rising edge and is always generated after power-on, so that the connection state of the hard disk can be continuously detected when the terminal equipment works, whether the hard disk data is lost or not can be timely found, and the problem that the connection state of the hard disk cannot be detected when the existing terminal equipment works in a working mode is solved.

Drawings

Fig. 1 is a block diagram of a motherboard according to an embodiment of the present utility model.

Fig. 2 is a schematic circuit diagram of a detection trigger circuit according to an embodiment of the utility model.

Fig. 3 is a schematic diagram of a simulation waveform of a trigger signal according to an embodiment of the present utility model.

Fig. 4 is a schematic diagram of timing waveforms of voltages on the trigger signal, the second capacitor and the third capacitor according to an embodiment of the present utility model.

Fig. 5 is a schematic circuit layout of a motherboard according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. Embodiments of the present utility model are intended to be within the scope of the present utility model as defined by the appended claims.

Referring to fig. 1, a terminal device for triggered hard disk detection provided in an embodiment of the present utility model includes a box, a main board is disposed in the box, a detection trigger circuit 10 and a south bridge chip 20 are disposed on the main board, the detection trigger circuit 10 is connected to the south bridge chip 20, the detection trigger circuit 10 detects a trigger signal pch_int that outputs a periodic pulse after being powered on, and controls the south bridge chip to periodically detect a connection state of a hard disk according to the trigger signal. When the south bridge chip 20 detects the rising edge of the trigger signal pch_int, the connection state of the hard disk is detected. Based on the trigger signal pch_int, a rising edge is provided for each period, and the rising edge is always generated after the terminal device is powered on, so that hard disk detection can be continuously performed after the terminal device is powered on, and the BIOS in the south bridge chip 20 can timely find whether hard disk data is lost or not.

In this embodiment, the terminal device is preferably a desktop computer, and the case is a case of a host computer. In the specific implementation, other devices with hard disk may also be provided with the detection trigger circuit 10 and the south bridge chip 20 on the main board. It should be understood that the main board is further provided with an existing power circuit for outputting a system voltage +3vs after the power-on key is pressed, and the system voltage +3vs is high in all of the power-on process, the working mode and the standby mode, and the specific circuit structure is not described in detail herein. The south bridge chip 20 is preferably adl_s_pch_ext_1p2, and detects the hard disk when the BIOS inside the south bridge chip detects the rising edge. In this embodiment, a periodic rising edge is mainly generated, and a connection state of a hard disk is periodically and repeatedly detected during a working period of a terminal device, so as to avoid data loss caused by poor connection.

The detection trigger circuit 10 includes a rising module 110 and a falling module 120, where the rising module is connected to the falling module and the south bridge chip; after the rising module 110 detects that the motherboard is powered on (at this time, the system voltage +3vs is generated), outputs a high-level trigger signal pch_int and controls the falling module 120 to delay, and the falling module 120 pulls down the trigger signal pch_int after the delay time is reached; the rising module 110 controls the falling module 120 to be cut off after being delayed according to the low-level trigger signal pch_int, and the rising module 110 outputs the high-level trigger signal pch_int again according to the system voltage +3vs. The trigger signal pch_int thus repeatedly goes high and low, i.e. becomes a corresponding periodic pulse signal with periodically varying rising and falling edges.

In this embodiment, as shown in fig. 2, the rising module 110 includes a first switching tube Q1, a first resistor R1, and a first capacitor C1; the gate of the first switch tube Q1 is connected to one end of the first resistor R1, one end of the first capacitor C1 and the falling module 120; the drain electrode of the first switching tube Q1 is connected with the falling module 120, the other end of the first resistor R1 is input with the system voltage +3VS, and the source electrode of the first switching tube Q1 and the other end of the first capacitor C1 are grounded; one end of the first resistor R1 outputs a trigger signal pch_int, and a pin gpp_e4/sata_ DEVSLP0 connected to the south bridge chip.

The first switching tube Q1 is preferably an NMOS tube with the model of L2N7002LT 1G. The first resistor R1 and the first capacitor C1 are used for delaying, the system voltage +3VS charges the C1 through the input of the R1, and the R1 can be limited to protect the C1. The resistance of the first resistor R1 is preferably 100kΩ, the capacitance of the first capacitor C1 is preferably 0.1uF, and when the system voltage +3vs is input, the voltage on the first capacitor C1 can rise rapidly, as shown in fig. 3 (a waveform diagram of the trigger signal pch_int simulation), so that the trigger signal pch_int becomes high level. As the trigger signal pch_int rises to the on voltage of the first switch Q1, Q1 is turned on, and the input terminal of the falling module 120 is pulled down. The output terminal of the falling module 120 controls the level of the trigger signal pch_int, and Q1 is turned off when the trigger signal pch_int is pulled down to a low level by the falling module 120, and the input terminal of the falling module 120 is not affected by Q1.

The falling module 120 includes a second switching tube Q2, a third switching tube Q3, a second resistor R2, a third resistor R3, a second capacitor C2, and a third capacitor C3; the gate of the second switching tube Q2 is connected to one end of the second resistor R2 (i.e. the input end of the falling module 120), one end of the second capacitor C2 and the drain of the first switching tube Q1; the drain electrode of the second switching tube Q2 is connected with the grid electrode of the third switching tube Q3, one end of the third resistor R3 and one end of the third capacitor C3; the drain electrode of the third switch tube Q3 (i.e. the output end of the falling module 120) is connected with one end of the first resistor R1, and the other end of the second resistor R2 and the other end of the third resistor R3 are both input with the system voltage +3vs; the source of the second switching tube Q2, the source of the third switching tube Q3, the other end of the second capacitor C2 and the other end of the third capacitor C3 are all grounded.

The second switching tube Q2 and the third switching tube Q3 are NMOS tubes with model L2N7002LT 1G. The second resistor R2 and the second capacitor C2 play a role in first time delay, and the third resistor R3 and the third capacitor C3 play a role in second time delay; the delay adopts a capacitor charging mode, namely, the system voltage +3VS charges the connected capacitor through the corresponding resistor input, R2 can be limited to protect C2, and R3 is limited to protect C3. In this embodiment, the resistance of the second resistor R2 and the third resistor R3 is preferably 200kΩ, and the capacitance of the second capacitor C2 and the third capacitor C3 is preferably 10uf.

As shown in fig. 4, in the first period T1, when the system voltage +3vs charges C1 and the trigger signal pch_int becomes high level, Q1 is turned on, the voltage RC1 (also the gate voltage of Q2) on the second capacitor C2 is directly pulled down to low level, Q2 is turned off, and at this time, the system voltage +3vs charges C3; the voltage RC2 (also the gate voltage of Q3) on the third capacitor C3 gradually rises, when the on condition of Q3 is reached, Q3 is turned on, the trigger signal pch_int is pulled down to a low level, the trigger signal pch_int of the low level turns Q1 off, the system voltage +3vs charges C2, the voltage RC1 on C2 gradually rises, when the on condition of Q2 is reached, Q2 is turned on to pull down the voltage RC2 on C3 to a low level, Q3 is turned off, and the first period T1 ends.

A second period T2 is entered. At this time, the level of the trigger signal pch_int is changed to the high level by charging C1 with the system voltage +3vs. The working principle of the first period T1 is repeated. And so on, thereby outputting the trigger signal pch_int of the periodic pulse.

Based on the smaller value of C1 and R1, the charging speed is higher, and the trigger signal PCH_INT can quickly become high level; the resistance values of C2, C3, R2 and R3 are large and the charging speed is slow, so that the gradually rising waveform shown in fig. 4 can be seen. Fig. 4 is a theoretical timing waveform diagram, and thus the radian of the rise and fall of the trigger signal pch_int does not show the radian shown in fig. 3.

With continued reference to fig. 1 to 3, the detection trigger circuit 10 operates according to the following principle:

after the system voltage +3VS is electrified, the trigger signal PCH_INT outputs a high level, the Q3 is conducted to pull down the RC2 voltage to a low level, the Q2 is cut off, the system voltage +3VS starts to charge C1, the grid voltage of the Q1 is gradually increased, when the system voltage +3VS is charged to the level that Q1 can be opened, the Q1 is conducted to pull down the trigger signal PCH_INT to the low level, at the moment, the Q3 is cut off, the system voltage +3VS starts to charge C2, when the system voltage +3VS is charged to the level that Q2 can be opened, the Q2 is conducted to discharge C1, the grid voltage of the Q1 is reduced to the level that Q1 is cut off, at the moment, the trigger signal PCH_INT is pulled up to the high level by the system voltage +3VS, and one period of the trigger signal PCH_INT is completed. The simulation waveform of the final trigger signal pch_int is shown in fig. 4, and the simulation waveform is 2.896S, 65.33S, and 2.64V. The hard disk detection is performed once every time the south bridge chip 20 detects a high level.

Fig. 5 shows only the positions of some important components on the motherboard, which are only examples, and can be laid out according to the requirements when the embodiment is implemented.

In summary, the terminal device for triggered hard disk detection provided by the utility model outputs the trigger signal of the periodic pulse to control the south bridge chip to periodically detect the connection state of the hard disk after power-on. Based on the trigger signal is a periodic pulse, each period has a rising edge and is always generated after power-on, so that the BIOS in the south bridge chip can be intermittently triggered to work after the terminal equipment is powered on, and the BIOS scans the input/output equipment again, so that the BIOS can timely find whether hard disk data is lost or not.

Compared with the existing circuit for outputting the periodic pulse signal by using the crystal oscillator, the frequency of the trigger signal generated by the utility model is not too high, and if the frequency is too high, the interrupt trigger detection is too frequent, so that too much CPU resource is occupied.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims (9)

1. The terminal equipment for triggering type hard disk detection comprises a box body, wherein a main board is arranged in the box body, and a south bridge chip is arranged on the main board;

And the detection trigger circuit detects a trigger signal of the output periodic pulse after power-on, and controls the south bridge chip to periodically detect the connection state of the hard disk according to the rising edge of the trigger signal.

2. The terminal device for triggering hard disk detection according to claim 1, wherein the detection triggering circuit comprises a rising module and a falling module, and the rising module is connected with the falling module and the south bridge chip;

When the rising module detects the system voltage, a high-level trigger signal is output and the falling module is controlled to delay, and the falling module pulls down the trigger signal after the delay time is up;

The rising module also controls the falling module to delay according to the low-level trigger signal and then cut off, and the rising module outputs the high-level trigger signal again according to the system voltage and controls the falling module to delay.

3. The terminal device for triggering hard disk detection as recited in claim 2, wherein the rising module includes a first switching tube, a first resistor and a first capacitor;

The grid electrode of the first switch tube is connected with one end of the first resistor, one end of the first capacitor and the descending module; the drain electrode of the first switching tube is connected with the falling module, the other end of the first resistor is input with system voltage, and the source electrode of the first switching tube and the other end of the first capacitor are grounded; one end of the first resistor outputs a trigger signal and is connected with the south bridge chip.

4. The terminal device for triggering hard disk detection according to claim 3, wherein the falling module comprises a second switching tube, a third switching tube, a second resistor, a third resistor, a second capacitor and a third capacitor;

The grid electrode of the second switching tube is connected with one end of the second resistor, one end of the second capacitor and the drain electrode of the first switching tube; the drain electrode of the second switching tube is connected with the grid electrode of the third switching tube, one end of the third resistor and one end of the third capacitor; the drain electrode of the third switching tube is connected with one end of the first resistor, and the other end of the second resistor and the other end of the third resistor are both input with system voltage; the source electrode of the second switch tube, the source electrode of the third switch tube, the other end of the second capacitor and the other end of the third capacitor are grounded.

5. The terminal device for triggering hard disk detection according to claim 3, wherein the first switching tube is an NMOS tube.

6. A terminal device for triggering hard disk detection according to claim 3, wherein the resistance of the first resistor is 100kΩ, and the capacitance of the first capacitor is 0.1uF.

7. The terminal device for triggered hard disk detection of claim 4, wherein the second switching tube and the third switching tube are NMOS tubes.

8. The terminal device for triggered hard disk detection of claim 4, wherein the second resistor and the third resistor have resistance values of 200kΩ.

9. The terminal device for triggered hard disk detection of claim 4, wherein the second capacitor and the third capacitor have a capacitance of 10uF.