CN116015267B - A power-on and power-off reset method and device for protecting low-voltage components of a chip - Google Patents

Abstract

The present invention discloses a power-on and power-off reset method and device for protecting low-voltage devices of a chip, wherein the method comprises the following steps: when the target chip is powered on, a first reset signal is generated by a power-on reset circuit, and a second reset signal is generated by a power-off reset circuit, if the voltage of the first reset signal is less than the voltage of the second reset signal, the first reset signal is output, otherwise the second reset signal is output; the output reset signal is timed by an oscillator, and the time is counted to a first preset time delay, and the low-voltage device in the target chip is started; when the time is counted to a second preset time delay, the internal integrated circuit in the target chip is started to initialize the target chip; after the initialization is completed, the internal integrated circuit generates an indication signal, and sends it to the power supply module of the low-voltage device through a pre-reset circuit, thereby starting the power supply module to supply low voltage to the low-voltage device. The present invention can well solve the overvoltage problem of internal low-voltage devices during the power-on and power-off process in multi-power domain applications.

Description

A power-on and power-off reset method and device for protecting low-voltage components of a chip

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a power-on and power-off reset method and device for protecting low-voltage components of a chip.

Background technique

Currently, many integrated circuits include a power-on-reset circuit (POR), which is used to ensure that analog and digital modules are initialized to a preset state after the integrated circuit is powered on.

For example, the invention patent with patent publication number CN103427812A discloses a power-on reset circuit and method thereof. The power-on reset circuit is arranged in a circuit system to perform a power-on reset operation on the circuit system. The power-on reset circuit includes: a voltage divider network circuit (I1) and a reset signal POR generating circuit (I2) connected thereto. The reset method includes the following steps: (1). The voltage divider network circuit divides the external power supply voltage Vdd1; (2). The reset signal POR generating circuit (I2) generates a reset signal with temperature compensation; (3). The circuit system receives the reset signal to perform a power-on reset, and sends a reset release signal to turn off the power-on reset circuit. The power-on reset circuit and method thereof provided by the invention can resist power supply voltage interference and jitter to a certain extent, and the temperature compensation function makes the reset circuit less affected by temperature. After the reset is completed, the power-on reset circuit automatically shuts down to achieve zero static power consumption.

For another example, the invention patent with patent publication number CN106357249A discloses a power-on reset circuit and an integrated circuit, the power-on reset circuit comprising: a first power-on module, outputting a first power-on signal; a first holding module, connected to the output end of the first power-on module, inputting the first power-on signal, and outputting a first reset signal; a second power-on module, connected to the output end of the first holding module, inputting the first reset signal, and outputting a second power-on signal; a second holding module, connected to the output end of the second power-on module, inputting the second power-on signal, and outputting a second reset signal. The invention improves the structure of the power-on reset circuit so that the power-on reset circuit can generate a reliable reset signal in both slow power-on and fast power-on conditions, thereby realizing power-on reset of the integrated circuit system.

However, conventional power-on reset circuits generate reset levels by comparing the power supply voltage with the reference voltage. Due to the uncertainty of the power-on time, the reset level is often not so certain. In addition, if the chip works in the high-voltage domain and low-voltage devices are used inside the chip, the low-voltage devices will usually be over-voltage during the power-on or power-off process.

Summary of the invention

In order to solve the above problems, the present invention proposes a power-on and power-off reset method and device for protecting chip low-voltage devices, which can well solve the overvoltage problem of internal low-voltage devices during power-on and power-off processes in multi-power domain applications.

The technical solution adopted by the present invention is as follows:

A power-on and power-off reset method for protecting low-voltage components of a chip comprises the following steps:

S1. When the target chip is powered on, a first reset signal is generated by a power-on reset circuit, and a second reset signal is generated by a power-off reset circuit. If the voltage of the first reset signal is less than the voltage of the second reset signal, the first reset signal is output, otherwise the second reset signal is output;

S2. The first reset signal or the second reset signal outputted in step S1 is timed by an oscillator until a first preset delay is reached, and the low-voltage device in the target chip is started;

S3. The oscillator is timed to a second preset delay, the internal integrated circuit in the target chip is started, and the target chip is initialized;

S4. After the initialization is completed, the internal integrated circuit generates an indication signal and sends it to the power supply module of the low-voltage device through the pre-reset circuit, thereby starting the power supply module to provide low-voltage power to the low-voltage device.

Furthermore, the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device.

Furthermore, the power-off reset circuit includes a MOS tube, a first resistor and a third inverter, the gate and drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to a power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit.

Furthermore, the low voltage device includes a low voltage dropout linear regulator.

Further, the oscillator is configured to be automatically turned off after the initialization is completed.

A power-on and power-off reset device for protecting low-voltage devices of a chip, comprising a power-on reset circuit, a power-off reset circuit, a pre-reset circuit and an oscillator, wherein the signal output ends of the power-on reset circuit and the power-off reset circuit are electrically connected to the oscillator, the low-voltage device in the target chip and an internal integrated circuit, the signal input end of the pre-reset circuit is electrically connected to the internal integrated circuit, and the signal output end of the pre-reset circuit is electrically connected to a power supply module of the low-voltage device.

Furthermore, the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device.

Furthermore, the power-off reset circuit includes a MOS tube, a first resistor and a third inverter, the gate and drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to a power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit.

Furthermore, the low voltage device includes a low voltage dropout linear regulator.

Further, the oscillator is configured to be automatically turned off after the initialization is completed.

The beneficial effects of the present invention are:

(1) The power-on time of each module can be selected according to the actual application, that is, the first preset delay and the second preset delay;

(2) A power-off reset circuit is added to prevent the conventional power-on reset circuit from not working properly when the chip is powered on from a non-0 level;

(3) A pre-reset circuit is added to ensure the connection control between the power domains, and it can work normally regardless of the power supply power-on sequence. This function can be extended to more power domains, and the pre-reset process can be used in the same way.

In summary, the present invention can strictly control the working or shut-down time of each module, and at the same time, in different power domains, the pre-reset is performed through the pull-down resistor, which can ensure that the internal low-voltage components can be well protected in the power-on sequence of different power supplies. In addition, the existing power-on reset circuit must be powered on at a very low voltage to generate a reset signal. The present invention adds a power-off reset module, and the chip can also perform the power-on reset work more smoothly when it is powered on from a non-zero power supply.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a block diagram of a power-on and power-off timing sequence according to an embodiment of the present invention.

FIG. 2 is a block diagram of a power-on and power-off timing sequence according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a power-off reset circuit according to an embodiment of the present invention.

Detailed ways

In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

Example 1

This embodiment provides a power-on and power-off reset method for protecting low-voltage components of a chip, as shown in FIG. 1 and FIG. 2 , including the following steps:

S1. When the target chip is powered on, a first reset signal is generated through a power-on reset circuit (POR, Power-on-Reset), and a second reset signal is generated through a power-off reset circuit. If the voltage of the first reset signal is less than the voltage of the second reset signal, the first reset signal is output, otherwise the second reset signal is output. This embodiment adds a power-off reset circuit on the basis of a conventional power-on reset circuit, generates a reset signal and performs an "AND" logic with the reset signal of the power-on reset circuit, and is used to reset below a set value, so as to ensure that the reset signal is generated more stably during the next power-on process from a non-0 level.

S2. The first reset signal or the second reset signal outputted in step S1 is timed by an oscillator (OSC), and when the time reaches a first preset delay Delay1, the low-voltage device in the target chip is started. The first preset delay Delay1 is used to ensure the stability of the bias circuit of the target chip. Preferably, the low-voltage device can be a low dropout regulator (LDO).

S3. The oscillator times to a second preset time delay Delay2, starts the internal integrated circuit (I2C) in the target chip, and initializes the target chip. The second preset time delay Delay2 is used to ensure the stability of the low-voltage device. Preferably, the oscillator is configured to automatically shut down after the target chip is initialized, thereby saving power consumption.

S4. After the initialization is completed, the internal integrated circuit generates an indication signal and sends it to the power supply module of the low-voltage device (i.e., LDO_core in Figure 1) through the pre-reset circuit, thereby starting the power supply module to provide low-voltage power to the low-voltage device. Since the power supply domain of the low-voltage device is different from the power supply domain of the power-on reset circuit, a two-stage inverter is connected in series, and a pull-down resistor is used for pre-reset processing. In this way, it can be ensured that no matter what the power-on sequence of the first power supply VDDIN and the second power supply VDD_ANA is, the start-up timing of the power supply module can be well controlled.

In this embodiment, the power-on reset circuit can be implemented using a general structure.

Preferably, as shown in Figure 3, the power-off reset circuit includes a MOS tube, a first resistor and a third inverter, the gate and drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to the power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit.

Preferably, the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device. As shown in Figure 1, the power supply INV1 of the first inverter is the first power supply VDDIN, and the power supply INV2 of the second inverter is the second power supply VDD_ANA.

Example 2

This embodiment is based on embodiment 1:

This embodiment provides a power-on and power-off reset device for protecting low-voltage devices of a chip, including a power-on reset circuit, a power-off reset circuit, a pre-reset circuit and an oscillator, the signal output ends of the power-on reset circuit and the power-off reset circuit are electrically connected to the oscillator, the low-voltage device in the target chip and the internal integrated circuit, the signal input end of the pre-reset circuit is electrically connected to the internal integrated circuit, and the signal output end of the pre-reset circuit is electrically connected to the power supply module of the low-voltage device. In this embodiment, the power-on reset circuit can be implemented using a general structure.

This embodiment adds a power-off reset circuit on the basis of a conventional power-on reset circuit, generates a reset signal and performs an "AND" logic with the reset signal of the power-on reset circuit, and is used to reset below a set value, so as to ensure that the reset signal is generated more stably during the next power-on process from a non-0 level. Preferably, as shown in FIG3 , the power-off reset circuit includes a MOS tube, a first resistor and a third inverter, the gate and drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to the power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit.

Since the power supply domain of the low-voltage device is different from the power supply domain of the power-on reset circuit, the present embodiment adopts two-stage inverters in series, and uses a pull-down resistor for pre-reset processing, so that it can be ensured that no matter how the power-on sequence of the first power supply VDDIN and the second power supply VDD_ANA is, the start-up timing of the power supply module can be well controlled. Preferably, the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device. As shown in Figure 1, the power supply INV1 of the first inverter is the first power supply VDDIN, and the power supply INV2 of the second inverter is the second power supply VDD ANA.

The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims (9)

1. A power-on and power-off reset method for protecting low-voltage components of a chip, characterized in that it comprises the following steps: S1. When the target chip is powered on, a first reset signal is generated by a power-on reset circuit, and a second reset signal is generated by a power-off reset circuit. If the voltage of the first reset signal is less than the voltage of the second reset signal, the first reset signal is output, otherwise the second reset signal is output; S2. The first reset signal or the second reset signal outputted in step S1 is timed by an oscillator until a first preset delay time is reached, and the low-voltage device in the target chip is started; S3. The oscillator is timed to a second preset delay, the internal integrated circuit in the target chip is started, and the target chip is initialized; S4. After the initialization is completed, the internal integrated circuit generates an indication signal and sends it to the power supply module of the low-voltage device through the pre-reset circuit, thereby starting the power supply module to provide low-voltage power to the low-voltage device; The power-off reset circuit includes a MOS tube, a first resistor and a third inverter, the gate and the drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to a power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit. 2. The power-on and power-off reset method for protecting chip low-voltage devices according to claim 1 is characterized in that the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device. 3. The power-on and power-off reset method for protecting a chip low-voltage device according to claim 1 or 2, wherein the low-voltage device comprises a low-dropout linear regulator. 4. The power-on/power-off reset method for protecting chip low-voltage devices according to claim 1 or 2, characterized in that the oscillator is configured to automatically shut down after the initialization is completed. 5. A power-on and power-off reset device for protecting low-voltage devices of a chip, used to implement the steps of the power-on and power-off reset method described in claim 1, characterized in that the power-on and power-off reset device comprises a power-on reset circuit, a power-off reset circuit, a pre-reset circuit and an oscillator, the signal output ends of the power-on reset circuit and the power-off reset circuit are electrically connected to the oscillator, the low-voltage devices in the target chip and the internal integrated circuit, the signal input end of the pre-reset circuit is electrically connected to the internal integrated circuit, and the signal output end of the pre-reset circuit is electrically connected to the power supply module of the low-voltage device. 6. According to claim 5, the power-on and power-off reset device for protecting chip low-voltage devices is characterized in that the pre-reset circuit includes a first inverter, a second inverter and a pull-down resistor, the signal input end of the first inverter is electrically connected to the internal integrated circuit, the signal output end of the first inverter is electrically connected to the first end of the pull-down resistor and the signal input end of the second inverter, the second end of the pull-down resistor is grounded, and the signal output end of the second inverter is electrically connected to the low-voltage device. 7. The power-on and power-off reset device for protecting chip low-voltage devices according to claim 5 is characterized in that the power-off reset circuit comprises a MOS tube, a first resistor and a third inverter, the gate and drain of the MOS tube are electrically connected to the first end of the first resistor and the signal input end of the third inverter, the second end of the first resistor is connected to a power supply, and the signal output end of the third inverter is electrically connected to the power-on reset circuit, the low-voltage device and the internal integrated circuit. 8. The power-on and power-off reset device for protecting a chip low-voltage device according to any one of claims 5 to 7, wherein the low-voltage device comprises a low-dropout linear regulator. 9. The power-on/power-off reset device for protecting low-voltage components of a chip according to any one of claims 5 to 7, characterized in that the oscillator is configured to automatically shut down after the initialization is completed.