CN116647216B - Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence - Google Patents
Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence Download PDFInfo
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Abstract
本发明公开了一种解决POR和LDO上电顺序的方法、电路、锁相环及芯片，其中电路包括低压差线性稳压器、上电复位电路、反相器、第一MOS管、第二MOS管、第一电阻、第二电阻和第三电阻，低压差线性稳压器的信号输入端、第一电阻的第一端、第二MOS管的源极接入工作电压VDD；第一MOS管的栅极连接低压差线性稳压器的信号输出端，漏极连接第一电阻的第二端和第二MOS管的栅极，源极接地。本发明通过第一电阻作为上拉电阻使第二MOS管保持初始关断状态，再通过低压差线性稳压器的输出信号控制第一MOS管的栅极，使低压差线性稳压器输出稳定后上电复位电路再进行输出，从而确保正确的上电时序。
The present invention discloses a method, circuit, phase-locked loop and chip for solving the power-on sequence of POR and LDO, wherein the circuit includes a low voltage difference linear regulator, a power-on reset circuit, an inverter, a first MOS tube, a second MOS tube, a first resistor, a second resistor and a third resistor, the signal input end of the low voltage difference linear regulator, the first end of the first resistor and the source of the second MOS tube are connected to the working voltage VDD; the gate of the first MOS tube is connected to the signal output end of the low voltage difference linear regulator, the drain is connected to the second end of the first resistor and the gate of the second MOS tube, and the source is grounded. The present invention uses the first resistor as a pull-up resistor to keep the second MOS tube in an initial off state, and then controls the gate of the first MOS tube through the output signal of the low voltage difference linear regulator, so that the power-on reset circuit outputs after the output of the low voltage difference linear regulator is stable, thereby ensuring the correct power-on timing.
Description
技术领域Technical Field
本发明涉及时钟芯片设计技术领域，尤其涉及一种解决POR和LDO上电顺序的方法、电路、锁相环及芯片。The present invention relates to the technical field of clock chip design, and in particular to a method, circuit, phase-locked loop and chip for solving the power-on sequence of POR and LDO.
背景技术Background technique
在时钟芯片设计中，正确可靠的上电时序决定芯片是否能正常的工作。这就需要POR(Power On Reset)来进行上电复位，电源VDD上电初期产生一个复位信号(RESET信号)，初始化整个系统芯片，当VDD足够高时，POR跟随电源电压输出，使各模块正常工作，当VDD下降至足够低时，POR输出低即RESET信号，复位整个芯片电路。In the design of clock chips, the correct and reliable power-on timing determines whether the chip can work normally. This requires POR (Power On Reset) to perform power-on reset. A reset signal (RESET signal) is generated at the beginning of power-on of the power supply VDD to initialize the entire system chip. When VDD is high enough, POR follows the power supply voltage output to enable each module to work normally. When VDD drops to a low enough level, POR outputs a low RESET signal to reset the entire chip circuit.
在数字模块需要用到LDO(低压差线性稳压器)的情形时，需要保证数字的LDO稳定后再输出POR为高。这时无法确定是POR先拉起还是LDO先稳定，通常可以用计数器计数来延迟POR拉起，但延迟时间随VDD上电时间和PVT(Process Voltage Temperature，工艺电压温度)的影响，往往无法给出准确的延迟时间。When a digital module needs to use LDO (low dropout linear regulator), it is necessary to ensure that the digital LDO is stable before outputting POR high. At this time, it is impossible to determine whether POR is pulled up first or LDO is stable first. Usually, a counter can be used to delay POR pulling up, but the delay time is affected by VDD power-on time and PVT (Process Voltage Temperature), and it is often impossible to give an accurate delay time.
发明内容Summary of the invention
为了解决上述问题，本发明提出一种解决POR和LDO上电顺序的方法、电路、锁相环及芯片，通过增加第一电阻作为上拉电阻使第二MOS管保持初始关断状态，再通过低压差线性稳压器的输出信号控制第一MOS管的栅极，使低压差线性稳压器输出稳定后上电复位电路再进行输出，从而确保正确的上电时序。In order to solve the above problems, the present invention proposes a method, circuit, phase-locked loop and chip for solving the POR and LDO power-on sequence, by adding a first resistor as a pull-up resistor to keep the second MOS tube in an initial off state, and then controlling the gate of the first MOS tube by the output signal of the low-voltage difference linear regulator, so that the power-on reset circuit outputs again after the output of the low-voltage difference linear regulator is stable, thereby ensuring the correct power-on timing.
本发明采用的技术方案如下：The technical solution adopted by the present invention is as follows:
一种解决POR和LDO上电顺序的电路，包括低压差线性稳压器、上电复位电路、反相器、第一MOS管、第二MOS管、第一电阻、第二电阻和第三电阻，所述低压差线性稳压器的信号输入端、第一电阻的第一端、第二MOS管的源极接入工作电压VDD；所述第一MOS管的栅极连接低压差线性稳压器的信号输出端，漏极连接第一电阻的第二端和第二MOS管的栅极，源极接地；所述第二MOS管的漏极连接第二电阻的第一端，所述第二电阻的第二端连接第三电阻的第一端和反相器的输入端，所述反相器的输出端连接上电复位电路，所述第三电阻的第二端接地；通过所述第一电阻作为上拉电阻使第二MOS管保持初始关断状态，再通过所述低压差线性稳压器的输出信号控制第一MOS管的栅极，使低压差线性稳压器输出稳定后上电复位电路再进行输出。A circuit for solving the power-on sequence of POR and LDO comprises a low voltage difference linear regulator, a power-on reset circuit, an inverter, a first MOS tube, a second MOS tube, a first resistor, a second resistor and a third resistor, wherein the signal input end of the low voltage difference linear regulator, the first end of the first resistor and the source of the second MOS tube are connected to an operating voltage VDD; the gate of the first MOS tube is connected to the signal output end of the low voltage difference linear regulator, the drain is connected to the second end of the first resistor and the gate of the second MOS tube, and the source is grounded; the drain of the second MOS tube is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor and the input end of the inverter, the output end of the inverter is connected to the power-on reset circuit, and the second end of the third resistor is grounded; the first resistor is used as a pull-up resistor to keep the second MOS tube in an initial off state, and then the gate of the first MOS tube is controlled by the output signal of the low voltage difference linear regulator, so that the power-on reset circuit outputs again after the output of the low voltage difference linear regulator is stable.
进一步地，通过调节第一电阻和第一MOS管的尺寸使基准电压VREF输出稳定后，第一MOS管的下拉能力大于第一电阻的上拉能力，即第一MOS管的导通电阻Ron小于第一电阻，第二MOS管开始导通，反相器、第一电阻和第二电阻的连接点电压开始上升，上升到反相器的阈值电压时，上电复位电路开始输出。Furthermore, after the reference voltage V REF output is stabilized by adjusting the sizes of the first resistor and the first MOS tube, the pull-down capability of the first MOS tube is greater than the pull-up capability of the first resistor, that is, the on-resistance R on of the first MOS tube is less than the first resistor, the second MOS tube starts to be turned on, and the voltage at the connection point of the inverter, the first resistor and the second resistor starts to rise. When it rises to the threshold voltage of the inverter, the power-on reset circuit starts to output.
进一步地，所述第一MOS管的导通电阻Ron的计算方法包括：Furthermore, the calculation method of the on-resistance R on of the first MOS tube includes:
其中，L表示第一MOS管的栅长，W表示第一MOS管的栅宽，μn表示第一MOS管的迁移率，Cox表示单位面积栅氧化层电容，Vgs表示第一MOS管的栅源电压，Vt表示第一MOS管的阈值电压。Wherein, L represents the gate length of the first MOS tube, W represents the gate width of the first MOS tube, μ n represents the mobility of the first MOS tube, Cox represents the gate oxide capacitance per unit area, Vgs represents the gate-source voltage of the first MOS tube, and Vt represents the threshold voltage of the first MOS tube.
一种高性能锁相环，包括上述解决POR和LDO上电顺序的电路。A high performance phase-locked loop comprises the circuit for solving the power-on sequence of POR and LDO.
一种时钟芯片，包括上述高性能锁相环。A clock chip comprises the above-mentioned high-performance phase-locked loop.
一种解决POR和LDO上电顺序的方法，包括以下步骤：A method for solving the power-on sequence of POR and LDO includes the following steps:
步骤S1.当工作电压VDD开始上电时，第一MOS管的栅极处基准电压VREF开始上升；第一MOS管处于关断状态，将第一MOS管的漏极、第二MOS管的栅极和第一电阻第二端的连接点记为A点，则A点将被第一电阻上拉跟随工作电压VDD变化，此时第二MOS管的栅源电压为零，处于关断状态，上电复位电路输出为0；Step S1. When the working voltage VDD starts to be powered on, the reference voltage V REF at the gate of the first MOS tube starts to rise; the first MOS tube is in the off state, and the connection point of the drain of the first MOS tube, the gate of the second MOS tube and the second end of the first resistor is recorded as point A, then point A will be pulled up by the first resistor to follow the change of the working voltage VDD, at this time, the gate-source voltage of the second MOS tube is zero, it is in the off state, and the output of the power-on reset circuit is 0;
步骤S2.当基准电压VREF上升到第一MOS管的阈值电压Vth后，第一MOS管导通，A点开始下拉，第一MOS管的导通电阻Ron随基准电压VREF上升而减小；Step S2. When the reference voltage V REF rises to the threshold voltage V th of the first MOS tube, the first MOS tube is turned on, point A starts to pull down, and the on-resistance R on of the first MOS tube decreases as the reference voltage V REF rises;
步骤S3.通过调节第一电阻和第一MOS管的尺寸使基准电压VREF输出稳定后，第一MOS管的下拉能力大于第一电阻的上拉能力时，A点被下拉至0，第二MOS管开始导通，反相器、第一电阻和第二电阻的连接点即B点的电压开始上升，上升到反相器的阈值电压时，上电复位电路的输出上拉至工作电压VDD。Step S3. After the reference voltage VREF output is stabilized by adjusting the sizes of the first resistor and the first MOS tube, when the pull-down capability of the first MOS tube is greater than the pull-up capability of the first resistor, point A is pulled down to 0, the second MOS tube starts to conduct, and the voltage of point B, the connection point of the inverter, the first resistor and the second resistor, starts to rise. When it rises to the threshold voltage of the inverter, the output of the power-on reset circuit is pulled up to the operating voltage VDD.
进一步地，步骤S3中，第一MOS管的下拉能力大于第一电阻的上拉能力时，第一MOS管的导通电阻Ron小于第一电阻。Further, in step S3, when the pull-down capability of the first MOS transistor is greater than the pull-up capability of the first resistor, the on-resistance R on of the first MOS transistor is less than the first resistor.
进一步地，第一MOS管的导通电阻Ron的计算方法包括：Furthermore, the calculation method of the on-resistance R on of the first MOS tube includes:
其中，L表示第一MOS管的栅长，W表示第一MOS管的栅宽，μn表示第一MOS管的迁移率，Cox表示单位面积栅氧化层电容，Vgs表示第一MOS管的栅源电压，Vt表示第一MOS管的阈值电压。Wherein, L represents the gate length of the first MOS tube, W represents the gate width of the first MOS tube, μ n represents the mobility of the first MOS tube, Cox represents the gate oxide capacitance per unit area, Vgs represents the gate-source voltage of the first MOS tube, and Vt represents the threshold voltage of the first MOS tube.
一种高性能锁相环，基于上述解决POR和LDO上电顺序的方法。A high performance phase locked loop is provided based on the above method for solving the power-on sequence of POR and LDO.
一种时钟芯片，包括上述高性能锁相环。A clock chip comprises the above-mentioned high-performance phase-locked loop.
本发明的有益效果在于：The beneficial effects of the present invention are:
本发明通过增加第一电阻作为上拉电阻使第二MOS管保持初始关断状态，再通过低压差线性稳压器的输出信号控制第一MOS管的栅极，使低压差线性稳压器输出稳定后上电复位电路再进行输出，从而确保正确的上电时序。The present invention increases a first resistor as a pull-up resistor to keep the second MOS tube in an initial off state, and then controls the gate of the first MOS tube through the output signal of a low voltage difference linear regulator, so that the power-on reset circuit outputs after the output of the low voltage difference linear regulator is stable, thereby ensuring a correct power-on timing.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是POR先于LDO拉起的波形示意图。Figure 1 is a waveform diagram showing that POR is pulled up before LDO.
图2是实施例1的解决POR和LDO上电顺序的电路原理图。FIG. 2 is a schematic diagram of a circuit for solving the power-on sequence of POR and LDO according to Embodiment 1.
图3是实施例1的POR和LDO输出波形示意图。FIG. 3 is a schematic diagram of POR and LDO output waveforms of Example 1.
具体实施方式Detailed ways
为了对本发明的技术特征、目的和效果有更加清楚的理解，现说明本发明的具体实施方式。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明，即所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.
实施例1Example 1
如图1所示，当上电复位电路POR在A点拉起时，低压差线性稳压器LDO还未稳定，导致数字使能错误。虽然可以通过计数器延时上电复位电路POR的拉起时间，保证低压差线性稳压器LDO稳定，但延迟时间设置太少则余量不够，而上电的时间也有严格要求；延迟时间设置太多，则会浪费上电时间。As shown in Figure 1, when the power-on reset circuit POR is pulled up at point A, the low-dropout linear regulator LDO is not stable yet, resulting in a digital enable error. Although the pull-up time of the power-on reset circuit POR can be delayed by a counter to ensure the stability of the low-dropout linear regulator LDO, if the delay time is set too short, the margin is insufficient, and the power-on time also has strict requirements; if the delay time is set too long, the power-on time will be wasted.
基于此，本实施例提供了一种解决POR和LDO上电顺序的电路，无需计数器，如图1所示，该电路包括低压差线性稳压器LDO、上电复位电路POR、反相器、第一MOS管M1、第二MOS管M2、第一电阻R1、第二电阻R2和第三电阻R3，低压差线性稳压器LDO的信号输入端、第一电阻R1的第一端、第二MOS管M2的源极接入工作电压VDD；第一MOS管M1的栅极连接低压差线性稳压器LDO的信号输出端，漏极连接第一电阻R1的第二端和第二MOS管M2的栅极，源极接地；第二MOS管M2的漏极连接第二电阻R2的第一端，第二电阻R2的第二端连接第三电阻R3的第一端和反相器的输入端，反相器的输出端连接上电复位电路POR，第三电阻R3的第二端接地。Based on this, the present embodiment provides a circuit for solving the power-on sequence of POR and LDO without a counter. As shown in FIG1 , the circuit includes a low voltage difference linear regulator LDO, a power-on reset circuit POR, an inverter, a first MOS tube M1, a second MOS tube M2, a first resistor R1, a second resistor R2 and a third resistor R3. The signal input end of the low voltage difference linear regulator LDO, the first end of the first resistor R1 and the source of the second MOS tube M2 are connected to the working voltage VDD; the gate of the first MOS tube M1 is connected to the signal output end of the low voltage difference linear regulator LDO, the drain is connected to the second end of the first resistor R1 and the gate of the second MOS tube M2, and the source is grounded; the drain of the second MOS tube M2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the input end of the inverter, the output end of the inverter is connected to the power-on reset circuit POR, and the second end of the third resistor R3 is grounded.
该电路通过第一电阻R1作为上拉电阻使第二MOS管M2保持初始关断状态，再通过低压差线性稳压器LDO的输出信号控制第一MOS管M1的栅极，使低压差线性稳压器LDO输出稳定后上电复位电路POR再进行输出。The circuit uses the first resistor R1 as a pull-up resistor to keep the second MOS tube M2 in an initial off state, and then controls the gate of the first MOS tube M1 through the output signal of the low voltage difference linear regulator LDO, so that the power-on reset circuit POR outputs again after the output of the low voltage difference linear regulator LDO is stable.
同时，本实施例提供了一种解决POR和LDO上电顺序的方法，包括以下步骤：At the same time, this embodiment provides a method for solving the power-on sequence of POR and LDO, including the following steps:
步骤S1.当工作电压VDD开始上电时，第一MOS管M1的栅极处基准电压VREF开始上升；第一MOS管M1处于关断状态，将第一MOS管M1的漏极、第二MOS管M2的栅极和第一电阻R1第二端的连接点记为A点，则A点将被第一电阻R1上拉跟随工作电压VDD变化，此时第二MOS管M2的栅源电压为零，处于关断状态，上电复位电路POR输出为0；Step S1. When the working voltage VDD starts to be powered on, the reference voltage V REF at the gate of the first MOS tube M1 starts to rise; the first MOS tube M1 is in the off state, and the connection point of the drain of the first MOS tube M1, the gate of the second MOS tube M2 and the second end of the first resistor R1 is recorded as point A, then point A will be pulled up by the first resistor R1 to follow the change of the working voltage VDD, at this time, the gate-source voltage of the second MOS tube M2 is zero, it is in the off state, and the power-on reset circuit POR output is 0;
步骤S2.当基准电压VREF上升到第一MOS管M1的阈值电压Vth后，第一MOS管M1导通，A点开始下拉，第一MOS管M1的导通电阻Ron随基准电压VREF上升而减小；Step S2. When the reference voltage V REF rises to the threshold voltage V th of the first MOS tube M1 , the first MOS tube M1 is turned on, point A starts to pull down, and the on-resistance R on of the first MOS tube M1 decreases as the reference voltage V REF rises;
步骤S3.通过调节第一电阻R1和第一MOS管M1的尺寸使基准电压VREF输出稳定后，第一MOS管M1的下拉能力大于第一电阻R1的上拉能力时，A点被下拉至0，第二MOS管M2开始导通，反相器、第一电阻R1和第二电阻R2的连接点即B点的电压开始上升，上升到反相器的阈值电压时，上电复位电路POR的输出上拉至工作电压VDD。Step S3. After the reference voltage VREF output is stabilized by adjusting the sizes of the first resistor R1 and the first MOS tube M1, when the pull-down capability of the first MOS tube M1 is greater than the pull-up capability of the first resistor R1, point A is pulled down to 0, the second MOS tube M2 starts to be turned on, and the voltage of point B, the connection point of the inverter, the first resistor R1 and the second resistor R2, starts to rise. When it rises to the threshold voltage of the inverter, the output of the power-on reset circuit POR is pulled up to the operating voltage VDD.
优选地，步骤S3中，第一MOS管M1的下拉能力大于第一电阻R1的上拉能力时，第一MOS管M1的导通电阻Ron小于第一电阻R1。Preferably, in step S3, when the pull-down capability of the first MOS transistor M1 is greater than the pull-up capability of the first resistor R1, the on-resistance R on of the first MOS transistor M1 is smaller than the first resistor R1.
更为优选地，第一MOS管M1的导通电阻Ron的计算方法如下：More preferably, the on-resistance R on of the first MOS tube M1 is calculated as follows:
其中，L表示第一MOS管M1的栅长，W表示第一MOS管M1的栅宽，μn表示第一MOS管M1的迁移率，Cox表示单位面积栅氧化层电容，Vgs表示第一MOS管M1的栅源电压，Vt表示第一MOS管M1的阈值电压。Wherein, L represents the gate length of the first MOS tube M1, W represents the gate width of the first MOS tube M1, μ n represents the mobility of the first MOS tube M1, Cox represents the gate oxide capacitance per unit area, Vgs represents the gate-source voltage of the first MOS tube M1, and Vt represents the threshold voltage of the first MOS tube M1.
如图3所示为改进后的POR输出波形，可以看出A点先被第一电阻R1上拉跟随工作电压VDD变化，当第一MOS管M1导通且下拉电阻小于第一电阻R1时，A点被下拉到0，第二MOS管M2打开，上电复位电路POR开始输出。FIG3 is an improved POR output waveform. It can be seen that point A is first pulled up by the first resistor R1 to follow the change of the working voltage VDD. When the first MOS tube M1 is turned on and the pull-down resistance is less than the first resistor R1, point A is pulled down to 0, the second MOS tube M2 is turned on, and the power-on reset circuit POR starts to output.
实施例2Example 2
本实施例在实施例1的基础上：This embodiment is based on embodiment 1:
本实施例提供了一种高性能锁相环，包括实施例1的解决POR和LDO上电顺序的电路。This embodiment provides a high-performance phase-locked loop, including the circuit for solving the POR and LDO power-on sequence of embodiment 1.
实施例3Example 3
本实施例在实施例2的基础上：This embodiment is based on Embodiment 2:
本实施例提供了一种时钟芯片，包括实施例2的高性能锁相环。This embodiment provides a clock chip, including the high-performance phase-locked loop of Embodiment 2.
以上所述仅是本发明的优选实施方式，应当理解本发明并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围，则都应在本发明所附权利要求的保护范围内。The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.
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