CN221509562U

CN221509562U - Circuit for pulse digital interference

Info

Publication number: CN221509562U
Application number: CN202323614241.9U
Authority: CN
Inventors: 李继; 李刚
Original assignee: Chengdu Basansiyi Information Technology Co ltd
Current assignee: Chengdu Basansiyi Information Technology Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-08-09
Anticipated expiration: 2033-12-28

Abstract

The utility model discloses a circuit for pulse digital interference, wherein an FPGA, an I-path DAC error correction circuit, a Q-path DAC error correction circuit, a 90-degree bridge and a summing circuit form a I Q signal correction circuit; the DDS chip, the phase-locked loop voltage-controlled oscillation source, the analog switch, the RF switch, the low-pass filter, the amplifier and the attenuator form a random pulse generation circuit; the I Q signal correction circuit and the random pulse generation circuit form a random I Q modulation signal circuit. According to the scheme, the digital modulation RF signal is used as a carrier wave of high-speed switch pulse modulation, the FPGA outputs random continuous switch pulses with certain frequency to be loaded on the digital RF signal, and the synthesized digital modulation signal and the pulse signal are transmitted together. The transmitted RF signal contains digital modulation wave and pulse wave which interfere with the wireless signal, and has double suppression shielding effect on the wireless signal.

Description

Circuit for pulse digital interference

Technical Field

The utility model belongs to the technical field of electronic circuits, and particularly relates to a circuit for pulse digital interference.

Background

With the use of wireless electronic devices becoming more frequent, the problem of illegal use of electronic devices becomes more serious, especially the problem of illegal interception and illegal use of wireless communication devices, and for the problem of illegal interception and illegal use of wireless communication devices, the problem of poor shielding effect of conventional interference shielding devices exists, and the pulse digital interference device meets the development requirement.

The pulse digital jammer mainly generates 4 kinds of interference signals: impulse interference, random digital modulation signal interference, dot frequency interference and sweep frequency interference: 1) Impulse interference. And generating a pulse interference signal with random frequency in a target frequency range, locking the target frequency, and outputting a random interference pulse modulation signal to form suppression of a wireless communication signal. 2) Random digital modulation signal interference. The digital modulation signal interference signals with random frequencies are generated in the target frequency range, the target frequency is annihilated, the signal to noise ratio is reduced, and normal communication is suppressed. 3) And point frequency interference. With the target frequency known, the interference signal is output aiming at the target frequency, producing a suppressing effect on the target communication. 4) And frequency sweep interference. And frequency scanning is carried out in a target frequency range, and when the collision probability of the interference signal frequency and the communication frequency reaches a certain value, the signal to noise ratio of communication is affected, so that the error rate is increased, and effective interference is generated.

Disclosure of utility model

The utility model aims to provide a circuit for pulse digital interference, which solves the problems of illegal interception and illegal use of wireless communication equipment in the background technology, and the problem of poor shielding effect of a conventional interference shielding device.

In order to solve the technical problems, the utility model adopts the following technical scheme:

A circuit for pulse digital interference, characterized by: the digital signal processing circuit comprises an FPGA, a DDS chip, a phase-locked loop voltage-controlled oscillation source, an IQ modulator, an analog switch, an RF switch, a low-pass filter, an amplifier and an attenuator, an I-path DAC error correction, a Q-path DAC error correction, a 90-degree bridge and a summing circuit; the FPGA, the I-path DAC error correction circuit, the Q-path DAC error correction circuit, the 90-degree bridge and the summing circuit form an IQ signal correction circuit;

The phase-locked loop voltage-controlled oscillation source, the analog switch, the RF switch, the low-pass filter, the amplifier and the attenuator form a random pulse generating circuit;

the DDS chip, the analog switch, the I-path DAC error correction, the Q-path DAC error correction, the 90-degree bridge and the summing circuit form a random IQ modulation signal circuit;

The RF switch includes a first RF switch and a second RF switch, and the analog switch includes a first analog switch and a second analog switch.

According to the above technical scheme, the IQ signal correction circuit specifically comprises: the FPGA is respectively connected with one end of the I-path DAC error correction circuit and one end of the Q-path DAC error correction circuit, and the other ends of the I-path DAC error correction circuit and the Q-path DAC error correction circuit are respectively connected with the summing circuit;

The summing circuit comprises a first summing circuit and a second summing circuit; the input end of the first summing circuit is connected with the Q-path DAC error correction circuit and the 90-degree bridge respectively; the output end of the first summing circuit is connected with the IQ modulator; the input end of the second summing circuit is respectively connected with the I-path DAC error correction circuit and the 90-degree bridge; the output end of the second summing circuit is connected with the IQ modulator;

The 90 DEG bridge is also connected to a random pulse generating circuit.

According to the technical scheme, the FPGA is respectively connected with the DDS chip and one end of a phase-locked loop voltage-controlled oscillation source; the other end of the DDS chip and the phase-locked loop voltage-controlled oscillation source are connected with the analog switch;

One end of the first analog switch is connected with the DDS chip, and the other end of the first analog switch is connected with one end of the second analog switch and the 90-degree bridge respectively; the other end of the second analog switch is connected with a phase-locked loop voltage-controlled oscillation source; the phase-locked loop voltage-controlled oscillation source is also connected with one end of a filter, the other end of the filter is connected with one end of a first amplifier, and the other end of the first amplifier is connected with one end of an attenuator; the other end of the attenuator is connected with the RF switch;

One end of the first RF switch is connected with the attenuator, and the other end of the first RF switch is respectively connected with the IQ modulator and the second RF switch; the IQ modulator is also connected to a second RF switch, which is also connected to a second amplifier that outputs the random IQ modulated signal to an external circuit for signal interference.

According to the above technical scheme, the random IQ modulation signal circuit specifically comprises: the FPGA is respectively connected with the phase-locked loop voltage-controlled oscillator and one end of the DDS chip, the other end of the DDS chip is connected with one end of the first analog switch, the other end of the first analog switch is connected with one end of the 90-degree bridge, and the other end of the 90-degree bridge is connected with the summing circuit;

The summing circuit comprises a first summing circuit and a second summing circuit; the input end of the first summing circuit is connected with the Q-path DAC error correction circuit and the 90-degree bridge respectively; the output end of the first summing circuit is connected with the IQ modulator; the input end of the second summing circuit is respectively connected with the I-path DAC error correction circuit and the 90-degree bridge; the output end of the second summing circuit is connected with the IQ modulator.

Further, the FPGA controls the DDS to generate random FSK, QPSK, MSK and sawtooth wave signals, controls the analog switch to an IQ modulation working state, generates I-path Q-path correction data to be input into the DAC, and enters the IQ modulator after the I-path Q-path correction signal is completely orthogonal, and comprises a local oscillation signal LO generated by a phase-locked loop voltage-controlled oscillator chip to form a random digital IQ modulation signal which is output to the power amplifier.

According to the technical scheme, the interference circuit further comprises a clock source, and the clock source is respectively connected with the DDS chip and the phase-locked loop voltage-controlled oscillator.

Compared with the prior art, the utility model has the following beneficial effects:

According to the scheme, the digital modulation RF signal is used as a carrier wave of high-speed switch pulse modulation, the FPGA outputs random continuous switch pulses with certain frequency to be loaded on the digital RF signal, and the synthesized digital modulation signal and the pulse signal are transmitted together. The transmitted RF signal contains digital modulation wave and pulse wave which interfere with the wireless signal, and has double suppression shielding effect on the wireless signal.

Drawings

FIG. 1 is a block diagram of the overall circuit of the present utility model;

FIG. 2 is a schematic block diagram of a random IQ modulated signal implementation of the present utility model;

Fig. 3 is a schematic block diagram of a random pulse signal implementation of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Example 1

As shown in fig. 1, a circuit for pulse digital interference is characterized in that: the digital signal processing circuit comprises an FPGA, a DDS chip, a phase-locked loop voltage-controlled oscillation source, an IQ modulator, an analog switch, an RF switch, a low-pass filter, an amplifier and an attenuator, an I-path DAC error correction, a Q-path DAC error correction, a 90-degree bridge and a summing circuit; the FPGA, the I-path DAC error correction circuit, the Q-path DAC error correction circuit, the 90-degree bridge and the summing circuit form an IQ signal correction circuit;

Further, the DDS chip adopts existing devices, such as an AD9835 chip.

Further, the phase-locked loop voltage-controlled oscillation source adopts the existing device, such as a MAX2870 chip.

Example two

As shown in fig. 1, the IQ signal correction circuit is specifically: the FPGA is respectively connected with one end of the I-path DAC error correction circuit and one end of the Q-path DAC error correction circuit, and the other ends of the I-path DAC error correction circuit and the Q-path DAC error correction circuit are respectively connected with the summing circuit;

The 90 DEG bridge is also connected to a random pulse generating circuit.

As shown in fig. 3, the random pulse generating circuit specifically includes: the FPGA is respectively connected with the DDS chip and one end of the phase-locked loop voltage-controlled oscillation source; the other end of the DDS chip and the phase-locked loop voltage-controlled oscillation source are connected with the analog switch;

The random IQ modulation signal circuit specifically comprises: the FPGA is respectively connected with the phase-locked loop voltage-controlled oscillator and one end of the DDS chip, the other end of the DDS chip is connected with one end of the first analog switch, the other end of the first analog switch is connected with one end of the 90-degree bridge, and the other end of the 90-degree bridge is connected with the summing circuit;

The interference circuit also comprises a clock source which is respectively connected with the DDS chip and the phase-locked loop voltage-controlled oscillator.

Generates modulation signals of digital modulation modes FSK, QPSK, MSK, etc., and VCO scanning voltage. The 90-degree bridge converts the digital signal of the DDS into an I/Q baseband signal with 90-degree phase error, and the I/Q mixer carries out quadrature modulation on various random digital modulation signals to a radio frequency carrier wave.

Example III

As shown in fig. 1, the dot frequency interference and the sweep frequency interference are realized by controlling a PLL special chip phase-locked loop voltage-controlled oscillator by an FPGA embedded with an MCU. An ultra-wideband phase-locked loop (PLL), an integrated Voltage Controlled Oscillator (VCO), capable of operating in integer and fractional divide-by-N modes. By matching with an external reference clock oscillator and a loop filter, a high-performance frequency synthesizer can be formed, a clock in a frequency range of 23.5MHz to 6.0GHz can be generated, and excellent phase noise and spurious indexes can be maintained. A multi-way integrated VCO and 1-128 output divider, which internally covers the 3000MHz to 6000MHz range, is used to achieve clock output in the ultra-wideband frequency range. The device provides a double-channel differential output driver, can be respectively set to provide output power of-4 dBm to +5dBm, and can control silence through software or hardware. Is controlled by a 3-wire serial port and is compatible with 1.8V control logic. The comb spectrum generator has the advantages of low power consumption, capability of generating sine waves with high frequency and the like, and can fulfill the functions of comb spectrum generator, frequency hopping and the like.

The digital modulation RF signal is used as carrier wave of high-speed switch pulse modulation, the FPGA outputs random continuous switch pulse with a certain frequency to be loaded on the digital RF signal, and the synthesized digital modulation signal and the pulse signal are transmitted together. The transmitted RF signal contains digital modulation wave and pulse wave which interfere with the wireless signal, and has double suppression shielding effect on the wireless signal.

When the digital modulation signal passes through the high-speed switch, the random pulse wave with a certain frequency output by the FPGA controls the high-speed switch to generate nanosecond high-power pulse wave, and when the digital modulation signal passes through the high-speed switch, the random pulse wave is modulated on the digital modulation signal.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present utility model, and the present utility model is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present utility model has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A circuit for pulse digital interference, characterized by: the digital signal processing circuit comprises an FPGA, a DDS chip, a phase-locked loop voltage-controlled oscillation source, an IQ modulator, an analog switch, an RF switch, a low-pass filter, an amplifier and an attenuator, an I-path DAC error correction, a Q-path DAC error correction, a 90-degree bridge and a summing circuit; the FPGA, the I-path DAC error correction circuit, the Q-path DAC error correction circuit, the 90-degree bridge and the summing circuit form an IQ signal correction circuit;

2. A circuit for pulse digital interference according to claim 1, characterized in that: the IQ signal correction circuit specifically comprises: the FPGA is respectively connected with one end of the I-path DAC error correction circuit and one end of the Q-path DAC error correction circuit, and the other ends of the I-path DAC error correction circuit and the Q-path DAC error correction circuit are respectively connected with the summing circuit;

The 90 DEG bridge is also connected to a random pulse generating circuit.

3. A circuit for pulse digital interference according to claim 1, characterized in that: the random pulse generating circuit specifically comprises: the FPGA is respectively connected with the DDS chip and one end of the phase-locked loop voltage-controlled oscillation source; the other end of the DDS chip and the phase-locked loop voltage-controlled oscillation source are connected with the analog switch;

4. A circuit for pulse digital interference according to claim 1, characterized in that: the random IQ modulation signal circuit specifically comprises: the FPGA is respectively connected with the phase-locked loop voltage-controlled oscillator and one end of the DDS chip, the other end of the DDS chip is connected with one end of the first analog switch, the other end of the first analog switch is connected with one end of the 90-degree bridge, and the other end of the 90-degree bridge is connected with the summing circuit;

5. A circuit for pulse digital interference according to claim 1, characterized in that: the interference circuit also comprises a clock source which is respectively connected with the FPGA, the DDS chip and the phase-locked loop voltage-controlled oscillator.