CN204131498U - A kind of phase-locked loop frequency synthesizer - Google Patents

Abstract

The utility model discloses a phase-locked loop frequency synthesizer, which comprises a frequency synthesis unit, a radio frequency switch, a frequency and phase detector, a first loop filter, a voltage-controlled oscillator, a prescaler, and a direct digital frequency synthesizer and the second loop filter; the input end of the frequency synthesis unit is used to receive the first-level reference frequency, the frequency synthesis unit synthesizes the first-level reference frequency and outputs i frequencies, and the radio frequency switch arbitrarily selects one of the i frequencies to be compatible with The frequency with which the output frequency is not a multiple is used as the secondary reference frequency; the frequency and phase detector compares the phase of the secondary reference frequency with the filtered feedback frequency, and outputs the phase detection voltage according to the comparison result; the first loop filter The phase voltage is filtered and processed to output the error voltage; the voltage-controlled oscillator converts the error voltage into an output frequency; the direct digital frequency synthesizer is used to perform fractional frequency division processing on the frequency output by the prescaler and output the feedback frequency. The utility model utilizes switching of a plurality of reference sources to effectively suppress stray.

Description

A Phase Locked Loop Frequency Synthesizer

technical field

The utility model belongs to the field of radio technology, in particular to a phase-locked loop frequency synthesizer.

Background technique

In modern electronic equipment and electronic systems, frequency synthesis technology has become an indispensable key technology and has been widely used in various fields. To this day, in order to meet different application requirements, various new frequency synthesis schemes are still emerging continuously.

As a key technology capable of generating high-quality sine waves, frequency synthesis technology has been widely used in electronic measurement systems and electronic equipment. In the receiver, the frequency source designed using frequency synthesis technology is used as a local oscillator, and the carrier signal is mixed and down-converted to a baseband signal; in the transmitter, the frequency source is also used as a local oscillator, and the baseband signal is mixed and up-converted to modulate to the carrier, and then transmit into the space through the antenna; in the electronic measurement system, the frequency source, as the reference signal of the entire measurement system, plays a vital role in the process of realizing various signal measurements. In these applications, the performance of the frequency source directly affects the performance of the entire system and equipment.

In the field of test and measurement, instrumentation manufacturers represented by Agilent and Roger & Schwartz have very deep technical accumulation in the field of frequency synthesis technology. Among many instruments and meters such as spectrum analyzers, signal analyzers, and network analyzers, the frequency synthesizer is the most fundamental core component. As the reference and working clock of the entire instrument, not only the frequency resolution and spurious suppression, but also the working bandwidth, frequency conversion time, frequency accuracy and stability, phase noise and other indicators will directly affect the test performance of the entire instrument. , it can be said that without a frequency synthesizer with superior performance, it is impossible to have a test and measurement equipment with superior performance.

In short, the frequency synthesizer is the core of the microwave radio frequency system, and its research, design, and use have penetrated into all aspects of the entire industry. The development of frequency synthesizers with wider operating bandwidth, higher frequency resolution, shorter frequency conversion time, higher frequency accuracy and stability, lower phase noise, higher spurious suppression, and smaller size is an important aspect of the entire RF and microwave industry. general trend.

Corresponding to different needs, there are various solutions for frequency synthesis technology, but in the final analysis, they are all based on three basic solutions: direct frequency synthesis, indirect frequency synthesis, and direct digital synthesis.

Direct Synthesis (Direct Synthesis, DS) technology is the earliest developed frequency synthesis technology. The key RF microwave components used are mixers, frequency multipliers, frequency dividers, comb generators, and filters. Using these devices, the input reference signal is added, subtracted, multiplied, and divided, and finally the required frequency signal is obtained through switching. Because only some passive diode devices are used, the frequency synthesizer designed with this scheme has the characteristics of low phase noise. At the same time, the frequency switching speed only depends on the switching speed of the switch, and can achieve fast switching at the nanosecond level. However, due to the use of nonlinear devices such as mixers, frequency multipliers, frequency dividers, and comb spectrum generators, there are complex spurious signals in the output signal. In order to suppress these spurs, it is necessary to plan the frequency band reasonably and use a large number of filters, but the effect is very limited. Therefore, the direct frequency synthesis technology has the disadvantages of large volume and poor spurious suppression.

Indirect frequency synthesis technology is a frequency synthesis technology with phase-locked loop (Phase-Locked Loop, PLL) as the core. The main components include: phase frequency detector (Phase Frequency Detector, PFD), loop low pass filter (Low Pass Filter, LPF), voltage controlled oscillator (Voltage Controlled Oscillator, VCO), frequency divider, etc. Using the negative feedback loop of the phase-locked loop, the output frequency is locked at N times the reference frequency. According to the difference of N, PLLs can be divided into fractional PLLs and integer PLLs, both of which have their own characteristics and are used in different occasions. The output bandwidth of the phase-locked loop frequency synthesizer is determined by the VCO, which has the advantage of frequency bandwidth. In addition, since the phase-locked loop presents the characteristics of a low-pass filter to the input reference, good spectral purity can be obtained by adjusting the loop bandwidth, avoiding the use of a large number of filters and reducing the volume. However, the switching time of the PLL frequency synthesizer is relatively slow due to the narrow loop bandwidth that limits the charging and discharging time of the capacitor at the voltage control terminal of the VCO. At the same time, because the phase detection noise of the PFD is added in the loop band, and the out-of-band phase noise is determined by the voltage-controlled oscillator with a relatively low Q value, the phase noise index of this scheme is relatively low compared with the direct frequency synthesis technology. Difference. With the development of phase-locked loop technology, different types of phase-locked loops have been developed, such as analog phase-locked loop, hybrid phase-locked loop, all-digital phase-locked loop, integrated phase-locked loop and software phase-locked loop.

Direct Digital Synthesis (DDS) technology is a brand-new technology produced with the continuous development of digital IC technology, analog IC technology and computer technology, and plays an increasingly important role in modern frequency synthesis technology. role. Its principle is to correspond the amplitude and phase of the output signal, and the phase and time, and the output amplitude is represented by the digital quantity stored in the ROM. Perform digital-to-analog conversion on the amplitude values in different ROM addresses at different times to obtain the analog amplitude value of the time slice. Therefore, signals of arbitrary waveforms can be synthesized theoretically. This technology has the advantages of relatively wide frequency bandwidth, high frequency resolution, and high integration. However, due to the influence of factors such as CMOS technology, the absolute frequency of its output is relatively low. At the same time, due to the defects of the technology itself, there are large spurious signals in the output signal. In addition, this technology has a strong digital modulation capability, so it is widely used in baseband signal processing. At present, this technology is often combined with indirect frequency synthesis technology to give full play to their respective advantages and design frequency synthesis schemes with complex and changeable structures.

As mentioned above, DDS adopts an all-digital structure, which has many advantages such as short frequency conversion time, high frequency resolution, and low phase noise, but its synthesis frequency is low, the output frequency spurious component is large, and the spectrum purity is not as good as that of phase-locked loop synthesis. PLL; PLL frequency synthesis technology has the advantages of high operating frequency, broadband, and good spectrum quality, but the frequency resolution is low and the frequency establishment time is short. Therefore, the two technologies are combined to form a DDS+PLL combined frequency synthesizer, which can learn from each other to realize frequency Synthesis can achieve effects that are difficult to achieve with a single technology. The key technical problem of the DDS+PLL combined frequency synthesizer is that the DDS output has a lot of spurious signals, especially the near-end spurs of the output signal cannot be filtered out by filters, which will affect the spectral purity of the system to a certain extent.

Generally speaking, if the system allows, reducing the bandwidth of the loop is conducive to the suppression of fractional frequency spurs. However, since the general system bandwidth is limited by indicators such as stability, shock resistance, and frequency conversion speed, it cannot be too narrow. Therefore, the reduction of fractional frequency division spurs mainly depends on proper phase compensation of the system. One of the phase compensation methods is to add the digital accumulator output of the fractional-N control section to the D/A converter. The converter provides a reverse current ramp to the output of the phase detector to offset the influence of the phase error generated by it. This correction is called analog phase interpolation (AnalogPhase Interpolation, API). When the loop is operating at fractional frequency, the API correction circuit can generate a signal that cancels the change in the output of the phase detector.

The correction circuit consists of a level shifter, a diode switch and a current source. These current sources are all connected to the input node of the current summing integral amplifier, and output after integral amplification. The current source provides a holding current to the node, and the current holding time depends on the negative pulse width of the input end. The API correction technology requires high precision, and the adjustment is very difficult. Only an API precision of 0.03% can reduce the modulation signal sideband to -70dBc.

A more effective method that has been researched and applied is the digital correction method. This fractional frequency divider using digital correction method is realized by ∑-△ modulator. The ∑-△ technology is to sample the input signal at a high-speed sampling frequency far exceeding the Nyquist frequency, and quantize each sampled signal. The number of bits often adopts 1 bit. Through this oversampling technology and the structure of the feedback loop itself, the quantization noise generated by the A/D conversion is shaped to make it change beyond the signal bandwidth. At the same time, the phase-locked loop itself is used for the input The low-pass filtering characteristic of the noise filters out the fractional frequency noise before it is added to the VCO, thus greatly improving the spectral purity of the fractional frequency divider. Although the ∑-△ technology solves the problem of fractional spurs, the spurs are still relatively large, reaching about -60dBc, and the spurious performance is still not high enough to meet certain technical requirements.

Utility model content

Aiming at the defects of the prior art, the purpose of this utility model is to provide a phase-locked loop frequency synthesizer, aiming at solving the problem that the prior art cannot avoid the spurious output frequency of the phase-locked loop near the integer multiple of the reference frequency.

The utility model provides a phase-locked loop frequency synthesizer, comprising: a frequency synthesis unit, a radio frequency switch, a frequency and phase detector, a first loop filter, a voltage-controlled oscillator, a prescaler, and a direct digital frequency synthesis device and a second loop filter; the input end of the frequency synthesis unit is used to receive a primary reference frequency f _r , and the frequency synthesis unit is used to synthesize the primary reference frequency f _r and output i frequency f _i , i is a positive integer greater than or equal to 2; the input end of the radio frequency switch is connected to the output end of the frequency synthesis unit, and the radio frequency switch is an i select one switch for any of the i frequencies Select a frequency that is not a multiple of the output frequency f _o as the secondary reference frequency f _t ; the input of the frequency and phase detector is connected to the output of the radio frequency switch, and the input of the first loop filter terminal is connected to the output terminal of the frequency and phase detector, the input terminal of the voltage controlled oscillator is connected to the output terminal of the first loop filter, and the input terminal of the prescaler is connected to the The output terminal of the voltage controlled oscillator, the input terminal of the direct digital frequency synthesizer is connected to the output terminal of the prescaler, and the input terminal of the second loop filter is connected to the fractional frequency divider Output terminal, the output terminal of the second loop filter is connected to the feedback terminal of the frequency and phase detector; the frequency and phase detector is used to use the secondary reference frequency f _t and the filtered feedback frequency f _f Perform phase comparison, and output phase detection voltage u _d (t) according to the comparison result; the first loop filter is used to output error voltage u _c (t) after filtering the phase detection voltage u _d (t); The voltage-controlled oscillator is used to convert the error voltage u _c (t) into an output frequency f _o ; the prescaler is used to divide the output frequency so that the frequency output by the prescaler is directly Within the operating frequency range of the digital frequency synthesizer; the direct digital frequency synthesizer is used to perform fractional frequency division processing on the output frequency of the prescaler and then output the feedback frequency; the second loop filter is used to feedback the output of the direct digital frequency synthesizer After the frequency is filtered, the frequency f _f is output to the frequency and phase detector.

Wherein, the frequency synthesis unit includes a phase-locked loop and i frequency dividers, the input of the phase-locked loop is used as the input of the frequency synthesis unit to receive the primary reference frequency f _r , each frequency divider The input end of each frequency divider is connected to the output end of the phase-locked loop, and the output end of each frequency divider is used as the output end of the frequency synthesis unit.

Wherein, the direct digital frequency synthesizer includes: a frequency register, an accumulator, a phase register, a sine look-up table, a D/A converter and an analog filter connected in sequence; the input end of the frequency register is used to store the frequency control word K, the output end of the phase register is also connected to the accumulator; the output end of the analog filter is used to connect the input end of the second loop low-pass filter; the accumulator, the sine The look-up table and the D/A converter are also respectively connected to the output terminals of the prescaler.

Wherein, the relationship between the frequency f _i output by the frequency synthesis unit and the output frequency f _o of the voltage-controlled oscillator is: the least common multiple of f ₁ , f ₂ ... f _i is greater than that of the phase-locked loop frequency synthesizer The highest output frequency f _omax , and the output frequency f _o is not in a multiple relationship with the secondary reference frequency f _t .

The utility model adopts the form of DDS interpolation phase-locked loop frequency division feedback, utilizes the switching of multiple reference sources, avoids the stray of the output frequency of the phase-locked loop near the integer multiple of the reference frequency, and can effectively suppress the stray.

Description of drawings

Fig. 1 is the schematic diagram of the phase-locked frequency synthesizer of the variable reference source that the utility model embodiment provides;

Fig. 2 is a functional block diagram of the phase-locked loop frequency division scheme provided by the embodiment of the present invention;

Fig. 3 is the DDS principle block diagram that the utility model embodiment provides;

Fig. 4 (a) is the phase detector phase accumulative process figure that the utility model embodiment provides;

Fig. 4 (b) is the VCO tuning terminal voltage figure that the utility model embodiment provides;

Fig. 5 is the phase noise analysis model combined with DDS principle that the utility model embodiment provides;

Fig. 6 (a) is the 100MHz reference frequency step distribution figure that the utility model embodiment provides;

Fig. 6(b) is a distribution diagram of 103 MHz reference frequency steps provided by the embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

The phase-locked loop frequency synthesizer provided by the utility model is a closed-loop automatic control system that can track the phase of the input signal. The phase-locked loop has its unique and excellent characteristics. It has carrier tracking characteristics. As a narrow-band tracking filter, it can extract Signal submerged in noise; can be used to provide a series of frequency sources with high stability; can perform high-precision phase and frequency measurement, etc.

Fig. 1 is a schematic diagram of a phase-locked frequency synthesizer with a variable reference source according to the utility model. In this scheme, we use a variable reference source to replace the traditional single reference frequency source. The phase-locked loop frequency synthesizer Including: frequency synthesis unit 1, radio frequency switch 2, phase frequency detector (PFD) 3, first loop filter 4, voltage controlled oscillator (VCO) 5, prescaler 6, direct digital frequency synthesizer ( DDS) 7 and the second loop filter 8; the input end of the frequency synthesis unit 1 is used to receive the primary reference frequency f _r , the input end of the radio frequency switch 2 is connected to the output of the frequency synthesis unit 1, and frequency and phase discrimination The input end of the device 3 is connected to the output end of the radio frequency switch 2, the input end of the first loop filter 4 is connected to the output end of the frequency and phase detector 3, and the input end of the voltage controlled oscillator 5 is connected to the first loop The output end of the filter 4, the input end of the prescaler 6 is connected to the output end of the voltage controlled oscillator 5, the input end of the direct digital frequency synthesizer 7 is connected to the output end of the prescaler 6, and the second loop The input end of filter 8 is connected to the output end of direct digital frequency synthesizer 7, and the output end of second loop filter 8 is connected to the feedback end of frequency discrimination phase detector 3; Wherein f _r is as a reference frequency, after Multiple frequencies are obtained by frequency synthesis, controlled by the radio frequency switch 2 to provide a variable output frequency, which is sent to the frequency and phase detector 3 as the secondary reference frequency f _i . At the initial moment, the output frequency of the direct digital frequency synthesizer 7 filtered by the second loop filter 8 is not equal to the secondary reference frequency, and the phase difference between the two signals increases continuously at the speed of the frequency difference. At this time, the phase-locked loop cannot lock. The output of the frequency and phase detector 3 is connected to the tuning terminal of the voltage-controlled oscillator 5 after passing through the first loop filter 4 . According to the phase relationship of the two input signals, the frequency and phase detector 3 constantly changes the voltage u _d (t), thereby changing the output frequency f ₀ of the voltage-controlled oscillator 5, and finally makes the direct digital frequency synthesizer 7 go through the second loop The output frequency of the filter 8 is equal to the reference frequency, and the phase remains consistent. At this time, the phase-locked loop enters the locked state, and the output of the frequency and phase detector 3 does not change anymore.

In the embodiment of the utility model, the relationship between the frequency f _i output by the frequency synthesis unit 1 and the output frequency f _o of the voltage-controlled oscillator 5 is: the least common multiple of f ₁ , f ₂ ... f _i is greater than the phase-locked loop frequency The highest output frequency f _omax of the synthesizer, and the output frequency f _o is not in a multiple relationship with the secondary reference frequency f _t .

When i is 2 as an example, two reference frequencies f ₁ and f ₂ can be provided to the phase detector, and which frequency to choose as the secondary reference frequency is determined according to the output frequency. The output frequency f _o and the input frequency f _t cannot be multiplied. And f ₁ *f ₂ >f _{omax -fomin} (output frequency bandwidth) is satisfied, when i is an integer of 3 or more, and so on.

Compared with the traditional frequency synthesizer, the utility model adds a frequency synthesis unit 1 and a radio frequency switch 2, and the output frequency f _o will appear a lot of near-end stray near the integer multiple of the input frequency of the phase detector, and the traditional methods are not very good To solve the stray problem, these two modules provide a variable reference source for the phase detector, so that the relationship with the input frequency f _i is not an integer multiple, so that the stray will be greatly reduced.

The design of the reference source is the key to this scheme. In order to achieve high resolution and low spurious performance in the 2.6GHz-3.2GHz frequency band, the least common multiple of multiple secondary reference frequencies must be above 600MHz. The PLL frequency division scheme is used in the utility model, and the principle block diagram is shown in Fig. 2. The PLL receives the primary reference frequency f _r and generates a high frequency signal, and then uses i frequency dividers with different frequency division ratios Divide this high-frequency signal into i different frequencies f _i , and finally use a radio frequency switch to select the frequency f _t . The phase-locked loop frequency division scheme has relatively low spurs and is easy to control, ensuring accurate locking of the subsequent phase-locked loop.

In order to better illustrate the phase-locked loop frequency synthesizer provided by the embodiment of the present invention, the working principle of each module will be described below.

In the specific implementation of the variable reference source, the frequency synthesis unit 1 and the radio frequency switch 2 in the utility model can be completed by selecting the clock chip AD9517-2 and the switch chip ADG904 of ADI Company. The chip AD9517-2 integrates PFD, VCO, and frequency divider. It only needs an external loop low-pass filter to form a complete phase-locked loop, and can use the built-in frequency divider and delay circuit to adjust the phase, frequency and The air ratio is adjusted. ADG904 is a four-in-one switch. In the on state, the insertion loss within the 100MHz bandwidth is less than 0.5dB, and the isolation is greater than 50dB. The four branches have a built-in 50 ohm load in the off state, and the port can be matched even when it is off.

When the built-in PLL of AD9517-2 works at 10MHz, the phase noise reaches -151dBc/Hz, and the output range of the built-in voltage-controlled oscillator is between 2.05GHz and 2.33GHz. The chip has four output signals, two of which are high-frequency low-voltage positive emitter-coupled logic (Low Voltage Positive Emitter-Couple Logic, LVPECL) signals, and the other two are configurable differential or single-ended output CMOS signals. The maximum output frequency of LVPECL is 2.9GHz, and the single-ended CMOS output can also reach 250MHz. The additional noise of the built-in frequency divider reaches -142dBc/Hz1KHz at 50MHz output, which can meet the requirements of low phase noise output and the input requirements of frequency and phase detectors.

In order to reduce the cost and system complexity, we choose to use the built-in voltage-controlled oscillator and set the output frequency of the VCO to 2300MHz. Through the frequency division by 2 of the built-in VCO frequency divider, the maximum output range is close to 1150MHz, and the target output range is exactly between 2300MHz and 3450MHz, which can achieve small steps in the whole band. At the same time, in order to reduce the power consumption of the chip, we gave up using the LVPECL output with high power, and chose two single-ended CMOS outputs, and selected two close frequencies of 46MHz and 50MHz as the reference frequency to reduce the post-stage phase-locking caused by the change of the reference frequency. Effect of loop bandwidth variation. Through calculation, it can be obtained that the phase noise of the voltage-controlled oscillator and the output phase noise of 50MHz are relatively ideal when the loop bandwidth of 200kHz is 70° and the phase margin is 70°.

The four-way output of AD9517-2 is connected with the four-way input of ADG904, and the output frequency selection of the RFC terminal is controlled through the control port to generate a secondary reference frequency, thus forming a complete variable reference signal source.

The frequency and phase detector 3 in the utility model is also called a phase comparator, which is used to compare the phase difference between the feedback signal u _f generated by the fractional frequency divider and the secondary reference signal u _i to generate an error voltage. In theory, it is usually analyzed by using the theory of sinusoidal simulation of PFD.

An analog multiplier is used here as a model for the PFD. Assuming that the multiplication coefficient of the phase detector is K _m (unit is 1/V), under the unified expression of ω ₀ t as a reference, the input signal u _i and the feedback signal u _f can be expressed as: u _i =V _i cos [ω ₀ t+θ ₁ (t)]; u _f =V _f cos[ω ₀ t+θ ₂ (t)]; where, the expressions of the secondary reference frequency f _i and the filtered feedback frequency f _f are respectively for: These two signals are added to both ends of the phase detector, and the output phase detection voltage u _d (t) after multiplication is: $u_d\left(t\right)=\frac{1}{2}{K}_m{V}_f{V}_i\sin [2{\mathrm{\ω}}_{0}t+{\mathrm{\θ}}_1\left(t\right)+{\mathrm{\θ}}_2\left(t\right)]+\frac{1}{2}{K}_m{V}_f{V}_i\sin [{\mathrm{\θ}}_1\left(t\right)-{\mathrm{\θ}}_2\left(t\right)];$ After the 2ω ₀ component is filtered out by the first low-pass filter, the obtained error voltage u _c (t) is only related to the phase difference between the input and the feedback signal; $u_c\left(t\right)=\frac{1}{2}{K}_m{V}_f{V}_i\sin [{\mathrm{\θ}}_1\left(t\right)-{\mathrm{\θ}}_2\left(t\right)].$

The first loop filter 4 and the second loop filter 8 in the utility model have the same structure, and the loop filter plays a role of low-pass filtering in the circuit, and more importantly, it plays a decisive role in the adjustment of the loop parameters. role. The loop filter is a linear circuit. Since the circuit is composed of linear resistors, linear capacitors, and operational amplifiers, it is a linear system. The transfer function of the loop low-pass can be calculated in the complex frequency domain. When there is no detailed analysis requirement for the loop low-pass, F(s) can be used instead. For the phase noise introduced by the VCO, the phase-locked loop has the characteristics of a high-pass filter. In order to suppress the noise of the VCO, it is hoped that the wider the loop bandwidth, the better, but for the noise introduced by the phase detector and frequency divider, the phase-locked loop presents a low-pass filter If you want to suppress their noise, you want the loop bandwidth to be as low as possible, so in order to take into account this contradiction, choose the phase noise intersection point as the loop bandwidth, so that their phase can be reasonably suppressed.

The voltage-controlled oscillator 5 in the utility model is used as the output element of the phase-locked loop, and plays a decisive role in the out-of-band phase noise of the output signal. The relationship between the output frequency of the ideal voltage-controlled oscillator and the tuning voltage is ω(t)=ω ₀ +K _v *u _c (t); there is a linear relationship between the output frequency of the ideal voltage-controlled oscillator and the tuning voltage, K _v is the tuning slope.

In the present utility model, DDS is used for fractional frequency division, so the principle of DDS is mainly introduced below: the principle of direct digital synthesis technology is to correspond the amplitude and phase of the output signal, and the phase and time, and the output amplitude is determined by A digital representation stored in ROM. By performing digital-to-analog conversion on the digital amplitude values in different ROM addresses at different times, the analog amplitude value of the time slice can be obtained, and the cycle goes back and forth to generate different waveforms. Therefore, signals of any form can be synthesized theoretically. The principle of direct digital frequency synthesizer (DDS) 7 concrete realizations is as shown in Figure 3, specifically comprises frequency register 71, accumulator 72, phase register 73, sine look-up table 74, D/A converter 75 and analog filter 76; The input end of the frequency register 71 is used to store the frequency control word K, the 72 input ends of the accumulator are connected to the output end of the frequency register 71, the input end of the accumulator 72 is connected to the output end of the frequency register 71, and the phase register The input end of 73 is connected to the output end of accumulator 72, the input end of sine lookup table 74 is connected to the output end of phase register 73, the input end of D/A converter 75 is connected to the output end of sine lookup table 74, analog filter The input terminal of the filter 76 is connected to the output terminal of the D/A converter 75, and the output terminal of the analog filter 76 is connected to the input terminal of the second loop low-pass filter 8.

F _r is the phase step frequency, and in the utility model, F _r is the output frequency of the prescaler 6, and the frequency register 71 is used to store the frequency control word K (step size), and the phase accumulator is the core of the DDS system, and it It consists of an accumulator 72 and an n-bit phase register 73. Every time a clock pulse comes, the phase register increases with a step size K. The amplitude quantization value of the sine function is stored in the sine lookup table 74 . Under the synchronization of _Fr , the accumulator 72 continuously accumulates the step size, and uses the accumulated result as the address of the ROM sinusoidal lookup table 74 to read the sinusoidal amplitude quantized value, and then converts it by the D/A converter 75 into an analog quantity, and finally output through an analog filter 76. The relationship between the output frequency and K, F _r , n is

The prescaler 6 between VCO and DDS is optional. The function of the prescaler is to adjust the output frequency of VCO to the operating frequency range of DDS. If the output range of VCO is within the operating frequency range of DDS, it can be No prescaler is used.

The function of the direct digital frequency synthesizer 7 is to realize the fractional frequency division, so first analyze the fractional spurious problem that will occur in the fractional frequency division, if the fractional frequency division ratio is NF (N represents the integer part, F represents the fractional part), directly The input reference frequency of the digital frequency synthesizer is F _PFD , then the output frequency is (NF)*F _PFD . It is worth noting that the fractional frequency division is realized in the form of averaging. In the frequency division process, in order to realize fractional NF frequency division, N frequency division will be performed in a certain period, and N+1 frequency division will be performed in another period, and so on. So no matter what state it is in, it is different from the reference frequency, thus creating ripple in the PFD output.

Intuitive analysis, the phase error takes 360° as the cycle, and the phase error increases by (0.F)*360° for each phase detection cycle, so the phase accumulation process is completed every 1/(0.F) phase detection cycle, as shown in the figure 4(a), the output voltage of the PFD after passing through the loop low-pass is proportional to the phase difference, so the output voltage curve as shown in Figure 4(b) can be obtained.

It can be seen from the figure that the output voltage of the voltage controlled oscillator is a sawtooth wave, where the Fourier transform expression of the sawtooth wave is,

$\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; \&pi;</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; sin</span>}\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; sin</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 3</span>}}\mathrm{<span\; class="notranslate">\; sin</span>}\mathrm{<span\; class="notranslate">\; 3</span>}\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}\mathrm{<span\; class="notranslate">\; sin</span>}\mathrm{<span\; class="notranslate">\; 4</span>}\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; )</span>$

Where T is the period of the sawtooth wave. It can be seen that there are not only DC components in the control voltage to keep the output frequency at (NF)*F _PFD , but also various sinusoidal components with frequency n/T. These sinusoidal components will modulate the output signal, producing modulation spurs.

Since a phase accumulation process is completed every 1/(0.F) phase detection period, T=1/(F _PFD *0.F) here. Therefore, modulation spurs will appear at (NF)*F _PFD left and right frequency offset m*(F _PFD *0.F) (m is a positive integer), deteriorating the performance of the phase-locked loop.

As an embodiment of the utility model, the fractional frequency division is realized by DDS. The output signal of the actual DDS product will contain more spurs. It mainly includes the strays introduced by the reference clock, the strays introduced by the phase truncation error and the strays introduced by the non-linearity of D/A conversion. When the phase step frequency F _r of the DDS is relatively high and the output frequency f _out is relatively low, the strays introduced by the nonlinearity of the D/A conversion can be minimized by choosing the DDS output frequency f _out reasonably. Therefore, the near-end spurious of DDS is mainly caused by the phase truncation error at this time.

Figure 5 shows the relationship between the phase truncation error Δφ _cut and the output Δφ _no . Figure 5 is combined with the DDS phase noise analysis model, assuming that the open-loop gain of the entire loop is G(s), because the address of the sinusoidal lookup table is linear, and the D/A converter is also linear under ideal conditions. From a control principle point of view, they can be considered as proportional links. From this, the equation of G(s) and the closed-loop transfer function H(s) of input and output can be obtained.

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; DAC</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; ROM</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

$\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; cut</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; DAC</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; ROM</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; DAC</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; ROM</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}$

Where A _DAC is the gain of the D/A converter, A _ROM is the gain of the sinusoidal lookup table, K _m is the gain of the phase detector, F(s) is the transfer function of the low-pass filter, and K _v is the tuning slope of the voltage-controlled oscillator . It can be seen from the closed-loop transfer function that the loop has a low-pass characteristic to the phase truncation error, and the gain in the passband is 1, and the stray of DDS will not be amplified by the loop.

The utility model overcomes the defects of the stray suppression method in the prior art, provides a stray suppression method effectively, adopts the form of DDS interpolation phase-locked loop frequency division feedback, and utilizes switching of multiple reference sources to avoid phase-locking Spurs where the loop output frequency is near integer multiples of the reference frequency.

When the output frequency is (NF)*F _PFD , fractional modulation spurs will appear at the left and right frequency offset m*(F _PFD *0.F) of the carrier. If the frequency deviation is smaller than the loop bandwidth, the low-frequency modulation signal can pass through completely, and the modulation spurs in the band are relatively large. But when m*(F _PFD *0.F) is much larger than the low-pass cut-off frequency, the modulation signal will be suppressed by the loop low-pass, and the modulation spurs will be greatly reduced. Therefore, in the vicinity of the integer multiple of the secondary reference frequency, the frequency band with larger spurs is modulated. In the prior art, taking a reference frequency of 100 MHz and a phase-locked loop bandwidth of 400 kHz as an example, when the output frequency is 3 GHz, a pure frequency spectrum can be obtained. However, in the prior art, when the output frequency is in the range of (3GHz-400kHz, 3GHz+400kHz) and other than 3GHz, the output spectrum will contain large modulation spurs.

The following describes the system for different numbers of reference sources.

(1) When the post-stage PLL has only one reference source (traditional)

Taking the reference frequency of 100MHz and the loop bandwidth of the PLL as 500kHz as an example, when the output frequency is 3GHz which is an integral multiple of 100MHz, a pure spectrum can be obtained. But when the output frequency is in the range of 3GHz±500kHz (except 3GHz), the output spectrum will contain a lot of modulation spurs. Beyond this range, modulation spurs will be gradually suppressed as the frequency deviation increases. So we can get Figure 6(a). When the frequency falls within the slash area (integer multiple of 100MHz ±500kHz), high resolution cannot be achieved, and in the blank area, small steps can be achieved.

(2) When the post-stage PLL has two variable reference sources

Take the reference frequency of 100MHz and 103MHz as an example, when using the reference frequency of 100MHz, when the output frequency falls in the area of the slash, we change the reference frequency to another frequency of 103MHz. Still taking the PLL loop bandwidth of 500kHz as an example, the backslash area of this frequency (integer multiple of 103MHz±500kHz) does not overlap with the original slash area of 100MHz. In this way, the original 100MHz slash area becomes the current 103MHz blank area, and the original modulation spurs will be suppressed by the loop low-pass, so the resolution of these areas can also be made very high, as shown in Figure 6(b). shown in the shaded area.

The key to using this solution is how to get frequency groups A, B, and even more without overlapping regions. It is not difficult to see that if a frequency C is numerically a common multiple of A and B, no matter which frequency is used as the reference frequency, it is impossible to achieve a small step near C. Therefore, the least common multiple of the reference frequency will determine the output bandwidth of the frequency synthesizer, and the least common multiple cannot fall within the required output frequency band. For example, the least common multiple of 100MHz and 103MHz is 10.3GHz, so high resolution cannot be achieved near 10.3GHz and its harmonics, and the widest output range is 10.3GHz.

(3) The post-stage phase-locked loop has multiple variable reference sources

A plurality of mutually prime reference frequencies are used to increase their least common multiple, and at the same time make the common multiple fall outside the range of the output frequency band, so that a higher output frequency bandwidth can be obtained.

The fractional phase-locked loop frequency synthesizer using the variable reference source solution solves the problem of poor spurious performance of the fractional phase-locked loop, and realizes a resolution higher than 100Hz within the frequency output range of 2.6GHz to 3.2GHz. The spurious suppression is higher than 75dBc, and has the characteristics of high resolution and low spurious.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements and modifications made within the spirit and principles of the utility model Improvements and the like should all be included within the protection scope of the present utility model.

Claims (5)

1. a phase-locked loop frequency synthesizer, it is characterized in that, comprising: frequency synthesis unit (1), radio-frequency (RF) switch (2), phase frequency detector (3), first ring path filter (4), voltage controlled oscillator (5), pre-divider (6), Direct Digital Frequency Synthesizers (7) and the second loop filter (8);

The input of described frequency synthesis unit (1) is for receiving one-level reference frequency f _r, described frequency synthesis unit (1) is for by one-level reference frequency f _rcarry out synthesis process and export i frequency f _i, i be more than or equal to 2 positive integer;

The input of described radio-frequency (RF) switch (2) is connected to the output of described frequency synthesis unit (1), and described radio-frequency (RF) switch (2) is that an i selects a switch, for selecting one and output frequency f arbitrarily in a described i frequency _odo not become the frequency of multiple proportion as secondary reference frequency f _t;

The input of described phase frequency detector (3) is connected to the output of described radio-frequency (RF) switch (2), the input of described first ring path filter (4) is connected to the output of described phase frequency detector (3), the input of described voltage controlled oscillator (5) is connected to the output of described first ring path filter (4), the input of described pre-divider (6) is connected to the output of described voltage controlled oscillator (5), the input of described Direct Digital Frequency Synthesizers (7) is connected to the output of described pre-divider (6), the input of described second loop filter (8) is connected to the output of described decimal frequency divider (7), the output of described second loop filter (8) is connected to the feedback end of described phase frequency detector (3),

Described phase frequency detector (3) is for by secondary reference frequency f _twith filtered feedback frequency f _fcarry out phase compare, and export phase demodulation voltage u according to comparative result _d(t); First ring path filter (4) is for described phase demodulation voltage u _dt () carries out output error voltage u after filtering process _c(t); Described voltage controlled oscillator (5) is for by described error voltage u _ct () is converted to output frequency f _o; Described pre-divider (6) for the frequency of described output frequency being carried out to scaling down processing and making pre-divider (6) export in the operating frequency range of Direct Digital Frequency Synthesizers (7); Direct Digital Frequency Synthesizers (7) carries out output feedack frequency after fractional frequency division process for the frequency exported pre-divider (6); Second loop filter (8) carries out output frequency f after filtering process for the feedback frequency exported Direct Digital Frequency Synthesizers (7) _fto described phase frequency detector (3).

2. phase-locked loop frequency synthesizer as claimed in claim 1, it is characterized in that, described frequency synthesis unit (1) comprises phase-locked loop and i frequency divider, the input of described phase-locked loop as the input of described frequency synthesis unit (1) for receiving one-level reference frequency f _r, the input of each frequency divider is connected to the output of described phase-locked loop, and the output of each frequency divider is as the output of described frequency synthesis unit (1).

3. phase-locked loop frequency synthesizer as claimed in claim 1, it is characterized in that, described Direct Digital Frequency Synthesizers (7) comprising: the frequency register (71) connected successively, accumulator (72), phase register (73), sine lookup table (74), D/A converter (75) and analog filter (76);

The input of described frequency register (71) is used for depositing frequency control word K, and the output of described phase register (73) is also connected with described accumulator (72); The output of described analog filter (76) is for connecting the input of described second loop low pass filter (8); Described accumulator (72), described sine lookup table (74) are also connected with the output of described pre-divider (6) respectively with described D/A converter (75).

4. the phase-locked loop frequency synthesizer as described in any one of claim 1-3, is characterized in that, the frequency f that described radio-frequency (RF) switch (2) exports _twith the output frequency f of described voltage controlled oscillator (5) _odo not become multiple proportion.

5. the phase-locked loop frequency synthesizer as described in any one of claim 1-3, is characterized in that, the pass that i frequency should meet is: f ₁, f ₂... f _ileast common multiple be greater than the highest output frequency f _omax.