CN221328928U - Oscillating circuit - Google Patents

Abstract

The application discloses an oscillating circuit, which comprises a BAW oscillator, a driving amplifying circuit and a tail current source; a drive amplification circuit coupled to the BAW oscillator to provide an oscillating drive signal; the BAW oscillator is used for responding to the oscillation driving signal to output a frequency signal; the tail current source has a first output terminal and a second output terminal for providing energy for driving the amplifying circuit to provide an oscillation driving signal; the driving amplification circuit includes at least one pair of transistors and at least one pair of variable capacitance units; in each pair of transistors, the grid electrode of each transistor is connected with the first output end of the tail current source through a resistor and connected with the drain electrode of the other transistor through a variable capacitance unit; the drain electrodes of the transistors are respectively connected with one output end of the BAW oscillator; the source of each transistor is grounded and connected to the second output of the tail current source. The oscillating circuit provided by the application can work under low power consumption, and has the advantages of low phase noise, low jitter performance and easiness in integration.

Description

Oscillating circuit

Technical Field

The application relates to the technical field of circuits, in particular to an oscillating circuit.

Background

In modern electronic systems, such as in the field of radio frequency communications, there is an increasing demand for GHz range frequency reference sources, which can reduce the closed loop gain of the system compared to conventional MHz frequency references, enabling a wider loop bandwidth, thereby providing lower jitter, lower phase noise and better frequency stability in the circuitry.

Currently, quartz crystal oscillators are generally selected as frequency references, however, quartz crystal oscillators operating in a high frequency (e.g., GHz or MHz) range are few, and are difficult to integrate due to unique manufacturing and packaging requirements, and the performance of the circuit such as phase noise and jitter is significantly poor.

Disclosure of utility model

In view of this, the present application provides an oscillating circuit so that the oscillating circuit can operate at low power consumption, and has advantages of low phase noise, low jitter performance, and easy integration.

The application provides an oscillating circuit, which is characterized by comprising a BAW oscillator with a BAW resonator, a driving amplifying circuit and a tail current source; the drive amplification circuit is coupled to the BAW oscillator to provide an oscillating drive signal; the BAW oscillator is configured to output a frequency signal in response to the oscillating drive signal; the tail current source has a first output terminal and a second output terminal for providing energy to the drive amplification circuit so that the drive amplification circuit provides the oscillating drive signal; wherein the drive amplification circuit includes at least one pair of transistors, at least one pair of variable capacitance units, and at least one pair of resistors; in each pair of transistors, the grid electrode of each transistor is connected with the first output end of the tail current source through a resistor, and is connected with the drain electrode of the other transistor through one variable capacitance unit; the drain electrode of each transistor is respectively connected with one output end of the BAW oscillator; the source of each of the transistors is grounded and connected to the second output of the tail current source. .

Optionally, the BAW oscillator further comprises a load capacitance; the load capacitance is connected in parallel with the BAW resonator.

Optionally, the at least one pair of transistors includes a first transistor and a second transistor, and the at least one pair of resistors includes a first resistor and a second resistor; the grid electrode of the first transistor is connected with the first output end of the tail current source through the first resistor, and is connected with the drain electrode of the second transistor through a variable capacitance unit, the drain electrode is connected with the first output end of the BAW oscillator, and the source electrode is grounded; the grid electrode of the second transistor is connected with the second output end of the tail current source through a second resistor, and is connected with the drain electrode of the first transistor through one variable capacitance unit, the drain electrode is connected with the second output end of the BAW oscillator, and the source electrode is grounded.

Optionally, the tail current source includes a current source, a third transistor, and a first capacitor; the input end of the current source is used for accessing bias voltage, and the output end of the current source is respectively connected with the drain electrode of the third transistor, the grid electrode of the third transistor and the first end of the first capacitor; the grid electrode of the third transistor is used as a first output end of the tail current source, and the source electrode of the third transistor is connected with the second end of the first capacitor and used as a second output end of the tail current source; the second end of the first capacitor is grounded.

Optionally, the variable capacitance unit includes a fourth transistor and a second capacitance; the grid electrode of the fourth transistor is used for being connected with control voltage, the drain electrode of the fourth transistor is respectively connected with the first end of the second capacitor and the drain electrode of one transistor in the driving amplifying circuit, and the source electrode of the fourth transistor is respectively connected with the second end of the second capacitor and the grid electrode of the other transistor in the driving amplifying circuit.

Optionally, the oscillating circuit further comprises a load unit; the load unit is respectively connected with the drain electrode of each transistor in the at least one pair of transistors to provide a direct current bias signal for each transistor.

Optionally, the load unit includes a first current providing structure and a second current providing structure arranged in mirror image; the first current supply structure is connected with the drain electrode of one transistor in the pair of transistors of the driving amplifying circuit so as to provide a direct current bias signal for the connected transistor; the second current supply structure is connected to the drain of the other transistor of the pair of transistors to provide a dc bias signal for the connected transistor.

Optionally, the first current providing structure includes a fifth transistor, a third resistor, and a third capacitor; the second current supply structure comprises a sixth transistor, a fourth resistor and a fourth capacitor; the source electrode of the fifth transistor is used for being connected with a set voltage and is connected with the first end of the third capacitor, the drain electrode of the fifth transistor is respectively connected with the drain electrode of the first transistor and the first end of the third resistor, and the grid electrode of the fifth transistor is respectively connected with the second end of the third capacitor, the second end of the third resistor and the grid electrode of the sixth transistor; the source electrode of the sixth transistor is used for being connected with a set voltage and is connected with the first end of the fourth capacitor, the drain electrode of the sixth transistor is respectively connected with the drain electrode of the second transistor and the first end of the fourth resistor, and the grid electrode of the sixth transistor is respectively connected with the second end of the fourth capacitor and the second end of the fourth resistor.

Optionally, the first current providing structure includes a sixth resistor, a first end of the sixth resistor is connected to a set voltage, and a second end of the sixth resistor is connected to a drain electrode of the first transistor; the second current supply structure comprises a seventh resistor, a first end of the seventh resistor is connected with the first end of the sixth resistor and connected with the set voltage, and a second end of the seventh resistor is connected with the drain electrode of the second transistor.

Optionally, the oscillating circuit further comprises an output unit, wherein the output unit is provided with a buffer module for buffering an accessed signal and/or a frequency dividing module for dividing the frequency signal; the buffer memory module comprises an inverter, a capacitor and a resistor, wherein the resistor is connected with the inverter in parallel; one end of the capacitor is connected with the input end of the inverter, and the other end of the capacitor is used as the input end of the buffer module and is connected with the output end of the BAW oscillator; the output end of the inverter is used as the output end of the buffer module; the frequency dividing module comprises a frequency divider.

The oscillating circuit provided by the application can work under low power consumption based on the BAW resonator, and has the advantages of low phase noise, low jitter performance and easiness in integration; by setting the capacitance parameters of the load capacitance and/or the variable capacitance unit, the frequency shift of the BAW resonator can be compensated, causing the BAW oscillator to output the desired frequency signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic circuit diagram of an oscillating circuit according to an embodiment of the application;

fig. 2 is a schematic circuit diagram of a variable capacitance unit according to an embodiment of the present application;

Fig. 3 is a schematic circuit diagram of an oscillating circuit according to another embodiment of the present application;

Fig. 4A and 4B are schematic circuit diagrams showing the output unit according to various embodiments of the present application.

Detailed Description

The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.

The present application provides an oscillating circuit, which, referring to fig. 1, may comprise a BAW oscillator 10, a drive amplifying circuit 20 and a tail current source 30.

The drive amplification circuit 20 is coupled to the BAW oscillator 10 to provide an oscillating drive signal.

The BAW oscillator 10 is configured to output a frequency signal in response to an oscillation drive signal; the frequency of the frequency signal may be determined according to the capacitance in the BAW oscillator 10 and/or the capacitance in the driving amplification circuit 20, and thus, the capacitance parameter in the BAW oscillator 10 and/or the capacitance parameter in the driving amplification circuit 20 may be controlled to output a desired frequency signal. Specifically, the BAW oscillator 10 may include a BAW resonator, and a plurality of capacitors disposed in parallel with the BAW resonator may be disposed in the BAW oscillator 10 and the driving amplification circuit 20, and the frequency of the frequency signal output from the BAW oscillator 10 may be adjusted by adjusting the magnitudes of the capacitors connected in parallel in the access circuit.

The tail current source 30 is used to provide energy (e.g., current and bias voltage) to the driver amplifier circuit 20 to ensure that the driver amplifier circuit 20 can provide a large oscillating drive signal.

The BAW resonator has the characteristics of high quality factor (Q), stable frequency output and easy integration, and the BAW resonator-based oscillation circuit 1 can operate at low power consumption and has the advantages of low phase noise, low jitter performance and easy integration.

In some embodiments, BAW oscillator 10 includes a BAW resonator and a load capacitance C1; the load capacitor C1 is used for compensating the frequency shift of the BAW resonator so as to enable the BAW resonator to output a desired frequency signal; the BAW resonator is configured to generate a frequency signal having a frequency based on the load capacitance C1 from the oscillation drive signal. In this embodiment, the BAW resonator is connected in parallel with the load capacitance C1. By providing a suitable load capacitance C1 it is possible to compensate for the frequency shift of the BAW resonator caused by factors such as residual errors from factory calibration, thereby causing the BAW oscillator 10 to output a desired oscillation frequency. In other examples, the load capacitance C1 may be omitted, and the oscillation frequency of the BAW oscillator 10 output is adjusted by the variable capacitance unit 21 described later.

In one example, a BAW resonator may include a first piezoelectric electrode, a second piezoelectric electrode, a piezoelectric film between the two piezoelectric electrodes, and the like. The output frequency of the BAW resonator may be in the GHz order, e.g. operating around 2.5 GHz.

In some embodiments, the driving amplification circuit 20 includes at least one pair of transistors (e.g., a first transistor M1 and a second transistor M2) and at least one pair of variable capacitance units 21; wherein each transistor is connected to a variable capacitance unit 21. Further, the driving amplifying circuit 20 may further include at least one pair of resistors (e.g., a first resistor R1 and a second resistor R2). In each pair of transistors, the grid electrode of each transistor is connected with the output end of the tail current source 30 through a resistor so as to be connected with energy signals such as bias voltage and the like, and the grid electrode of each transistor is also connected with the drain electrode of the other transistor through a variable capacitance unit 21; the drains of the transistors are respectively connected with one output end of the BAW oscillator 10; the source of each transistor is grounded.

In one example, as shown in fig. 1, at least one pair of transistors includes a first transistor M1 and a second transistor M2, and a pair of resistors includes a first resistor R1 and a second resistor R2. The grid electrode of the first transistor M1 is connected with the first output end of the tail current source 30 through a first resistor R1, and is connected with the drain electrode of the second transistor M2 through a variable capacitance unit 21, the drain electrode is connected with the first output end OUT1 of the BAW oscillator 10, and the source electrode is grounded; the gate of the second transistor M2 is connected to the first output terminal of the tail current source 30 through the second resistor R2, and is connected to the drain of the first transistor M1 through a variable capacitance unit 21, the drain is connected to the second output terminal OUT2 of the BAW oscillator 10, and the source is grounded. It will be appreciated that the first output of the tail current source 30 may provide a voltage (or current) signal or the like to the connected transistor to adjust the on state of the transistor. Specifically, the first transistor M1 and the second transistor M2 may each be an NMOS transistor, and a negative resistance is provided in the design to compensate for the loss of the BAW resonator and keep the BAW resonator oscillating. The control voltage VC is applied to the variable capacitance unit 21, thereby adjusting the impedance of the variable capacitance unit 21 and the capacitance in the drive amplification circuit 20 access circuit, which will be described in detail later. It will be appreciated that the drive amplification circuit 20 is connected in parallel with the BAW resonator and that the frequency of the frequency signal output by the BAW vibrator 10 can be adjusted by varying the capacitance in the drive amplification circuit 20 via the variable capacitance unit 21.

In other embodiments, the drive amplifying circuit 20 includes a pair of transistors (also referred to as a transistor pair, such as a first transistor M1 and a second transistor M2) shown in fig. 1; but more than two pairs of transistors (i.e., multiple transistor pairs) may be included, wherein two transistors of each transistor pair may be cross-coupled and multiple transistor pairs may be connected in parallel.

In some embodiments, as shown in fig. 1, tail current source 30 includes a current source IA, a third transistor M3, and a first capacitance C2. The input end of the current source IA is used for accessing the bias voltage Vbias, and the output end of the current source IA is respectively connected with the drain electrode of the third transistor M3, the grid electrode of the third transistor M3 and the first end of the first capacitor C2; the gate of the third transistor M3 is used as a first output end of the tail current source 30, and the source is connected with the second end of the first capacitor C2 and is used as a second output end of the tail current source 30; the second terminal of the first capacitor C2 is grounded. Wherein the bias voltage Vbias may be provided by a charge pump or other power supply circuit (device). In the tail current source 30 provided in the present embodiment, the gate of the third transistor M3 is connected to the current source IA, in which case, the gate of the third transistor M3 has a constant Direct Current (DC) voltage value due to the current source IA, thereby being able to provide constant bias voltages to the gates of the second transistor M2 and the first transistor M1.

The source of the third transistor M3 (i.e., the second output terminal of the tail current source 30) is connected to the branches of the first transistor M1 and the second transistor M2, respectively, i.e., the source of the third transistor M3 is connected to the source stages of the first transistor M1 and the second transistor M2, respectively. Thus, the tail current source 30 can be used to supply current to each branch of the oscillating circuit 1 (such as the branch where the first transistor M1 and the second transistor M2 are respectively located), so as to ensure that the driving amplifying circuit 20 can provide a larger oscillating driving signal.

It is understood that the tail current source 30 includes the current source IA and the third transistor M3 in fig. 1, but the constitution thereof is not limited thereto. The tail current source 30 for applying a constant DC voltage to the gates of the first and second transistors M1 and M2 may be modified to various forms, for example, the tail current source 30 may be implemented with a bipolar MOS and/or a resistor, the tail current source 30 may be formed as a current mirror, or the like, as required by those of ordinary skill in the art.

In one example, referring to fig. 1, the variable capacitance unit 21 includes a fourth transistor M6 and a second capacitance C5. The gate of the fourth transistor M6 is applied with a control voltage VC, and the second capacitor C5 is connected between the drain and the source of the fourth transistor M6; specifically, the gate of the fourth transistor M6 is used for accessing the control voltage VC, the drain is connected to the first end of the second capacitor C5 and the drain of one transistor (e.g., the first transistor M1) in the driving amplifying circuit 20, and the source is connected to the second end of the second capacitor C5 and the gate of another transistor (e.g., the second transistor M2) in the driving amplifying circuit 20. The control voltage VC is used to change the impedance of the fourth transistor M6 to affect the on state of the fourth transistor M6, thereby adjusting the magnitude of the equivalent capacitance of the variable capacitance unit.

In other examples, referring to fig. 2, each variable capacitance unit 21 may further include a fifth resistor R5 disposed between the source of the fourth transistor M6 and the second capacitor C5. In one example, the fourth transistor M6 may be an NMOS transistor. In other examples, the fourth transistor M6 in each variable capacitance unit 21 may be a PMOS transistor.

It will be appreciated that the oscillation frequency of the frequency signal output by the oscillating circuit 1 may be adjusted via a capacitor in the access circuit. For example, the fourth transistor M6 in each variable capacitance unit 21 is adjusted via the control voltage VC, in which case, adjusting the magnitude of the control voltage VC may change the impedance of the fourth transistor M6 to affect the on state of the third transistor M6, thereby adjusting the magnitude of the equivalent capacitance in the switching circuit of the variable capacitance unit 21 to change the overall capacitance in the switching circuit, thereby adjusting the oscillation frequency of the output signal (i.e., the output frequency signal) of the oscillating circuit 1.

Specifically, the corresponding relation between the frequency of the output signal and the control voltage VC can be obtained through the preliminary test of the oscillating circuit 1, and in the application process of the oscillating circuit 1, the magnitude of the control voltage VC is correspondingly adjusted according to the corresponding relation between the frequency of the output signal and the control voltage VC, so that the oscillating circuit 1 provides the output signal with the desired frequency to the back-end load.

In some embodiments, referring to fig. 1, the oscillating circuit 1 further comprises a load unit 40. The load unit 40 is configured to provide a dc bias signal for the transistors in the driving amplifying circuit 20, for example, the load unit 40 may be connected to the first transistor M1 and the second transistor M2 to provide the dc bias signal for the first transistor M1 and the second transistor M2, and the switching-in of the load unit 40 may ensure a minimum current required for the corresponding circuit to oscillate, because the current flowing through the circuit may vary according to the drain-source voltages of the first transistor M1 and the second transistor M2. The load unit 40 may also provide a load for driving the amplifying circuit 20 to provide gain for the BAW resonator.

In some embodiments, the load unit 40 may include several transistors, resistors, and the like. Specifically, referring to fig. 1, the load unit 40 may include a first current providing structure and a second current providing structure disposed in mirror image to provide dc bias signals to connected transistor pairs via two branches, respectively; specifically, the first current supply structure is connected to the drain of one transistor (e.g., the first transistor M1) of the pair of transistors of the driving amplification circuit 20 to supply a dc bias signal to the connected transistor; the second current supply structure is connected to the drain of the other transistor of the pair of transistors (e.g., the second transistor M2) to provide a dc bias signal to the connected transistor.

Specifically, the first current supply structure includes a fifth transistor M4, a third resistor R3, and a third capacitor C3; the second current supply structure includes a sixth transistor M5, a fourth resistor R4, and a fourth capacitor C4.

In the first current providing structure, the source of the fifth transistor M4 is configured to be connected to the set voltage VDD, and is connected to the first end of the third capacitor C3, the drain is respectively connected to the drain of the first transistor M1 and the first end of the third resistor R3, and the gate is respectively connected to the second end of the third capacitor C3, the second end of the third resistor R3, and the gate of the sixth transistor M5. The fifth transistor M4 is a PMOS transistor, a source of the fifth transistor M4 is connected to one end of the third capacitor C3 and is connected to the set voltage VDD, a gate of the fifth transistor M4 is connected to the other end of the third capacitor C3, and a gate of the fifth transistor M4 is connected to a drain of the fifth transistor M4 through the third resistor R3, and a drain of the fifth transistor M4 may be connected to a drain of the first transistor M1 and a gate of the second transistor M2.

In the second current providing structure, the source of the sixth transistor M5 is connected to the set voltage VDD, and is connected to the first end of the fourth capacitor C4, the drain is connected to the drain of the second transistor M2 and the first end of the fourth resistor R4, respectively, and the gate is connected to the second end of the fourth capacitor C4 and the second end of the fourth resistor R4, respectively. The sixth transistor M5 may be a PMOS transistor, where a source of the sixth transistor M5 is connected to one end of the fourth capacitor C4 and is connected to the set voltage VDD, that is, the source of the sixth transistor M5 is connected to a source of the fifth transistor M4 and is connected to the set voltage VDD, a gate of the sixth transistor M5 is connected to the other end of the fourth capacitor C4, a gate of the sixth transistor M5 is connected to a drain of the sixth transistor M5 through the fourth resistor R4, a gate of the sixth transistor M5 is connected to a gate of the fifth transistor M4, and a drain of the sixth transistor M5 is connected to a drain of the second transistor M2 and a gate of the first transistor M1.

In other embodiments, the load unit 40 may have other circuit structures, for example, the load unit 40 may include a plurality of resistors. Specifically, referring to fig. 3, the load unit 40 may include a first current providing structure and a second current providing structure disposed in mirror image to provide dc bias signals to the connected transistor pairs via two branches, respectively. The first current providing structure comprises a sixth resistor M6, wherein a first end of the sixth resistor M6 is connected with a set voltage VDD, and a second end of the sixth resistor M6 is connected with a drain electrode of the first transistor M1; the second current providing structure includes a seventh resistor M7, a first end of the seventh resistor M7 and a first end of the sixth resistor M6 are connected to the set voltage VDD, and a second end is connected to the drain of the second transistor M2. Thereby, the first transistor M1 and the second transistor M2 can be supplied with the dc bias signal.

The set voltage VDD may be a power supply voltage of a corresponding circuit, which may be provided by a related power supply circuit or power supply device, for example, LDO (low dropout regulator, low dropout linear regulator) or the like. It is understood that in order to have a negative resistance for oscillation in the drive amplification circuit 20, the gate-source voltages of the first transistor M1 and the second transistor M2 need to be not lower than the threshold voltages thereof. Since the gate-source voltages of the first transistor M1 and the second transistor M2 are determined by the tail current source 30, oscillation can be maintained even when the set voltage VDD is set to be lower than a value used in a conventional LC VCO (inductance-capacitance voltage controlled oscillator). Since the gate-source voltages of the first transistor M1 and the second transistor M2 are independent of the set voltage VDD, the oscillation circuit 1 can oscillate even when the set voltage VDD is lower than the threshold voltages of the first transistor M1 and the second transistor M2. However, since the current flowing through the circuit varies according to the drain-source voltages of the first transistor M1 and the second transistor M2, it is necessary to secure a minimum current of oscillation, for which the load unit 40 supplies the first transistor M1 and the second transistor M2 with a direct current bias signal. In some embodiments, the bias voltage Vbias may be the same voltage as the set voltage VDD, as provided by the same circuit or device. Of course, the bias voltage Vbias and the set voltage VDD may be different voltages, which are determined according to the operation requirement of the oscillating circuit 1.

It can be understood that each transistor in the oscillating circuit 1 of the present application operates in a switching state, and the quiescent current is low, so that the power consumption of the oscillating circuit 1 can be effectively reduced.

In some embodiments, the oscillating circuit further includes an output unit (not shown in the figure), where the output unit is connected to one of two output terminals of the BAW resonator (i.e. connected to the first output terminal OUT1 or the second output terminal OUT 2), respectively, so as to process the frequency signal output by the BAW resonator to obtain a desired frequency signal.

In this embodiment, referring to fig. 4A and 4B, the oscillating circuit 1 further includes an output unit 40, where the output unit 40 is connected to an output terminal (e.g., the first output terminal OUT1 and/or the second output terminal OUT 2) of the BAW oscillator 10, and processes the frequency signal output by the BAW oscillator 10 to better acquire the frequency signal.

In some embodiments, referring to fig. 4A, the output unit 40 may include a buffer module 41, where an input terminal of the buffer module 41 is connected to an output terminal of the BAW oscillator 10, so as to perform a buffering process on an output of the BAW oscillator 10, thereby enhancing driving capability, and thus better acquiring a frequency signal.

Specifically, the buffer module 41 includes an inverter, a capacitor, and a resistor, where the resistor is connected in parallel with the inverter; one end of the capacitor is connected with the input end of the inverter, and the other end of the capacitor is used as the input end of the buffer module 41 to be connected with one output end of the BAW oscillator 10; the output of the inverter may be used as the output of the buffer module 41.

Alternatively, the number of the buffer modules 41 may be two, namely, the first buffer module and the second buffer module. The first buffer module is connected to an output end (e.g., the first output end OUT 1) of the BAW resonator 11; the input terminal of the second buffer module is connected to the other output terminal (e.g., the second output terminal OUT 1) of the BAW oscillator 10.

In some embodiments, referring to fig. 4B, the output unit 40 may include a frequency division module 42, and the frequency division module 42 performs a frequency division process on the accessed frequency signal to obtain a signal having a target frequency. In some embodiments, an input of the frequency dividing module 42 may be connected to an output of the buffer module 41 to access the signal output by the buffer module, so as to obtain a signal having a target frequency. Specifically, referring to fig. 4B, an output end of the buffer module 41 is connected to an input end of the frequency dividing module 42, in this case, a frequency signal output by the BAW resonator is buffered by the buffer module 41 and then enters the frequency dividing module 42, and the frequency dividing module 42 performs frequency dividing processing on the frequency signal to output a signal with a target frequency. In the present embodiment, by setting the frequency dividing modules 42 of different frequency dividing ratios, signals of different frequencies can be output. For example, the frequency signal output by the BAW resonator 11 is 2.52GHz, the frequency dividing module 42 divides the frequency by 8, and the final output signal of the oscillating circuit 1 is 315MHz. The frequency dividing module 42 may employ a common frequency divider. Of course, without being limited thereto, the frequency dividing module 42 may also be directly connected to the output terminal of the BAW oscillator 10 to acquire a signal having a target frequency.

The oscillation circuit can work under low power consumption based on the BAW resonator, and has the advantages of low phase noise, low jitter performance and easy integration; by setting the capacitance parameters of the load capacitance C1 and/or the variable capacitance unit 21, the frequency shift of the BAW resonator can be compensated for, causing the BAW oscillator 10 to output a desired frequency signal.

Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.

That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.

In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (10)

1. An oscillating circuit, characterized in that the oscillating circuit comprises a BAW oscillator with a BAW resonator, a drive amplifying circuit and a tail current source;

the drive amplification circuit is coupled to the BAW oscillator to provide an oscillating drive signal;

The BAW oscillator is configured to output a frequency signal in response to the oscillating drive signal;

The tail current source has a first output terminal and a second output terminal for providing energy to the drive amplification circuit so that the drive amplification circuit provides the oscillating drive signal;

Wherein the drive amplification circuit includes at least one pair of transistors, at least one pair of variable capacitance units, and at least one pair of resistors; in each pair of transistors, the grid electrode of each transistor is connected with the first output end of the tail current source through a resistor, and is connected with the drain electrode of the other transistor through one variable capacitance unit; the drain electrode of each transistor is respectively connected with one output end of the BAW oscillator; the source of each of the transistors is grounded and connected to the second output of the tail current source.

2. The oscillating circuit of claim 1, wherein the BAW oscillator further comprises a load capacitance; the load capacitance is connected in parallel with the BAW resonator.

3. The oscillating circuit of claim 1, wherein the at least one pair of transistors comprises a first transistor and a second transistor, and the at least one pair of resistors comprises a first resistor and a second resistor;

The grid electrode of the first transistor is connected with the first output end of the tail current source through the first resistor, and is connected with the drain electrode of the second transistor through a variable capacitance unit, the drain electrode is connected with the first output end of the BAW oscillator, and the source electrode is grounded; the grid electrode of the second transistor is connected with the second output end of the tail current source through a second resistor, and is connected with the drain electrode of the first transistor through one variable capacitance unit, the drain electrode is connected with the second output end of the BAW oscillator, and the source electrode is grounded.

4. The oscillating circuit of claim 1, wherein the tail current source comprises a current source, a third transistor, and a first capacitance;

The input end of the current source is used for accessing bias voltage, and the output end of the current source is respectively connected with the drain electrode of the third transistor, the grid electrode of the third transistor and the first end of the first capacitor; the grid electrode of the third transistor is used as a first output end of the tail current source, and the source electrode of the third transistor is connected with the second end of the first capacitor and used as a second output end of the tail current source; the second end of the first capacitor is grounded.

5. The oscillating circuit of claim 1 or 4, wherein the variable capacitance unit comprises a fourth transistor and a second capacitance;

The grid electrode of the fourth transistor is used for being connected with control voltage, the drain electrode of the fourth transistor is respectively connected with the first end of the second capacitor and the drain electrode of one transistor in the driving amplifying circuit, and the source electrode of the fourth transistor is respectively connected with the second end of the second capacitor and the grid electrode of the other transistor in the driving amplifying circuit.

6. The oscillating circuit of claim 3, wherein the oscillating circuit further comprises a load unit;

the load unit is respectively connected with the drain electrode of each transistor in the at least one pair of transistors to provide a direct current bias signal for each transistor.

7. The oscillating circuit of claim 6, wherein the load cell comprises a mirrored first current providing structure and a mirrored second current providing structure;

the first current supply structure is connected with the drain electrode of one transistor in the pair of transistors of the driving amplifying circuit so as to provide a direct current bias signal for the connected transistor; the second current supply structure is connected to the drain of the other transistor of the pair of transistors to provide a dc bias signal for the connected transistor.

8. The oscillating circuit of claim 7, wherein the first current providing structure comprises a fifth transistor, a third resistor, and a third capacitor; the second current supply structure comprises a sixth transistor, a fourth resistor and a fourth capacitor;

The source electrode of the fifth transistor is used for being connected with a set voltage and is connected with the first end of the third capacitor, the drain electrode of the fifth transistor is respectively connected with the drain electrode of the first transistor and the first end of the third resistor, and the grid electrode of the fifth transistor is respectively connected with the second end of the third capacitor, the second end of the third resistor and the grid electrode of the sixth transistor;

The source electrode of the sixth transistor is used for being connected with a set voltage and is connected with the first end of the fourth capacitor, the drain electrode of the sixth transistor is respectively connected with the drain electrode of the second transistor and the first end of the fourth resistor, and the grid electrode of the sixth transistor is respectively connected with the second end of the fourth capacitor and the second end of the fourth resistor.

9. The oscillating circuit of claim 7, wherein the first current providing structure comprises a sixth resistor, a first terminal of the sixth resistor is connected to a set voltage, and a second terminal of the sixth resistor is connected to a drain of the first transistor; the second current supply structure comprises a seventh resistor, a first end of the seventh resistor is connected with the first end of the sixth resistor and connected with the set voltage, and a second end of the seventh resistor is connected with the drain electrode of the second transistor.

10. The oscillating circuit according to claim 1, further comprising an output unit having a buffer module for buffering an incoming signal and/or a frequency dividing module for dividing the frequency signal;

The buffer memory module comprises an inverter, a capacitor and a resistor, wherein the resistor is connected with the inverter in parallel; one end of the capacitor is connected with the input end of the inverter, and the other end of the capacitor is used as the input end of the buffer module and is connected with the output end of the BAW oscillator; the output end of the inverter is used as the output end of the buffer module; the frequency dividing module comprises a frequency divider.